JPS58191974A - Network testing machine - Google Patents

Network testing machine

Info

Publication number
JPS58191974A
JPS58191974A JP57075882A JP7588282A JPS58191974A JP S58191974 A JPS58191974 A JP S58191974A JP 57075882 A JP57075882 A JP 57075882A JP 7588282 A JP7588282 A JP 7588282A JP S58191974 A JPS58191974 A JP S58191974A
Authority
JP
Japan
Prior art keywords
network
circuit
terminal
under test
circuit network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57075882A
Other languages
Japanese (ja)
Inventor
Masaaki Yamamoto
正明 山本
Mitsuyoshi Inoue
井上 順義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP57075882A priority Critical patent/JPS58191974A/en
Publication of JPS58191974A publication Critical patent/JPS58191974A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To test always correctly a network to be tested, by comparing and collating the voltage measurement result of each measuring terminal with preliminarily stored terminal voltage data of every network to be tested to retrieve the type or the like of the network to be tested. CONSTITUTION:Terminals 111-11n of a network 10 to be tested are inserted to measuring terminals 61-6n, and the start switch of a CPU2 is turned on. The CPU2 controls a driver 15 to operate relays RL01-RL0n successively to cause a digital voltmeter 13 to measure voltages of measuring terminals 61-6n successively through a switching circuit 12, and results are sent to the CPU2 through a buffer memory 14. They are compared and collated with data of combinations of voltage values of every network stored in a memory 1 to retrieve the type or the like of the network 10 connected to measuring terminals. The CPU2 reads out information of the classification of each terminal of the pertinent network 10 in accordance with the retrieval result and controls a driver 7 to perform connections in a connecting circuit 5 similarly to a conventional case. Hereafter, the testing operation of the network 10 is performed similarly to the conventional case.

Description

【発明の詳細な説明】 索し得る回路網試験機に関するものである1第1図は従
来の回路網試験機の概略構成を示すもので、図中1は動
作手順のプログラムや抜数の被試験回路網毎に対応した
鴎用の真理値表、各端子の入力用・出力用等の種別の情
報を予め記憶したメモリ、2はメモリ1内のプロフラノ
、に従って各回路を制衡する中央処理装置(CPU)3
は被試験回路網へ送り出す試験信号を一時格納するレジ
スタ、4は被試験回路網の出力化+弓を読取るスキャナ
、5はレジスタ3及びスキャナ4を複数の測定端子に選
択的に接続する接続.]11路、6−1.6−2・・5
 − nは抜き差し式の測定端子、7は複数のリレーR
LI 1,RLI 2。
DETAILED DESCRIPTION OF THE INVENTION Related to a searchable circuit network testing machine 1 Figure 1 shows a schematic configuration of a conventional circuit network testing machine. A central processing unit that controls each circuit according to the truth table for each test circuit network, a memory that stores information on the type of each terminal such as input/output, etc. 2 is a profurano in memory 1 (CPU)3
4 is a register that temporarily stores the test signal sent to the circuit under test, 4 is a scanner that reads the output + bow of the circuit under test, and 5 is a connection that selectively connects the register 3 and scanner 4 to a plurality of measurement terminals. ] 11th route, 6-1.6-2...5
- n is a removable measurement terminal, 7 is multiple relays R
LI 1, RLI 2.

RL2 1,RL22・・・・RLn 1,RLr+2
を動作するドライバ、8−1.8−2  ・8−mは被
試験回路網の種類、品名、型番等(以)、4iに種類等
とのみ記す、、)を指定するだめの電鍵、9は電鍵8−
1. 8−2. 8 − mによる被試験回路網の指定
をCPU2に適応するテーク信号に変換する変換器、1
′0は電子回路パッケージ、IC搭載パッケージ、IC
等の被試験回路網、11−1.11−2・・・11−n
は被試験回路網10の信号入力・出力用の端子である、
、接続回路5はレジスタ3の信号を測定端子の方向への
み送るだめのゲート回路5 a−11、5a−215a
’−nlと、測定端子からの信号をスキャナ4の方向へ
のみ送るためのケート回路5a−12゜5a−22・・
5a−n2と、各測定端子とレジスタ3とを接続するた
めのリレーRLII、RL2]−RL n 1の接点5
b−11,51)−21−5b−nlと、各測定端子と
スキャナ4とを接続するためのリレーRL12.RL2
2−RLn2の接点5 b−12゜5b−22・・・5
b−n2とからなっている。
RL2 1, RL22...RLn 1, RLr+2
driver, 8-1.8-2 ・8-m is a telephone key for specifying the type, product name, model number, etc. (hereinafter, 4i is only written as type, etc.) of the circuit network under test, 9 is electric key 8-
1. 8-2. Converter 1 for converting the designation of the circuit network under test by 8-m into a take signal adapted to the CPU 2;
'0 is an electronic circuit package, IC mounted package, IC
Circuit network under test such as 11-1.11-2...11-n
are signal input/output terminals of the circuit network under test 10,
, the connection circuit 5 is a gate circuit 5a-11, 5a-215a that is designed to send the signal of the register 3 only in the direction of the measurement terminal.
'-nl and a gate circuit 5a-12゜5a-22 for sending the signal from the measurement terminal only in the direction of the scanner 4.
5a-n2 and relays RLII and RL2 for connecting each measurement terminal and resistor 3]-RL n 1 contact 5
b-11,51)-21-5b-nl and a relay RL12 for connecting each measurement terminal and the scanner 4. RL2
2-RLn2 contact 5 b-12゜5b-22...5
It consists of bn2.

次に上記装置を動作するには1ず画定端子6−1 +’
 6−22= 6− n K被試験回路網10の端子1
1−1.11−2・・11−nを差し込み、電鍵8−1
.8−2:・F3−mを人手を介して操作して回路網1
0の種類等を指定する。CPU2はメモリ1から該当す
る回路網10の各乾イの種別の情報を読出し、入力用の
端子とレジスタ3とが、1だ出力用の端子とスキャナ4
とがそれぞれ接続するようにドライバ7を匍)御し接続
回路5内の接続を行々わせる3に こで、例えは図示の回路網10の端イ11−1は入力用
、また端イ11−nは出力用であるからリレーRLII
及びRL n 2が動作し、子の接点5b−11及び5
b−n2が閉成し、レジスタ3と端子11−1、及びス
キャナ4と端イ11−nのそれぞれの接続ループが構成
される。
Next, to operate the above device, first connect the defining terminal 6-1 +'
6-22 = 6-n K terminal 1 of circuit network under test 10
Insert 1-1, 11-2...11-n, and press key 8-1.
.. 8-2:・Circuit network 1 by manually operating F3-m
Specify the type of 0. The CPU 2 reads information on each type of wire in the corresponding circuit network 10 from the memory 1, and sets the input terminal and register 3 to 1, the output terminal and scanner 4
For example, the end 11-1 of the circuit network 10 shown in the figure is for input, and the end 11-1 is for input, and 11-n is for output, so relay RLII
and RL n 2 operate, child contacts 5b-11 and 5
b-n2 is closed, and connection loops between the register 3 and the terminal 11-1, and between the scanner 4 and the terminal 11-n are formed.

接続回路5内の接続動作が終わばCP U 2はメモリ
1より読出した回路網10の真理値表に従ってレジスタ
3から試験信号(Qv、5vの論理レベルの信号)を回
路網10の各入力用の端子に送出し、各出力用の端子の
信号をスキャナ4で読取り、その信号を真理値表の出力
信号と比較する等の試験を実行する1、試験の結果、回
路網】0が正常であればCPU2は図示しない表示部に
これを表示し、異常(故障)であわば同様にこれを表示
する。
When the connection operation in the connection circuit 5 is completed, the CPU 2 sends a test signal (Qv, a signal at a logic level of 5v) from the register 3 to each input of the circuit network 10 according to the truth table of the circuit network 10 read from the memory 1. 1. As a result of the test, the circuit network 0 is normal. If there is, the CPU 2 displays this on a display section (not shown), and similarly displays this in case of an abnormality (failure).

ところで被試験回路網10はその種類等によって内部構
成がまったく異なり、各端イの入力用または出力用等の
種別も1つたく異なっている。従って回路網10の種類
等を指定する電鍵B−1,8−2・・8−mの操作を誤
ると、回路網】0の出力用の端子にレジスタ3が接続し
たり、入力用の端子にスキャナが接続したりして正しい
試験が行なえず、場合によっては被試験回路網10ある
いは試験機のレジスタ3、スキャナ4、CPtJ2等が
破壊する恐れがあった1゜本発明の目的はこれらの欠点
を除去するため各測定端子の電圧を測定する手段と、該
電a−世1+定結果を予め記憶した被試験回路網毎の端
イ市圧のデータと比較照合し測定端7に接続した被試験
回路網の種類等を検索する手段とを備えたもので、以下
図面について詳細に説明する、。
By the way, the internal configuration of the circuit network under test 10 is completely different depending on its type, and the type of each terminal (A) for input or output is also completely different. Therefore, if you make a mistake in operating the keys B-1, 8-2, . The purpose of the present invention is to solve these problems. In order to eliminate defects, a means for measuring the voltage at each measuring terminal was used, and the results were compared with pre-stored data on the terminal voltage for each circuit under test, and the voltage was connected to the measuring terminal 7. The device is equipped with means for searching for the type of circuit network under test, etc., and will be described in detail below with reference to the drawings.

第2図は本発明の一実施例を示すもので、図中第1図と
同一構成部分は同一符号をもって表わす。νIJち、1
はメモリ、2はCPU、3はレジスタ、4はスキャナ、
5は接続回路、6−1゜6−2−6−nは測定端ゴ、7
はドライバ、RLI 1゜RLI 2. RL21. 
RL22−RLn l、 RLn 2はリレー、10は
被試験回路網、11−1.11−2・・】1−nは回路
網10の端イ、12は切替え回路、13はデジタル・ボ
ルトメータ、14はバッファメモリ15は第2のドライ
バ(以下単にドライバ15と称す、) 、RLOl、R
LO2−RLOnはリレーである。
FIG. 2 shows an embodiment of the present invention, in which the same components as those in FIG. 1 are denoted by the same reference numerals. νIJchi, 1
is memory, 2 is CPU, 3 is register, 4 is scanner,
5 is the connection circuit, 6-1゜6-2-6-n is the measurement end go, 7
is the driver, RLI 1° RLI 2. RL21.
RL22-RLn l, RLn 2 is a relay, 10 is a circuit under test, 11-1, 11-2... ] 1-n is an end of the circuit network 10, 12 is a switching circuit, 13 is a digital voltmeter, 14 is a buffer memory 15 is a second driver (hereinafter simply referred to as driver 15), RLO1, R
LO2-RLOn are relays.

切替え回路12は徂j定端イ6−1.6−2・・6−n
の各端子をデジタル・ボルトメータ1:3に接続するだ
めのもので、リレーRLO]、RL02=RLOnの切
替え接点12−]、 l 2−2−12−nを有し、常
時は各測定端イを接続回路5に接続し、各リレーRLO
l、 RLO2=[LOnが動作した時、測定端子6−
1.6−2・・5− nがデジタル・ボルトメータ13
にそれぞれ接続する如くなっている。デジタル−ボルト
メータ13は検出した電圧をデジタル価に変換して出力
する。・〈ッ々メモリ14は測定端イ数に対応し/こ記
憶エリアを備えている。メモリ1は前述した内容の他に
被試験回路網毎に対応した各端子の魚信は状態(電源は
オン)における電圧値を記憶している。前述したように
被試験回路網はその種類等によって内部構成、各端子の
種別が異なるから、各被試験回路網の各端子の電圧価の
糾合せはその種類等によって個有のものとなっている、
The switching circuit 12 has fixed ends 6-1, 6-2...6-n.
It is for connecting each terminal of 1:3 to a digital voltmeter, and has relay RLO], RL02=RLOn switching contact 12-], l2-2-12-n, and normally each measuring terminal is Connect A to connection circuit 5, and connect each relay RLO
l, RLO2 = [When LOn operates, measurement terminal 6-
1.6-2...5-n is digital voltmeter 13
They are connected to each other. The digital voltmeter 13 converts the detected voltage into a digital value and outputs it.・〈〉memory 14 is provided with a storage area corresponding to the number of measurement ends. In addition to the above-mentioned contents, the memory 1 stores the voltage value of each terminal corresponding to each circuit network under test in the state (power is on). As mentioned above, the internal configuration and type of each terminal of the circuit network under test differ depending on its type, so the combination of voltage values at each terminal of each circuit network under test is unique depending on the type. There is,
.

次に上記装置を動作するには、1ず測定端イ6−1.6
−2−6−nに被試験回路網10の端イ11−1.1l
−2−11−nを差し込み、図示しなイCPU2の起動
スイッチをオンにする。CP ti 2はドライバ15
を制御してリレーRLOI、 R,LO2・・RLOn
を順次動作させ、回路網10か接続し−ている測定端子
6−1.6−2・5hの電圧を切替え回路12を介して
順次テシタル・ボルトメ−タに測定させる。該測定結果
はバッファメモリ14を介してCPU2に送られる,C
PU2は該測定結果をメモリ1内に記憶した各回路網毎
の電圧値の組合せのテークと比較照合し測定端イに接続
している回路網10の種類等を検索する。
Next, to operate the above device, 1.
-2-6-n is the end of the circuit network under test 10 11-1.1l
-2-11-n, and turn on the starting switch of CPU2 (not shown). CP ti 2 is driver 15
Control relays RLOI, R, LO2...RLOn
are operated in sequence, and the voltages at the measuring terminals 6-1, 6-2, and 5h connected to the circuit network 10 are sequentially measured by the digital voltmeter via the switching circuit 12. The measurement results are sent to the CPU 2 via the buffer memory 14.
The PU 2 compares and collates the measurement result with a take of combinations of voltage values for each circuit network stored in the memory 1, and searches for the type of the circuit network 10 connected to the measurement terminal A.

史にCPtJ2は該検索結果に従って該当する回路網1
0の各端子の種別の情報を読出し、ドライバ7を制御し
て接続回路5内の接続を前記従来例の場合と同様に行な
わせる,、以下、回路網10の試験動作については従来
例と同様であるから省略する。
Historically, CPtJ2 is the corresponding circuit network 1 according to the search results.
0 is read out, and the driver 7 is controlled to make the connection in the connection circuit 5 in the same manner as in the conventional example.Hereinafter, the test operation of the circuit network 10 is the same as in the conventional example. Therefore, it is omitted.

なお、回路網の種類等の検索において該電するものがな
い場合にはその旨を表示させるようにしてもよい。まだ
上記実施例において被試験回路網への電源は回路網を測
定端子に取付ける際、同時に供給されるものとする。
Note that when searching for the type of circuit network, etc., if there is no matching network, a message to that effect may be displayed. In the above embodiment, it is assumed that power is supplied to the circuit network under test at the same time as the circuit network is attached to the measurement terminal.

以上説明したように本発明によれば各測定端イの電圧を
測定する手段と、該電圧測定結果を予め記憶した被試験
回路網毎の端子電圧のテークと比較照合し測定端子に接
続した被試験回路網の種類等を検索する手段とを備えた
ので、従来のように人為的な誤操作による被試験回路網
の種類等の指定誤りがなく、常に正しい被試験回路網の
試験を行々うことができ、被試験回路網や試験機自体を
破壊する恐れがない等の利点がある3。
As explained above, according to the present invention, there is provided a means for measuring the voltage at each measurement terminal A, a means for measuring the voltage at each measurement terminal A, and a means for comparing and collating the voltage measurement result with a pre-stored take of the terminal voltage for each circuit network under test. Since it is equipped with a means to search for the type of circuit network under test, etc., there is no error in specifying the type of circuit network under test due to human error as in the past, and the correct circuit network under test can always be tested. There are advantages such as there is no risk of destroying the circuit network under test or the test equipment itself.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の説明に供するもので、第1図は従来の回
路網試験機の一例を示すブロック図、第2図は本発明の
回路網試験機の一実施例を示すブロック図である。 1・・メモリ、2・・CPU,3・・レジスタ、4・・
・スキャナ、5・接続回路、6・・測定端イ、7、15
・・ドライバ、10・・被試験回路網、11−1.11
−2・・・11−n・・被試験回路網10の端7、12
・・切替え回路、13・ テジタル・ボルトメータ、 
1 4・・ バッファメモリ、RLI 1,RLI 2
。 RL21,RL22・=RLnl,RLn2,RLOI
,R1、0 2 ・・ RLOn  ・・  リ  し
 ー   。 特許出願人  沖電気工業株式会社 代理人弁理士  吉 1)精 孝 第1図
The drawings serve to explain the present invention, and FIG. 1 is a block diagram showing an example of a conventional circuit network tester, and FIG. 2 is a block diagram showing an embodiment of the circuit network tester of the present invention. 1...Memory, 2...CPU, 3...Register, 4...
・Scanner, 5・Connection circuit, 6...Measurement end A, 7, 15
... Driver, 10... Circuit network under test, 11-1.11
-2...11-n...Ends 7, 12 of the circuit network under test 10
...Switching circuit, 13. Digital voltmeter,
1 4... Buffer memory, RLI 1, RLI 2
. RL21, RL22・=RLnl, RLn2, RLOI
,R1,02...RLOn...Re-shi. Patent applicant: Oki Electric Industry Co., Ltd. Patent attorney Yoshi 1) Takashi Sei Figure 1

Claims (1)

【特許請求の範囲】[Claims] 被試験回路網へ送シ出す試験信号を一時格納するレジス
タと被試験回路網の出力信号を読取るスキャナとを被緯
回路網の種類等に従って複数の測定端子に選択的に接続
し試験を行なう回路網試験機において、上記各測定端子
の電圧を測定する手段と、該電圧測定結果を予め記憶し
た被試験回路網毎の端子電圧のテークと比較助合し測定
端子に接続し7た被試験回路網の種類等を検索する手段
とを備えたことを特徴とする回路網試験機。
A circuit that performs tests by selectively connecting a register that temporarily stores the test signal sent to the circuit network under test and a scanner that reads the output signal of the circuit network under test to multiple measurement terminals according to the type of the circuit network under test. In the network testing machine, a means for measuring the voltage of each of the measurement terminals mentioned above, and a circuit under test connected to the measurement terminals for comparison and comparison with the terminal voltage of each circuit network under test in which the voltage measurement results are stored in advance. A circuit network testing machine characterized by comprising means for searching for network types, etc.
JP57075882A 1982-05-06 1982-05-06 Network testing machine Pending JPS58191974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57075882A JPS58191974A (en) 1982-05-06 1982-05-06 Network testing machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57075882A JPS58191974A (en) 1982-05-06 1982-05-06 Network testing machine

Publications (1)

Publication Number Publication Date
JPS58191974A true JPS58191974A (en) 1983-11-09

Family

ID=13589095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57075882A Pending JPS58191974A (en) 1982-05-06 1982-05-06 Network testing machine

Country Status (1)

Country Link
JP (1) JPS58191974A (en)

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