JPS58191658U - 発光素子リ−ドフレ−ムの樹脂液塗布装置 - Google Patents
発光素子リ−ドフレ−ムの樹脂液塗布装置Info
- Publication number
- JPS58191658U JPS58191658U JP1982089692U JP8969282U JPS58191658U JP S58191658 U JPS58191658 U JP S58191658U JP 1982089692 U JP1982089692 U JP 1982089692U JP 8969282 U JP8969282 U JP 8969282U JP S58191658 U JPS58191658 U JP S58191658U
- Authority
- JP
- Japan
- Prior art keywords
- resin liquid
- light emitting
- emitting device
- liquid coating
- lead frames
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は発光素子リードフレームを一部省略して示す正
面図、第2図は発光素子リードフレームの要部を示す斜
視図、第3図a ”−cは従来のプレディップ工程を示
す説明図、第4図はプレディップ工程後の発光素子リー
ドフレームの要部を示す斜視図、第5図は本考案の実施
例における発光素子リードフレームの樹脂液塗布装置の
使用状態を一部断面で示す斜視図である。 11・・・真空容器、fla・・・底板、llb・・・
蓋、12・・・ヒンジ、13・・・パレット受は台、1
4・・・樹脂液槽、15・・・支持棒、16・・・樹脂
液、17・・・パレット、18・・・発光素子リードフ
レーム。 第3図 1 ′ 21 1「 第4図 ?98 s−41g
面図、第2図は発光素子リードフレームの要部を示す斜
視図、第3図a ”−cは従来のプレディップ工程を示
す説明図、第4図はプレディップ工程後の発光素子リー
ドフレームの要部を示す斜視図、第5図は本考案の実施
例における発光素子リードフレームの樹脂液塗布装置の
使用状態を一部断面で示す斜視図である。 11・・・真空容器、fla・・・底板、llb・・・
蓋、12・・・ヒンジ、13・・・パレット受は台、1
4・・・樹脂液槽、15・・・支持棒、16・・・樹脂
液、17・・・パレット、18・・・発光素子リードフ
レーム。 第3図 1 ′ 21 1「 第4図 ?98 s−41g
Claims (1)
- 開閉自在な蓋を有する真空容器と、該真空容器内に配設
され、複数の発光素子リードフレームか装着されたパレ
ットを支持するパレット支持部材と、前記真空容器内に
、収容された樹脂液が前記リードフレームと離接するよ
うに上下動可能に配設された樹脂液槽とを具備したこと
を特徴とする発光素子リードフレームの樹脂液塗布装置
。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982089692U JPS58191658U (ja) | 1982-06-16 | 1982-06-16 | 発光素子リ−ドフレ−ムの樹脂液塗布装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982089692U JPS58191658U (ja) | 1982-06-16 | 1982-06-16 | 発光素子リ−ドフレ−ムの樹脂液塗布装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58191658U true JPS58191658U (ja) | 1983-12-20 |
Family
ID=30098285
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982089692U Pending JPS58191658U (ja) | 1982-06-16 | 1982-06-16 | 発光素子リ−ドフレ−ムの樹脂液塗布装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58191658U (ja) |
-
1982
- 1982-06-16 JP JP1982089692U patent/JPS58191658U/ja active Pending
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