JPS58190113A - Delay equalizer - Google Patents

Abstract

PURPOSE:To ensure the practical performance to an intermediate frequency with a simple pattern structure, by forming at least a part of an inductance element on a dielectric substrate in the form of a planar pattern. CONSTITUTION:Coils L1, L2 and L3 are formed on a dielectric substrate in the form of planar patterns 1-3 to constitute a delay equalizer of a bridge T-shaped circuit. Then capacitors C4 and C5 are provided on the substrate by means of chip capacitors 4 and 5. An earth plate 6 is connected to an earth structure formed on the rear side of the substrate with a screw 7.

Description

Detailed Description of the Invention (a) Technical field of the invention The present invention relates to ultra-high frequency radio illumination such as sub-millimeter and mi+) wave bands.
Delay ring (also known as phase equalizer) used in communication equipment
It is related to.

(b) Background of the Technology In wireless communication systems using frequencies such as quasi-millimeter waves and millimeter waves, the UHF band of several hundred MHz is used as an intermediate frequency. In wireless communication using such high frequency intermediate frequency No. 4a, a conventional variable delay equalizer (19.16/1989)
0) becomes difficult to apply.

(C) Prior art and problems When compensating the quality of a transmission signal system, it is necessary to stabilize not only the amount of attenuation but also the group propagation time of signals within the band within the filtering band. is used. A constant resistance reactance symmetric lattice circuit is known as a basic circuit of this delay equivalent circuit, but in practice, a circuit equivalently converted to a bridging T-type circuit having a grounded end is generally used.

Such a bridge T-shaped circuit is generally a lumped constant circuit that uses a coil for inductance and a capacitor for capacitance. In conventional delay equalizer circuits, a coil used only in a relatively low frequency region of 140 MHz or less uses a magnetic material, such as a ferrite core, as a core. However, in a high frequency range of several hundred MHz or more, the number of turns in the coil decreases and the loss due to the core increases, making it impossible to use the conventional bobbin structure. That is, the conventional V
For the inductance of a delay equalizer circuit operating in the HF band, a coil is wound around a suitable bobbin having a magnetic core.

However, in quasi-millimeter-wave and millimeter-wave wireless devices that use a frequency in the 700 MHz band as an intermediate frequency, the number of turns of the coil is less than one turn of the conventional bobbin, and it is no longer possible to use the same bobbin structure as before. It's coming.

(d) Object of the Invention The present invention enables practical use of the above-mentioned intermediate frequency of 700 MHz with a simple pattern structure.

(e) Structure of the Invention The present invention provides a lumped constant bridging T-type circuit delay equalizer characterized in that at least a part of the inductance element is formed as a planar pattern on a dielectric substrate. It accomplishes its purpose.

(f) Embodiment of the Invention FIG. 1 shows a basic circuit diagram of a delay equalizer of a bridge T-type circuit. The coil has a Y-connection configuration.

FIG. 2 shows a block diagram of the circuit of FIG. 1 which is constructed of a planar pattern. In the figure, pattern 1 is a coil Ll shown in FIG. 1, and pattern 2 is a coil L1 shown in FIG. 1, and pattern 2 is a coil L1 shown in FIG.

Capacitors 04 and C5 can be constructed by chip capacitors 4 and 5 on a flat substrate. The ground plate 6 is connected by a screw 7 to a ground structure formed on the back surface of the board.

FIG. 3 shows another basic circuit diagram of a bridge T-type delay equalizer. The coil is Δ-connected.

FIG. 4 shows a block diagram of the circuit of FIG. 3 which is constructed of a plane pattern. To explain this in comparison with FIG. 3, since the coil Lll shown in the upper part of FIG. 3 can have one turn, a predetermined inductance can be obtained by the pattern 11 in FIG. 4.

Coil L12 shown in FIG. 3 corresponds to pattern 12, and coil L13 shown in FIG. 3 corresponds to pattern 13, so that appropriate inductance can be obtained.

- 21 capacitors C14 and C15 can be constructed on a flat substrate by chip capacitors 14.15.

The ground plate I6 is connected by a screw 17 to a ground conductor formed on the back surface of the board.

FIG. 5 is an explanatory diagram of a method for adjusting inductance formed by a planar pattern according to the present invention. Here, a piece 18 of a predetermined shape made of dielectric material is placed on or near the coil pattern to change the electric field distribution and adjust the inductance.
Fix 8 with adhesive.

FIG. 6 is a perspective view showing a specific structure of a delay equalizer manufactured according to the present invention. A metal case 21 has a planar pattern formed on a dielectric substrate 22, and a drinking vessel with a predetermined delay whose input/output terminals are constituted by microstrip lines 25 is mounted and fixed inside the case 21. A waveguide 23 is used as a conductor for the external line, and the case 21 is sealed with a lid 24 (obviously not shown).

Note that the dielectric substrate is selected depending on the circuit conditions, and no specific material is selected.

(g) Effects of the Invention According to the present invention, the delay equalizer circuit is realized with a simple pattern and structure, and is excellent not only in economy but also in quality stability and reliability. It can contribute to the practicality and economic efficiency of wave communication.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of a delay equalizer with a bridge T-type circuit;
The diagram shows the configuration of the circuit shown in Figure 1, which is composed of a plane pattern.
Figure 3 is another basic circuit diagram of the delay equalizer of the bridged T-type circuit.
FIG. 4 is a block diagram of the circuit shown in FIG. 3 which is made up of a planar pattern, FIG. 5 is an explanatory diagram of an inductance adjustment method formed using a planar pattern according to the present invention, and FIG. FIG. 2 is a perspective view showing a specific structure of a slow equalizer. In the figure, 1.2.11.12.13 are patterns, 4.
5.14.15 is a chip capacitor, 6.16 is a grounding plate, 7.17 is a splash, 18 is a section, 21 is a case, 22
23 is a dielectric substrate, 23 is a conduit, and 24 is a lid. Fat 1 figure C4 躬7 figure 尤zu figure I4

Claims (1)

[Claims] A lumped constant type bridging T-type circuit delay equalizer, characterized in that at least a part of an inductance element is formed as a planar pattern on a dielectric substrate.