JPS5818876B2 - Inverter touch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter device having an improved commutation failure prevention circuit that ensures reliable commutation even when starting up a current source constant frequency inverter and when the output voltage is low. .

FIG. 1 shows a conventionally used current source inverter.

The thyristors 4, 5, 6, and 7 constitute an inverter, and the thyristors 4, 7 and 5, 6 are fired simultaneously at a constant cycle alternately.

Capacitor 9 and resistor 10 constitute a capacitive load,
The energy stored in the capacitor 9 causes the thyristors 4, 7 and 5, 6 to commutate.

The DC power supply 1 is a variable DC power supply such as a converter.

The reactor 3 is a DC reactor that supplies constant current to the inverter.

Now, when the thyristors 4 and 7 are conducting, the current from the DC power supply 1 is as follows:
The flow goes from resistor 10 to thyristor 7, and charge is stored in capacitor 9 with the polarity shown in FIG. A closed circuit consisting of capacitor 9 and capacitor 9 → thyristor 6 → thyristor 7 → capacitor 9 is formed.

The charge stored in the capacitor 9 forms a resonant circuit between the capacitor 9 and stray inductance such as the inductance of the connection of these closed circuits, and current flows from the capacitor 9 until the currents of the thyristors 4 and 7 become zero.

When the currents of thyristors 4 and 7 become zero, thyristor 4
, 7 become non-conductive, the voltage of capacitor 9 passes through thyristors 5 and 6, and a reverse voltage is applied to thyristors 4 and 7, so that thyristors 4 and 7 are turned off.

Since the thyristors 5 and 6 are in a conductive state, the current from the DC power supply 1 flows from the reactor 3 to the thyristor 5 to the capacitor 9.
Flows from resistance 10 to thyristor 6.

Therefore, the voltage across the capacitor 9 gradually goes from the polarity shown in FIG. 1'' to zero and then to the polarity opposite to that shown in FIG.

Next, when the thyristors 4 and 7 are ignited, the thyristors 5 and 6 become non-conductive through the same process as described above.

Here, if we pay attention to the thyristor 4, the voltage of the capacitor 9 is applied as a reverse bias to the thyristor 4 through the thyristor 5 during the period when the thyristor 4 becomes non-conductive and the voltage of the capacitor 9 changes from the polarity shown in FIG. 1 to zero. ing.

This period is the reverse bias period of the thyristor 4.

Therefore, if the current supplied from the DC power source 1 is constant, it is clear that the larger the voltage of the capacitor 9 during commutation, the longer the reverse bias time will be.

Generally, a certain value or more is required when the CyRisk is reverse biased.

Therefore, as the voltage of the capacitor 9 decreases, the reverse bias time becomes shorter, and eventually the SIRISK becomes insufficient in its commutation ability, leading to commutation failure.

Further, the thyristor 8, the DC power supply 2, the resistor 12, and the capacitor 11 constitute an initial charging circuit.

This circuit will be used to explain startup.

First, the voltage of the DC power supply 2 is applied to the capacitor 11 through the resistor 12.

Thereafter, thyristors 8 and 7 are ignited, and a voltage is applied to capacitor 9 with the polarity shown in FIG.

At this time, the thyristor 8 naturally turns off.

After that, thyristor 6.5-→thyristor 4,7→thyristor 6.5 is fired, and the inverter is activated.

As described above, in the conventional circuit, at startup, a voltage is applied to the capacitor 9 using the initial charging circuit, and commutation is reliably performed using this voltage.

Further, when the output voltage of the DC power source 1 is low, if the inverter is driven with a constant frequency, the inverter output voltage becomes low, and therefore the voltage of the capacitor 9 also becomes low, causing commutation failure.

This invention starts without using the above-mentioned initial charging circuit consisting of a capacitor, a resistor, and a DC power supply, and is equipped with a commutation failure prevention circuit to ensure stable commutation even at low output voltages. be.

The outline of the commutation failure prevention circuit according to the present invention will be explained.

This circuit detects the inverter output voltage, and commutation is possible when this output voltage exceeds a certain level.

The inverter is commutated by ANDing the signal from the constant frequency oscillator.

Therefore, at startup, the inverter output voltage rises slowly due to the reactor 3, so that when the commutation signal from the oscillator arrives, the capacitor 9 is still high.

The voltage is low and there is no sufficient commutation ability.

Therefore, when the inverter output voltage exceeds a certain value that allows commutation, the thyristor on the non-conducting side is fired to perform commutation.

Furthermore, when the output voltage of the DC power supply 1 becomes low and the commutation capability is lost, the output voltage of the DC power supply 1 increases and commutation is performed when the inverter output voltage exceeds a certain value.

Generally, the DC power supply 1 often uses a converter, but
Since the converter output voltage includes ripples that are an integral multiple of the commercial frequency, the output voltage becomes low and causes commutation failure.

Even in such a case, if the circuit of the present invention is used, the inverter can be operated stably.

Also, if the commutation capacity is sufficient, the commutation signal from the oscillator will come after the inverter output voltage reaches a certain value or higher, so
At this oscillation frequency, the inverter can supply AC power to the load.

Next, a block diagram of an applied embodiment of the commutation failure prevention circuit of the present invention is shown in FIG. 2, and a time chart thereof is shown in FIG.
As shown in the figure.

In FIG. 2, parts with the same numbers as in FIG. 1 are the same as in FIG. 1, so their explanation will be omitted.

The comparator circuit 20 is a comparator circuit that becomes high level when the voltages at the input terminals a and b of the inverter exceed a certain value EB.

A charging circuit is formed by a constant voltage source 21, a resistor 22, and a capacitor 24, and a transistor 23 is connected to a capacitor 24.
This is a discharge circuit.

The comparator circuit 25 sets the voltage of the capacitor 24 to a certain constant value ED.
The comparator becomes high level when it is above.

Constant voltage source 21, resistor 22, capacitor 24, comparison voltage E
D determines the inverter output frequency during normal operation.

Reference numeral 26 is an AND circuit that becomes high level when both comparators 20 and 25 are high and in a low state.

The monostable multi-by-break 27 is triggered by the rising edge of the AND circuit 26.

This multi-by-break 27 drives the base of the transistor 23 and discharges the voltage of the capacitor 24.

The flip-flop 28 is also driven by a monostable multi-bibreak 27, the output of which is connected to a gate circuit which fires the thyristors 4,7 and 5,6.

Next, the commutation failure prevention circuit shown in FIG. 2 will be explained using the time chart shown in FIG.

FIG. 3A shows the inverter output voltage waveform.

Therefore, the waveforms at terminals a and b become as shown in FIG. 3B.

FIG. 3C shows the output voltage of the comparator 20, which becomes high level when the inverter output voltage exceeds 88.

Further, the third diagram shows the output voltage waveform of the capacitor 24.

FIG. 3E shows the output voltage waveform of the comparator 25, which is at a high level when the output voltage of the capacitor 24 is higher than ED.

FIG. 3F shows the output voltage waveform of the AND circuit 26 and the comparator 2
When both 0 and 25 are high level, the level becomes high.

FIG. 3G shows the output voltage waveform of the monostable multi-bibreak 21.

At startup, the voltage between terminals a and b rises slowly due to the reactor 3, so the comparator 25 has already reached a high level, and then the voltage between a and b reaches EB, and the comparator 20 goes to a high level. Become.

At this time, the output of the AND circuit 26 becomes high level and drives the monostable multivibrator 2T, and the output inverts the flip-flop 28 to perform commutation.

Also, at this time, the voltage of the capacitor 24 is reset.

During normal operation, there is sufficient commutation capacity, so comparator 2
The output of the comparator 25 reaches a high level after a certain period of time tD determined by the output voltage of the constant voltage source 21, the resistor 22, the capacitor 24, and the comparison voltage ED of the comparator 25. At that time, the AND circuit becomes high level, and its output drives the monostable multivibrator 2T, and this output also inverts the flip-flop 28 to perform commutation.

Furthermore, the output voltage of the capacitor 24 is reset by the output of the monostable multivibrator 27.

Therefore, during normal operation, commutation is performed at the period t1), and the inverter operates as a constant frequency inverter.

Even when the output voltage of the DC power supply 1 is low, the above output voltage becomes high, and the inverter output voltage becomes high, so that terminals a and b
It is clear that commutation does not occur until the voltage between is EB.

As described above, this invention omits the initial charging circuit consisting of a cyrisk, a capacitor, a resistor, and a DC power supply, making the configuration simple, and also allows stable commutation even at low output voltages. It is possible to provide a stable inverter device that does not fail.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional constant current inverter, FIG. 2 is a circuit diagram of a constant current inverter device having a commutation failure prevention circuit according to the present invention, and FIG. 3 is an operation time chart of FIG. 2. Note that the same reference numerals in the figures indicate the same or corresponding parts. 1...DC power supply, 4, 5, 6, 7...
Cyrisk, 10, 22...Resistance, 3...
...Reactor, 9゜24...Capacitor, 2
6...AND circuit, 20°25...Comparator, 27...Monostable multivibrator, 2
8...Flip-flop, 23...Transistor, 21... Constant voltage power supply, a, b...
...Terminal.

Claims (1)

[Claims] 1 Control switching elements connected in a bridge configuration to constitute an inverter, a DC power source that supplies constant current DC power to two points on one diagonal of the bridge of the control switching element, and a control switching element on the other diagonal of the bridge of the control switching element. a capacitive load connected between two points, a first comparator circuit that generates a signal when the voltage at the input end of the inverter exceeds a predetermined value, a charging/discharging circuit that charges and discharges the voltage from the constant voltage source, and A second comparator circuit that generates a signal when the charging voltage of the discharging circuit exceeds a predetermined value, and a second comparator circuit that operates when both the first and second comparator circuits generate a signal and generates a signal that starts discharging of the charging/discharging circuit. An inverter device comprising: a trigger circuit that generates a signal for reversing the firing of the inverter;