JPS58186799A - Delay circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an acoustic signal delay circuit used in an echo device for an acoustic microphone or a residual adder installed in an audio circuit to increase the sense of presence.

The conventional circuit of this type was constructed as shown in FIG. In Figure 1, the sound bud signal input from the input terminal (1) is amplified to the desired level by the amplifier circuit (2), and
, I), (packet brigade device) enters (3). B, B, D, (3) output the delayed input signal by a delay time determined in inverse proportion to the frequency of the two-phase clock pulse generated from the clock oscillator (4). Since the signal and clock pulse appear in the output signal, the clock pulse is removed by the low-pass filter circuit (5) and the delayed signal is sent to the output terminal (6).
get to. Because of this configuration, there is a drawback that if the filter frequency of the low-pass filter circuit (5) is set to a low frequency, the frequency characteristics will be impaired, and conversely, the frequency characteristics may be improved by setting the filter frequency to a high frequency. In this case, the clock pulse becomes a noise component and the 87N ratio decreases.

This invention was made in order to eliminate these drawbacks, and it is a sound II that obtains a frequency characteristic and an 8/N ratio that can withstand practical use.
(This provides the No. 8 delay circuit.

Hereinafter, an embodiment of the present invention will be described, which is not shown in FIG.

In FIG. 2, the Otoso signal input from the input terminal (1) is amplified to the required level by the amplification 1gl path (2). Here, the high frequency component of the Otoso signal passes through the bypass capacitor (7) and reaches the output terminal (6).

In addition, the middle and low frequency components enter B, B, D, (a), are delayed by a delay time determined in inverse proportion to the frequency of the two-phase clock pulse generated from the clock oscillator (4), and are output. Ru. The clock pulse mixed in this output signal is removed by the low-pass filter circuit (5) and combined with the still frequency component at the output terminal (6). Since it is configured like this, B , B y
l) The clock pulses generated in (3) are removed by the low-pass filter circuit (5) so that the 87N ratio is sufficient, and the high-frequency components that are lowered by the low-pass filter circuit (5) are compensated for by the bypass capacitor (7). can do. Although the high frequency components are not delayed, the delay in the middle and low frequencies is primarily responsible for the reverberation effect 1, so it is possible to obtain a sufficient sense of presence even in the actual auditory sense.

As described above, the present invention has the advantage that sufficient frequency characteristics and SIN ratio can be obtained in a speech signal delay circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional delay circuit, and FIG. 2 is a block diagram of a delay circuit according to an embodiment of the present invention. In the figure, (]) is the input terminal, (2) is the amplifier circuit, (3) is B]
, I), (Packet Bricate Device) (4) is a clock oscillator, (5) is a filter circuit, (6) is an output terminal, and (7) is a bypass capacitor. Note that in the figures, the same reference numerals are used for corresponding parts. Agent Shin Kuzuno −

Claims (1)

[Claims] Sound 41: an input terminal for receiving signals, a clock generator for generating clock pulses, inputting the above-mentioned sound signal and clock pulse, and delaying the above-mentioned sound signals by a delay time determined by the frequency of the clock pulse; D, (
packet brigade device), this B, B, I)
, a low-pass filter circuit which inputs the output signal of , and outputs a delayed signal to the output terminal, and outputs the cylinder frequency component of the above-mentioned sound signal to the above-mentioned output terminal by bypassing the above-mentioned B, B, D and the low-pass filter circuit. Delay circuit with bypass capacitor.