JPS5818655B2 - A connecting device that connects multiple microprogrammed computers to a single central memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention is disclosed in Japanese Patent Application No. 48-132985;
The present invention relates to a device for connecting a plurality of computers controlled by microprograms to a single central memory, as disclosed in Japanese Patent Publication No. 0-7443 and Japanese Patent Publication No. 56-32654.

These computers each include a data processing device, means for exchanging data with peripheral devices via at least one data transfer channel, and a microprogram device consisting of a memory with a set of microprograms.

The microprogram includes a first microprogram that controls execution of instructions stored in the central memory;
A hierarchy is established between lists of tasks each containing tasks of the same type that can be executed only by said means for exchanging data or only by said data processing device to process tasks with a priority task list at the top. a second microprogram forming a usable processing device;
and a third microprogram used for setting a list of tasks to be executed and arranging executable tasks of the same type in the corresponding list of tasks.

Further, each computer is connected to the second and third microprograms, and stores signals of the third microprogram indicating the current status of the list of tasks and transmits the contents to the second microprogram. a first storage means for outputting the first . a third microprogram connected to the second and third microprograms to store a third microprogram signal indicating that the actual task has priority over the current working task; a second storage means for outputting the contents thereof; and a second storage means connected to the first and second microprograms for storing a signal of the second microprogram for displaying the type of task to be executed. and a third storage means for outputting the contents of one microprogram.

A connection device according to the present invention includes a plurality of switch means each connected to a corresponding data processing device and having an output number equal to the number of the data processing device, and setting a connection path via the switch means to connect the data processing device to the data processing device. the second microprogram representing one of the data processing devices;
a decoding means for outputting a signal to a storage means of the device; a first means connected to the data processing device and storing a communication request output from the corresponding data processing device; and validity of the communication request. The present invention is characterized in that it comprises a plurality of verification devices, each including a second means for storing , a set of logic gates energized by at least the first means, and a synchronization means for synchronizing each verification means.

This synchronization means generates a signal for booting a plurality of sets of said logic gates connected to said computer having a communication request subsequent to said communication request that has become valid.

In the connection device according to the invention, the management of the tasks consists of a plurality of sets of microprograms stored in a specialized memory of the computer and a status register assembly, each comprising three memory elements, also provided in the computer. It is executed by a combination of

Due to the special structure of this computer, no external elements are required to dispatch tasks according to priority to the available computers.

This connection device is not used for sending tasks, but is used to mutually exclude task management on a computer-by-computer basis, suitable for synchronizing said computers.

Therefore, the structure of the connection device of the invention is simpler than that of known devices combining multi-processor systems.

Other features and advantages of the device according to the invention will become apparent from the following description of a non-restrictive embodiment, which is illustrated by the accompanying drawings.

In order to clarify the explanation of connected devices, each processing device transfers a calculation program and data output from a peripheral device to the processing device, and also transmits the results to the same peripheral device. It must be made clear that it is operated by a program.

In order to avoid conflicts that may occur when attempting to execute calculation programs and channel programs at the same level, and to take into account priorities, each processing unit
“Virtual.

Each processor, operating using a special microprogram set of processors, or "words" of memory, and states of binary digits to manage different operations, assumes one of the following states:

Available: No program to run.

Ready The state of waiting for processing equipment to become available to run the nib program.

Operating: The state in which the processing device is in use.

Waiting: Waiting for data transfer to finish, and the operation is put on hold even if there are tasks in the waiting list.

A computing processor may be in one of the states described above, except for the 11-wait state, but cannot be stopped for this purpose.

The processor state is determined by a list associated with the processor, which lists the interactions between a control block in central memory and a program scheduled to perform a certain operation, including at least one task executable on the processor. Depends on the task.

This control block, also called task description m, consists of a group of words in central memory that define a task and is used for saving when executing said task and during interoperability.

. Each task takes one of the following states.

Usable: A state in which the corresponding operation has finished or has not started yet.

Startable: A state in which the processor is on the waiting list, but cannot run until the currently executing task is finished.

Operating: The state in which the relevant processor is running.

Waiting: A state in which a processor is returned to the waiting list due to one or more external factors.

Therefore, the operation of virtual processors in a processing unit involves forming a hierarchy among the processors, making the processing unit available to processors with priority, creating a waiting list of tasks for each processor, and A device to manage it is required.

The virtual processor is achieved by a microprogram-controlled processing unit shown in FIG.

1 In FIG. 1, a plurality of computers (hereinafter referred to as arithmetic processing units or processing units) are controlled by a microprogram.

) each comprises a read-only memory (ROM) 1 for storing microprograms, an arithmetic logic unit with at least one computing operator 2, an instruction register 3, a local memory 4 with registers, It includes an assembly 5 having a plurality of status registers, and a control unit 9 for controlling data transmission between the arithmetic processing unit and peripheral devices (not shown) via a peripheral device bus 10. .

Transmission between each processing unit and the central memory 6 takes place via a memory bus 8 and a control unit 7.

Exchange between elements within the processing unit takes place via at least one data bus 11.

The connections between each processing device are as shown in FIGS.
Dispatched through 30.31.

Status register assembly 5 and instruction register 3 and ROM
1 is connected via test bus 12.

Data regarding the state of the processing unit provides instructions to the ROM which sequentially generates microinstructions.

The microprogram memory conventionally consists of a diode matrix and is coupled to a read microinstruction register ROMR and an address register ROMAD.

Computing operator 2 is, for example, US
P 3,861,585, the local
Memory 4 is coupled to an address register LMAD.

The ROM 1, local memory 4, instruction register 3, status register 5, etc. are generally commercially available and have well-known configurations, so they will not be described in detail here.

The control unit 9 is also conventionally well known. FIG. 2 shows that memory 1 is divided into three parts or modules.

The first module consists of a main microprogram module (hereinafter referred to as main module) 13, called the "basic execution unit", and four modules specifically specialized to execute instructions associated with each processor of this processing unit. It consists of secondary microprogram modules (hereinafter referred to as secondary modules) 13L, 132, 133, and 134, and is for executing standard instructions.

This first module is coupled to the processing unit 15 and interprets and makes executable the instructions read from the central memory 6.

The processing unit 15 consists of an operator 2, an instruction register 3 and a local memory 4.

Main module 13 and four secondary modules 131-1
34 is connected to the central memory 6.

The four secondary modules 131 to 134 are the main module 1
3 and send a signal to the main module 13 when the instructions given to them are executed by the corresponding processor.

The four secondary modules 131 to 134 are, for example, a "channel" processor CR that transmits data at high speed, a processor TR that performs calculations in real time, and a "multiplex" processor C that processes multiplexed information.
It corresponds to four virtual processors consisting of MX and calculation processor CAL.

The remaining two modules of memory 1 are management block 14
and 16.

The management block 14 comprises a microprogram controlled automatic system for establishing a hierarchy between the processors or their respective associated work lists and enabling the processor 15 to take priority (dispatcher) to the processor.

Management block 16 includes an automatic microprogram control system that establishes a waiting list of executable tasks associated with each processor and manages the scheduler.

Management block 14 includes central memory 6 and main module 13
It is connected to the.

Furthermore, the management block 16 is activated by the main module 13 when the main module 13 contains in its microprogram a "system" instruction 4>IS, ie an operating instruction for one or more tasks to be performed.

The management block 16 is specifically configured to set up a hierarchical task system in order to maximize the utilization of the processing unit, and is capable of temporarily postponing the execution of a task or removing it from the waiting list. or later re-register on the waiting list.

Some of the tasks included in the waiting list may also be for other requests.

These are called "resource requests."

Taking into account the succession of such requests, the management block 16 has means for storing the requests in the "descriptor" of the task in question.

The management block 16 also has means for detecting instructions indicating the end of operations on a task and for removing or re-enlisting the task depending on whether all consecutive resource requests have been satisfied.

If tasks from different but identical processors are requested, the management block 16 has means for registering the descriptor of said task in a waiting list.

State Regista Assembly 5 supports four virtual processor CR, TR, CMX, CA, L, respectively, and four dual flip flop (BCR) 191, (BCR) 191, driven by management block 16. BTn,)1
92, (BCMX) 193 and (BCAL) 194.

Management block 14 includes means for checking the status of these four flip-flops.

Status register assembly 5 further includes management block 14
and 16 and interrogated by the main module 13, and two connected bistable flip-flops PAo 181 and P
A, 182;

Four processors are represented by a four-digit binary number.

Flip-flops 181 and 182 are management block 14
and is examined by blocks of the main module 13 to execute normal instructions.

This main module 13 includes means for checking the flip-flop EXD.

Registers 18, 19 and flip-flops 17 of the status register assembly 5 are provided for synchronizing the blocks of memory 1 with microprograms.

The numerical value indicated in register 18 specifies the type of processor in operation.

Flip-flop EXD is set by management block 16 when management block 16 changes the priority processor to the ready state.

Execution brain main module 13 detects changes in the configuration of the ready processor by examining flip-flop EXD17.

In this case, the management block 14 sets the hierarchy between processors.

4 flip-flops (BCR) 191, (BTR
) 192, (BCMX) 193, and (BCAL) 19
4 is set or reset by the management block 16 according to whether each corresponding processor is enabled or not.

The synchronization mechanism is very simple.

The management block 16 handles the resource requests to be executed by an external ``resource request JDR'' or ``system'' command + IS.
It is operated by the above-mentioned related commands, and here the latter is used.

The latter becomes ready when an instruction for one of the tasks associated with the enabled processor is input.

In this case, the management block 16 records this change in the register 19.
is stored in the corresponding flip-flop.

In addition, if the new ready processor has priority over the active processor, management block 16 sets flip-flop (EXD) 17 and transfers control to main module 13. .

The main module 13 is a flip-flop (EXD) 17
, interrupts the task in progress, transfers control to the management block 14 and transfers the local memory to the central memory 6 associated with the control block of the interrupted task.

Flip-flop (BCR) 191 of register 19;
(BTR) 192, (BCMX) 193 and (BCA,
L') 194 to determine the first task on the waiting list of tasks belonging to the new ready processor and operates register 18 to store the number of the processor being given to the processor system.

It then controls the transfer of a certain number of words from the control block (contents) of the new task to the registers of the local memory 4.

In particular, one of the words is set to its normal counter.

Such an operation is commonly referred to as "initialization setting."

The management hook 14 again passes control to the main module 13.

Usually, the main module 13 is passed to a processor with priority through an operation called "initialization setting."

The main module 13 controls normal counter reading and corresponding instruction reading, and transfers the read instructions to the instruction register 3.

Register 18 is then examined to determine whether the sign of the instruction contained in instruction register 3 is a computation-related instruction or a "channel" instruction related to data transfer.

When all operations corresponding to this new task having priority have been completed, the main module 13 transfers control to the management block 14.

The management network 14 again controls the transfer of the contents of the block and the tasks included in the registers of the local memory 4.

This allows the restarted task to start running again.

Each virtual processor has a corresponding flip-flop in register 19, a word of memory containing the address of the descriptor of the first task executable on this processor, a main module 13, and a word specific for this processor. is specified by an assembly of secondary modules 131-134.

In the actual case shown in FIG. 3, four processing units 20, 2L22 and 23, which are the same as the arithmetic processing unit described above, are connected to the central memory 16 via a common cable 24.

Each processing unit 20, 21, 22 and 23 is further connected to a group of peripheral devices, not shown, via a bus cable 251, 252, 253 and 254.

According to such system configuration, all chi? The Yarnell program can be applied not only to a set of virtual processors, but also to a single computing device.

A waiting list of specific channel programs is then established for each channel processor of each processing unit.

On the contrary, every calculation program 1 program is executed in the same way by each of the four processing units.

Note that a waiting list of only calculation programs may be set and this may be applied to four processing devices.

Each task is associated with a task descriptor, a set of words that defines the task, so that it can be executed,
It can be remembered if it is included.

The first word of each task's descriptor contains a first group of two-digit binary numbers specifying the processing unit on which the program is to be executed, and a two-digit binary number specifying the virtual processor on which the task is to be executed. and a second group of binary numbers of digits.

In the case of a calculation program, the state of the first group of digits is meaningless since this program can be executed on any processing device.

Central memory 6 contains the address of the first task selected for each processor.

Each processing unit has three channel processors and one calculation processor.

In total, the four processing unit groups have 16 virtual processors.

Therefore, the same number of words are stored in the central memory 6 with fixed addresses.

Each task contains the address of the first ready task ADT and a one-digit binary number S that determines whether the corresponding processor is ready.

The combination of address and binary number S represents the state of the processor.

That is, ADT=0, the processor is in the ready state ADT10 and S=1, the processor is in the ready state ADTlo and S-0, the processor is in the standby state The state of the processor in operation is determined by the register 18 (second
(see figure) by flip-flops PAo and PAl.

The 13 words corresponding to each of the 13 processors are:
In each processing unit, it is constantly controlled by a different management block 16, examined by management block 14, and used to manage a waiting list of processors.

The exchange of information between the processing units is preferably for the control of a synchronization system consisting of an interconnection system synchronized between each element of the microprogrammed memory, as well as a system for determining priorities between the processing units; This is done by managing 13 words of central memory 6.

The connection device connecting each processing unit includes an assembly 26 (FIG. 4) connected to the management block 16 of the waiting list of ready tasks.

Assembly 26 includes a decoder 27 of the known 2-bit/4-bit type connected to internal bus cable 11 (see FIG. 1).

The four output channels of this decoder 27 are respectively connected to the first input terminals of four AND gates 281, 282, 283 and 284, the second input terminals of which are connected to the output terminals of the management block 16. It is connected.

4 AND gates 281, 282, 283° and 2
84 output terminals, four bus cables 291.29
2, 293 and 294 to the respective processing devices.

As shown in FIG. 5, each of the management blocks 161, 162, 163 and 164 of the four processing units manages a waiting list of ready tasks for the assembly 2.
6 via four external bus cables 291, 292,
293 and 294.

Flip-flops 171, 172, 173 and 17
4 (FIG. 5) is used to store the state of ready processors that have been given priority, and is connected to four bus couples 291, 292, 293 and 294, respectively. 1 input terminal and four blocks 141, 1 for managing the processor of the corresponding processing device.
and second input terminals connected to 42° 143 and 144, respectively.

Such an arrangement interconnects processing devices.

One of the management books 161, 162, 163, and 164 determines a waiting list of tasks corresponding to a processor having priority, and when it is enabled, selects a task having priority from the waiting list. first descriptor
Read the word and transfer this word to internal bus cable 1.
Controls the sending of 1 to 1.

A decoder, for example decoder 27, is an AND gate 281
．． By opening one of 282, 283 and 284, external bus cable 2 is removed from blocks 161-164.
91 to 294, and ultimately to the flip-flops 171, 172 and 173 associated with said cable.
and 174 to control the transmission order to one input terminal.

The two-digit binary value sent from internal bus cable 11 to decoder 27 is the first digit of the task descriptor that determines the appropriate processing unit number. Extracted from part of a word.

With such interconnection, which flip-flop 1
Before the processor knows whether 71-174 receives a drive signal, each management block
174 can be set.

Since the destination is contained only in the task descriptor, management blocks 161-164 can access all tasks stored in memory and are completely identical.

Each processing unit differs only in its connection to the external bus cable.

Such an interconnection allows the processing device to take into account that one of the processors has changed from an enabled state to an operational state.

Communication between the processing units is carried out through one of 13 words of memory, each associated with 13 processors, but these processing units cannot modify or test these words at the same time.

For this reason, the present invention provides the control unit 7 (FIG. 1) of each processing device.
A priority unit UC,,U determines the priority order among the processing units.
It is equipped with C2...

As shown in FIG. 6, the priority devices UC1, UC2, . (FIG. 6), a second flip-flop ESY, a bus cable 30 and conductors 31 common to all priority processing units, and logic gates interconnecting these elements. , with priority rights associated with each processing unit.

The output terminal of AND gate 32 is connected to one of the input terminals of flip-flop ESY.

The three input terminals of the AND gate 32 are connected to the output terminal indicated by Q of the flip-flop DSY, an inverter 35 connected in series with the conductor 31 via an OR gate 33, and an AND gate 34. and is connected to the output terminal indicated by Q of the flip-flop ESY.

The Q terminal of the flip-flop ESY is OR gate 3.
3 input terminals and AND gate (line driver) 3
6 and is connected via line 37 to test bus cable 12 (not shown) (see FIG. 1).

Bus cable 30 is connected to the output terminal of AND gate 36 and to the input terminal of AND gate 34.

The output terminal Q of the flip-flop DSY is an AND gate 38 inserted between two priority devices respectively corresponding to two consecutive processing devices, for example, between UCl and UC2, and between UC2 and UC3. control.

At the beginning of each microprogram associated with the management blanks 14 and 16 of each processing unit, microinstructions related to microprogrammed management requests are set, consisting of 13 memory words corresponding to 13 processors.

If there is no such management request from the microprogram, AND gate 38 controls each flip-flop DSY.
It is opened under the control of the signal output from the output terminal Q of , and outputs one activation signal to the conductor 31.

For example, when the corresponding flip-flop DSY is set by a signal issued from the micro-instruction 4>S in response to a management request from the processing unit of the priority device UC2, the corresponding AND gate 38 is blocked, so that the activation signal is not activated. is the priority device U with the next priority via the AND gate 38.
It is not transmitted below c3.

Setting the flip-flop DSY opens the corresponding AND gate 32 and clocks (not shown)
When the flip-flop ESY is set by the clock signal output from the flip-flop ESY, the flip-flop ESY is configured such that the management request issued from the processing unit gains priority, and other management requests are not accepted. Indicates that there is no

The state of flip-flop ESY is sent over line 37, thereby also informing the higher priority unit UC1 that the processing unit has obtained a priority request.

The setting of the flip-flop ESY energizes the bus cable 30 and connects the AND gate 32 and the inverter 35 of the priority unit UC1 upstream of the priority unit UC2 blocked by the request having priority. Close via.

When the management purpose of the request has been fully fulfilled, the flip
The flop DSY is reset to zero by a signal R issued by a microinstruction belonging to the management block.

When flip-flop DSY is reset to zero,
Other priority devices Uc1. It becomes possible to accept and accept Uc3 management requests.

Such an arrangement has the effect of establishing a hierarchy between the processing units and preventing them from interrupting simultaneously to manage the 13 memory words.

The present connecting device may be modified without departing from the scope of the invention.

For example, instead of using a central memory register 19 (see Figure 2) to indicate the state of a ready processor, a three-digit binary number for a channel processor and a ready compute processor state may be used. , one digit common to all processing devices may be set.

This modification is used when the binary testing of these digits is not frequently included and therefore there is no need to introduce ancillary equipment to store the state of the processor.

[Brief explanation of the drawing]

1 is a block diagram of a processing unit; FIG. 2 is a block diagram of a microprogram-controlled processing unit with four virtual processors; and FIG. 3 is a block diagram of a microprogram-controlled processing unit with a single central memory and multiple processing units. Connection diagram, FIG. 4 is a block diagram of a connection device connected to each processing device to enable information exchange between the processing device and memory, FIG. 5 is a schematic block diagram of the connection device, and FIG. 6 1 is a block diagram of a priority device that controls connection requests between a processing device and a memory; FIG. 6... central memory, 20... processing unit, 27... decoder, 33... or...
Gate.

Claims (1)

Claims: 1 each comprising a data processing device 15, means for exchanging data with a peripheral device via at least one data transfer channel, and a microprogram device consisting of a memory 1 with a set of microprograms; a first microprogram 13 controlling the execution of instructions stored in a central memory 6; and a first microprogram 13 controlling the execution of instructions stored in a central memory 6; a second microprogram that establishes a hierarchy between lists of tasks each containing tasks of the same type that can only be executed by the device to form a processing device that can be used to process tasks with the priority task list at the top; 14, and a third microprogram 16 used for setting a list of tasks to be executed and arranging executable tasks of the same type in the corresponding list of tasks, and further controlling each of the microprograms. the computer comprising status register assembly means, said assembly means being connected to said second and third microprograms and storing signals of said third microprogram indicating the current status of said list of tasks; a first storage means 19 for outputting the contents to the second microprogram; a second storage means 17 for storing a signal of the third microprogram indicating that the third microprogram has priority and outputting the contents to the third microprogram; the second display unit connected to the microprogram and displaying the type of task to be executed;
a plurality of microprogram controlled computers connected to a single central memory, the third storage means for storing signals of the program and outputting the contents to the first microprogram; The connecting device further includes a plurality of switch means each connected to a corresponding data processing device 15 and having a number equal to the number of the data processing devices, and a connection path via the switch means set. in response to a signal from the third microprogram 16 of any one of the data processing devices 15;
a decoding means 27 for outputting a signal to the second storage means 17 representing one of the data processing devices 15; and a communication request output from the corresponding data processing device connected to the data processing device. first means (DSY) for storing the validity of said communication request; second means (ESY) for storing the validity of said communication request; a set of logic gates 32, 34 at least energized by said first means (DSY); ，
35, 36, and a synchronizing means for generating a signal for blocking a plurality of sets of logic gates connected to the computer having the request for communication following the request that has become valid; and a plurality of confirmation means synchronized by the means.