JPS5818654B2 - Arithmetic device based on key operations according to mathematical formulas - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device that allows key operations to be performed directly in accordance with the order of mathematical expressions that include parentheses, and more particularly to an arithmetic device that displays the results of calculations within the parentheses when the right parenthesis key is pressed.

Key operation methods for calculations in electronic desktop calculators and the like having four arithmetic operation keys have been conventional, such as the methods shown in FIGS. 1A and 1B and 1 to 3.

Method 1 has (+/-) key entry and (-/-) key entry, and is not completely mathematically correct.

Methods 2 and 3 cannot be performed exactly according to the formula if the formula includes parentheses.

The present invention is constructed so that arithmetic processing can be performed by key operations that directly follow a mathematical formula, as shown in the columns of the method of the present invention in FIGS. It is something.

Here, a brief explanation of terms used in the present invention will be given.

Addition, subtraction, multiplication, division, and exponentiation are each expressed as +1 1 * S / 3↑, and the second,
Figure 3 is a block diagram showing the first embodiment of the computing device of the present invention, and 1 is a keyboard for inputting numerical data and instructions; calculations can be executed simply by pressing each key according to a mathematical formula. be.

This keyboard has a numerical data key - Koshi ~ El, a decimal point key, four arithmetic operation command keys El, -B, E], a parenthesis key [
薯・■・Equal sign key date・ゞ< multiplication + 1 (for example, when calculating 23, use 2゜G, 3), display register (for example, Acc), display register clear key E
] All register all clear key [ etc. are mainly provided.

Reference numeral 2 denotes an ordinary encoder for encoding key signals from the keyboard 1 and inputting the encoded signals to the arithmetic unit.

Especially the operator Kan, Me 1 Kuchi. - In the case of the [Z] key, it is coded and ranked as shown in Figure 5.

3 is a register TR that can be shifted in both left and right directions, and the operators are coded and stored in the order in which they are pressed.

The order of this code signal is, for example, as shown in FIG.
Score or 1st place, ×, ÷ or 2nd place, +, - or 3rd place, C, (
, = is ranked fourth, and so on.

Reference numeral 4 denotes a comparison/discrimination circuit which discriminates the contents stored in the LSD digit of the register TR as shown in FIG.

The details are disclosed in FIG.

The control unit 5 performs various controls based on data and commands from the keyboard 1.

6 is a circuit for controlling four arithmetic operations between registers 7, 8 and 9;

Numerical registers 10 to 14 are used to temporarily store operands and arithmetic numbers, and to execute various mathematical formulas by key operations according to the mathematical formulas.

A1 to A9 are for data movement, A10 to AI9 are for controlling the LSD content determination, 01 to 05 are for or gates, ■1 to ■7 are for impark, Ml and M2 are for example, function calculation, constant multiplication, etc. is a normal memory register for.

All formulas A and +BXC- are operated by key operations directly according to the formula (as illustrated in the method column of the present invention for formulas A and BXC2 in Figure 1A).
The circuit diagrams in Figures 2 and 3, the flowchart in Figure 4, the code and ranking table in Figure 5, and the transition table of the final contents of each register after each key is pressed in Figure 6 explain.

It is now assumed that all registers are cleared by pressing the clear key as shown in FIG.

This state is shown in step A line of FIG. 6B.

Next, when the key is pressed, the control unit 5 executes the process shown in FIG.
Let's do it.

In other words, the specific processing method differs depending on the content of the code signal stored in the least significant digit (LSD) of the register TR; if the content of the LSD is not the code signal 0, proceed to process 1, and if the code signal is O, proceed to process 2. It is determined by circuit 4 and each step proceeds.

In this case, immediately after all registers have been cleared, the contents of the LSD are the code signal O of the clear key El defined in Figure 5.
Therefore, proceed to process 2.

That is, in FIG. 3, the contents of the LSD in the register TR are determined by the discriminating circuit 4 made up of a diode matrix circuit, an output is generated from the contents O of the LSD to the discriminating output line O, and an execution command for process 2 is issued by opening the AND gate A15. or is sent to the control section 5.

In process 2, as shown in FIG. 4J, the contents of register ACC are moved to register SR1 by opening AND gate A1, and S
Open ant game-1-A3 and save the contents of R1 to register S.
Move to R2, Antoge-1-A5°A7. A9.・
...Open register SR2 → SR3 → SR4
→Move the data contents of SR5 and each register.

This data movement command is generated from the output terminal PD of the control section 5.

The process of moving data between registers in units of one word is hereinafter referred to as PUSHDOWN.

After the bushdown of process 2 is completed, set register TR to 1.
Shift the digits to the left, and when that is finished, return to Figure 4 and proceed to the next process of process 2, that is, register TR.
The Lokey code signal 1 defined in FIG.

Therefore, the contents stored in each register in this state are shown in Figure 6A.
As shown in the STELLA PRO] line, the code signal 1 is stored in the LSD of the data A register TR in the register AC, and the data A is stored in the register SR1.

Next, when data B is inputted from the group of numeric keys on the keyboard 1, the content A stored in the register Acc is rewritten to B, as shown in step 718 line of FIG. 6B.

At this stage, the next command key to be input is +s s
Since it is not known whether s÷ or I, the operation is not executed yet, so the addition operation of A+B is not performed.

Next, when the 4-heat key is pressed, the control unit 5 executes the process shown in FIG.
Let's do it.

That is, if the content of the LSD in register TR is thicker than code signal 2, the process proceeds to process 1, and if it is smaller than 2, the process proceeds to process 2. Since the code signal 1 of the pressed key is stored, and this corresponds to a case smaller than 2, the process proceeds to AND gate A18 or opening process 2 in FIG.

Processing 2 is shown in FIG. 4j, and after finishing the bushing down of numerical data B and A and shifting the register TR by one digit to the left under the control of the control unit 5, the process returns to FIG. ■ As defined in Figure 5 for TR's LSD
Stores the key code signal 3 and stops.

At this stage, as shown in step X line of FIG.
Data B1 is stored in register S'R2.

In the case of setting the data C, the previous stored content B of the register Acc is simply rewritten to C, and no data movement occurs, and no calculations of any kind are performed at this stage.

Next, when the result calculation command key ■ is pressed, the control section 5 performs the processing shown in the fourth diagram.

In other words, first, as in the case of pressing the ■ key, the register TR is
It is determined whether or not the code signal stored in the LSD of is O.

In this case, as shown in FIG. 6, step B, line C, the register TR
Since the code signal 3 of the key is stored in the LSD of
opens and proceeds to process 1.

In process 1, the process shown in FIG. 4R is performed by the control section 5, the arithmetic execution circuit 6, and the register group.

Now, the LSD of Jisk TR is 3, so TRLSD=3
Proceeds to Yes in the determination part of , and compares the storage locations of register SRI and register Acc (in this case B, C'
) is executed in the operation execution circuit 6 under the control of the control unit 5, and the product (BXC) that is the calculation result is stored in the register Ac.
Store in c.

The execution of such multiplication operations or other operations such as addition, subtraction, and division can be carried out using well-known general techniques, such as the FIG.
PROCESSORIO and A described in IA
This can be easily done using RITI (METICUNIT 22, etc.).

Next, a data movement command is generated from the output terminals P and U of the control section 5, and the Antogame-1-A8°A6. A4. Open A2 and transfer the contents of register SR5 to SR4 and the contents of SR4 to SR.
3, the contents of SR3 are moved to SR2, and the contents of register SR2 are moved to register SR1.

This process is hereinafter referred to as POP UP.

Next, the register TR is shifted to the right by one digit to erase the multiplication code signal 3 for which the operation has been completed.

At this stage, as shown in the second line of step C in FIG. 6A, the product BXC is stored in the register Acc, the addition conid signal 1 is stored in the LSD of the register TR, and the content A of SR2 is pop-amplified and stored in the register SR1. The contents O of register SR4 are stored in register SR3 and cleared.

Even if data is moved in the following registers by the hop-up process, the contents are all O, so there is no change in whitening.

Next, when processing 1 is completed, return to the TRL of the 4th pattern
SD-〇? Return to the discrimination part again.

In this case, since the addition code signal 1 is stored in the LSD of the register TR, the process returns to process 1.

In process 1, since TRLSD=1 this time, register S
Contents of RI+4 A ll, ,=contents of register Acc "'BXC" are added in arithmetic execution circuit 6 under the control of control unit 5, and the answer "A+BXC" is stored in register Acc.

Pop-up processing is performed again, and when register TR is shifted to the right by one digit, the answer A+BXC is stored in register Acc, as shown in the Stellar Pro line of FIG. 6A, and the contents of all other registers become O.

At this point, the process returns to FIG. 4 and the LSD of the register TR is determined once again.

The previously stored addition code signal 1 in LSD of register TR has been shifted to the right by one digit and erased, and the current stored content is O, so TIRLSD:O? The determination goes to Yes, and all arithmetic processing is finished with HALT.
The answer "A+BXC" in the register A, cc can be displayed or read by the printing device O.

In this embodiment, as described above, the operator +j j * j Z
↑ Set the execution priority as shown in Figure 5, and shift the register TR to the left or right as appropriate in the order in which these keys are pressed.Also, set the data storage register group to correspond to it and perform pushdown and popup processing as appropriate. With this simple structure, the answer can be obtained by key operations that directly follow the mathematical formula.

In order to further explain the features of the present invention, an example using the bracket keys @ and @ (for example, AX(B+C)2) will be described below.

In other words, the operation when calculating the result of the formula A × (B + C) 2 by key operations according to the formula using the bracket keys ■ and ■ is shown in Figures 2.3, 4゜5 and Figure 6B. Refer to and explain.

Pressing the clear key to input data A into register Acc is performed in the same manner as in the previous example.

Next, when the x key is pressed, the process shown in FIG. 4d is performed.

That is, if the content of the LSD of the register TR is less than 2, the process proceeds to process 2, and if it is greater than 2, the process proceeds to process 1.

In this case, immediately after being cleared, the content of the LSD is O, so an instruction to open the anime game 1418 in FIG. 3 and proceed to the process 2 routine is entered into the control section 5.

Processing 2 is shown in FIG. 4J as described above, and the contents of register Acc are moved to register SR1 by opening AND gate A1, the contents of SR1 are moved to register SR2 by opening AND gate A3, and then the contents of register Acc are moved to register SR2 by opening AND gate A5. , A7 , A
9... Open SR2 → SR3...S
Move registers down by one word from R4 to SR5, shift register TR by one digit to the left, and then shift register TR by one digit to the left.
The next process after process 2 in FIG. d is that the multiplication code signal 3 is stored in the LSD of register TR and then stopped.

[After pressing the hot key, step X in Figure 6B]
As shown in the line, the contents A of register Acc or register SR
1, and at the same time, a code signal 3 representing a multiplication operation is stored in the LSD of the register TR.

At this time, no data has yet entered the other registers SR2, and 0 is simply moved thereto.

Next, when the ■ key is pressed, 0 is stored (cleared) in the register Acc as shown in Figure 4 f, and the LSD of the register TR is
A one-digit right shift is performed over the range from to the most significant digit (MSD), and as a result, 0 is stored in the LSD digit.

Next, in the case of data B, data A is stored in the cleared register Acc.

When the + key is pressed, the processing routine shown in Figure 4 is entered, but the difference from the Lokey case is that if the LSD of register TR is 0, AND gate A14 in Figure 3 is opened, and processing 1 is entered; Open AND gate A15 and proceed to process 2.

As in the previous example, the LSD of register TR stores the coded instruction key pressed immediately before each instruction key, so the priority is determined by comparing it with this and the calculation is controlled according to this result. means that something is done.

In other words, to re-express the features of the present invention including the previous example, in the case of Roki-Lokey, the operation of multiplying or dividing data existing on both sides of each key is executed by the previously pressed command key or code 3, This is limited to the case of the 4th or 5th key, the El key, or the 4th key, but if an operation of addition or subtraction between data existing on both sides of the El key or the El key is executed, add ■.

"A key is added.

In other words, as can be seen from the comparison/discrimination circuit 4 in Fig. 3, the flowchart in Fig. 4, and the ranking table in Fig. 5, in the case of exponentiation calculations, all command keys except the LO key are used to execute the calculations. All command keys except the 11 key are used to perform calculations and the conditions are short, and it becomes addition and subtraction.
, IZI, El, and command keys other than the 9 keys are limited to starting calculation execution.

This means a function to determine the calculation priority, and while the key operation order of one operator remains in accordance with the mathematical formula, the computer itself automatically positions the calculation order and starts or commands successive calculations. This means that it is possible to control data from storage to standby.

In this case, at the time when the ] key was pressed, the command key pressed immediately before this key is "day," which is stored in the LSD of O or register TR as a result, and the Since A15 is opened, data B is pushed down to the SR resist group in order to perform process 2 in FIG. 4J.

As a result, data B is stored in register SRI and data A is stored in register SR2.

Next, a one-digit left shift is performed in the range from LSD to MSD of register TR, and code signal 1 of the ■ key shown in FIG. 5 is stored in LSD of register TR, and the processing routine of FIG. 4 is completed.

Next, in the number of data C, the previous stored content B of the register Acc is rewritten to C, and at this stage step 710 of FIG.
As shown in the rows, each data A, B, and C is stored in a register S.
R2, register SR1, and register Acc.

Next, the case where the ■ key is pressed will be explained according to the flowchart in FIG. is opened, and a command signal to proceed to the processing 1 routine shown in FIG. 4R is given to the control section 5.

Here, as mentioned above, we will explain the LSD of register TR in more detail.
The contents of the book will be explored.

Now, the LSD of register TR is 1'', so it goes immediately below, an addition instruction is generated, and the contents of register SR1 are 91B.
Contents of register Acc to u C9 or operation execution circuit 6
The addition (sum) is stored in register A c c.

Next, a data movement command is issued from the output terminals P and V of the control unit 5, and the data movement command is output from the output terminals P and V of the control unit 5, and the data movement command is output from the output terminals P and V of the control unit 5. A6゜A4. A2 is opened and the pop-up data is moved from register SR5 to 5R4-+SR3 to SR2 to SR1, and the register TR is shifted to the right by one digit in the range from LSD to MSD, and returns to the determination point.

At this point, register Ac c contains B 11++T C1
The sum of 1 is stored and visible on the output device O.

A'' is stored in register SR1, and LS of register TR
Since D is 0'', based on the result of this judgment, the register TR is shifted to the left again by one digit in the range from LSD to MSD and enters the standby state, resulting in the contents stored in the register shown in the step-line of Figure 6B. Complete tasks with keys.

When the next key is pressed, the LSD of the register TR is checked as shown in the fourth diagram, and now the register TR (
7) Since the LSD is °゛3'', the AND gate A10 in Fig. 3 opens and a command to proceed to processing 1 enters the control unit 5, and the process proceeds to Yes of TRLSD = 37 in processing 1 in Fig. 4 R, so multiplication is performed. An instruction is generated and the contents of register SR1 +!AJ
Contents of register Acc in l B 11+ 41 C1
1 is added, this result is brought to the register Acc, the SR register group is popped up, the register TR is shifted to the left by one digit in the range from LSD to MSD, and the process returns to the checkpoint.

At this point, registers SR1 to SR5 are all 0'', and all digits from LSD to MSD in register TR are penalized.
C") has been stored, and since the LSD of the register TR is 0" as a result of the final determination, it enters a standby state and all calculations have been completed.

6C, D, E, and F show other calculation examples in the implementation circuits shown in the second and third figures, which follow the processing shown in the fourth figure as described above.

Particularly, FIG. 6C explains the case where if the order is the same, such as + and -, the calculations are executed in the order in which they were input.

FIG. 7 is a block diagram showing a second embodiment of the present invention.
The contents of the first digit and the new operator instruction entering the LSD are compared and determined, and at the same time the new instruction is stored in the LSD digit of the register TR.As shown in FIG. 13A, the processing control is as shown in FIG. It is possible to do this more easily than in the example above.

Figure 8.9.10 is a detailed diagram of Figure 7, Figure 11 is a basic timing pulse waveform diagram to explain its operation, and Figure 1
Figure 2 is a timing chart explaining the operation when the mathematical formula AX (B+C) = calculation is performed using the circuit example in Figure 8.
FIG. 14 shows the transition of the contents of each register at each step.

The configuration and operation of the second embodiment circuit example of the present invention shown in FIG. 7 will be described below with reference to FIGS.
This will be explained with reference to the drawings in the figures.

FIG. 9 shows a concrete example of a circuit of a pulse generator that generates the various timing pulses shown in FIGS. 11A and 11B.

That is, the clock pulse CP from the oscillator O8C is sent to the flip-flop F1. Signals Fo1, Fo2 via F2
Take out the and gate A21, 22, 23゜2
a signal TBO with weights of 1-2-4-8 from 4, respectively;
Take out TBl, TB2, and TB3.

In this embodiment, one word is set to 10 digits, so the flip-flops Fil, 12, 14 . From '18, each set output signal Fo11. Fo12°Fe14. Fo
1B or signal Fo2 as shown in FIG. 11B, and the least significant digit signal TLS of 1 word and 10 digits.
D, the next digit signal 'I' LSD-1-1, the most significant digit signal TMSD, and the 1-word end signal TEW are respectively A2-A2B of FIG.

A29. A30. Taken out from A31.

FIG. 10 shows the key press signals KC and KO- divided by 9 and KX for each key switch on the keyboard.

It explains how to generate K+, ni-, K(, ni, I, K'', etc.).

The key start signals STA and RT in Figure 11C are as shown in Figure 8A.
It is generated by the OR gate OR1, one-shot multi-by-break OS, flip-flop FSI, l'i''82° AND gate A32, etc.

This is a well-known technique, and each key signal (for example, +) of an operation command is asynchronously inputted from the OR gate OR1.

K (, etc.) is synchronized with the synchronization signal Fo18 or the TEW signal in the computer to obtain the 5TAR,T signal as shown in FIG. 11C.

That is, for example, a key signal of × is inputted to the one-shot multi-by-break O through the OR gate OR1.
8 is activated for a predetermined time as shown in FIG. Flip-flop F on falling
Since S2 is set, the output signal of AND gate A32 is 5TAR which rises for one word time as shown in FIG. 11C.
The 5TART signal causes each circuit to start operating.

The register TR shown in FIG. 8A is 1 from MSD to LSD.
It is 0 digit, and the contents are normally shifted to the right and circulated through Antogame-1-A34.

MSI)' is a 1-digit detour register for shifting left by 1 digit, and the AND gate A36. By opening A42 and passing the contents of register TR through register MSII)', the whole is shifted to the left by one digit.

In addition, AND gate A33 shifts the contents of register TR by one digit to the right, and holds the contents of the one digit shifted from LSD+1 digit to LSD digit for one cycle period of register TR, that is, one word time. It is interposed in a circular loop with

Antogame-1-A35 is an operator calf-signal (e.g. KX,
+ etc.) to the MSD of the register TR at the time of the timing 'I' LSD.

AND gates A37 to A41 constitute an encoder 2 for generating the code signal shown in FIG.

The discrimination circuit 4 is composed of a diode matrix circuit as shown in the figure, and the timing 'l' LSD-1-1 and T
L S stored in LSD of register TR at time of BO
D+ The stored content of the first digit is determined, and whether it is the content or code signals O to 5 is recognized by the signals from each output line.

FJ, FCI to FC4°F+, F-, F shown in Figure 8B
X, F÷, and F↑ are made into flip-flops, and are reset and reset according to various conditions.

The flip-flop FC1 is as shown in FIGS. 13A and 13B.
Next to the key 5 TART signal of the operator that has just been input, set one word time, and during that one word time, register TR goes low.
The contents of SD+1 digit are determined.

Flip-flop FC2 is set for one word time when shifting register TR by one digit to the right or left, PVSHDOWN, etc.

Flip-flop FCO3 is L of register TR in processing 1.
Set one word time when determining the contents of SD+1st digit.

Flip-flop FC4 is set for one word time when pop-up processing of register TR, right shift by one digit, etc. are performed.

Flip-flop FJ is flip-flop FC2, FC
Determine which of 3 to set.

Flip-flops F1, F-, FX, F÷, and F↑ are set when performing addition, subtraction, multiplication, division, and exponentiation operations, respectively.

The detailed operation of an example calculation of AX(B+C)= will be explained below with reference to FIGS. 8 to 14.

As shown in Figure 14, first press the clear key (large) and the 8th
Data register SR1 that constitutes the data stack in Figure B
, SR2, etc.
1, AC2, etc. are closed and the circulation loop is broken, so the registers SRI, SR2, etc.
etc. will be cleared.

Further, a clear signal KC is inputted to the arithmetic execution circuit 6 via the OR gate OR12 to clear the contents of the register ACC.

Deck A is stored in register ACC using well-known techniques.

Next, when the play key is pressed, the one-shot multi-by-break O8 is activated as shown in FIG. 12A through the or game 1-0RI, and the flip-flop FS1. FS2 is set to obtain the 5TART signal from AND gate A32.

This 5TART signal is 1 word time AND gate A35
is applied to

Also, AND gate A38 is the basic timing pulse TBO
or TBI is applied to the key signal, the multiplication code signal determined by 1+2=3 in FIG.
5 is input.

Therefore, AND gate A35 uses digit timing TI, S
Open at time D and send multiplication code signal 3 to OR gate OR2
through the MSD of the register TR and finally the LSD
The data is stored in the digit and thereafter dynamically cyclically held via the AND gate A34 in synchronization with the clock pulse CP.

In this way, code signal 3 of the figure key is stored in MSD of register 'TR at the time of LSD+1 digit within the 5TART signal high level time of FIG. 12A, and one word of 5TA
Stored in LSD at the end of the RT signal.

During the time when the key start signal 5TART is at a high level, the or game 1-0R8 and 9 shown in FIG.
1 opens and flip-flop FC1 is set, generating set output FCO1.

This is Figure 12A. As shown in the figure, the flip-flop FC1 is set immediately after the completion of one word time of the <5 TART signal, and the reset input of the ant game 1-A45 is
Since it is opened and reset by the next i signal TEW, the setting time of the flip-flop FC1 also becomes one word time.

This time is a time for various discriminations as shown in a of FIG. 13A.

First, it is determined whether LSD+1 of register TR is O or not, but in this case, LSD+1, LSD+
2...The stored contents of all up to MSD are O.

In FIG. 8A, register TR is a dynamic shift register whose contents are circular, so 1, LSD+1
The content O of the digit arrives at the LSD, and a signal is generated on the 'l' LSD-)-1=0 output line of the diode matrix 4, which determines that the content is O.

This signal causes AND gate A48 in FIG. 8B to output signal F.
Opens due to the presence of CO1, setting flip-flop FJ.

Flip-flop FJ remains set until signal TEW is applied to the reset input terminal.

This set signal FJO causes the flip-flop FCO2 to
It is set because the AND gate A49 is opened at the timing of the signal TEW.

(The state of each signal during this period is shown in FIG. 12A.

) The set time of the flip-flop FC2 is also one word time, and the signal 2, K) does not exist during that time, so the AND gate A51 opens, and the output signal of this gate becomes the push-down signal of the register SR2. Good luck, and gate A1. A3°, etc. are opened and the bushing down process is performed as shown in FIG. 13A.

At the same time, the output signals P and D of this Antogame-1-A51
passes through the or gate OR4 in Figure 8A and enters the AND gate A.
36. A42 is opened and AND gate A34 is closed by inverter I23, and register TR is shifted to the right and circulated through register M811)'.

Since the bushdown signals P and D are the set output FCO2 of the flip-flop FC2, they are at the by level for a time of 1 word and 10 digits, and during this time, the register TR is set to the register M.
Since the data is circulated by 11 digits including SD', the contents of the register TR immediately after the end of this word are shifted to the left by one digit.

This situation is shown in the second line of the step RO line in Figure 14, immediately after FCO2, and as shown in the figure, data A is stored in register ACC, and register TR is shifted to the left by one digit and multiplication code signal 3 is stored in LSD+1 digit. The state will be as follows.

Next, when the day key is pressed, all digits of the register ACC and only the LSD of the register TR are cleared, as shown in C of FIG. 13A, and at the same time, the register TR is shifted to the left by one digit.

In other words, when the ■ key is pressed, the 5
The TART signal is generated and the Antogame 1447 to Figure 8 is generated.
is opened, and when the above-mentioned bushdown signals P and D are input through the OR gate OR4, the register TR is operated in a similar manner.
Shift left one place.

Therefore, at this stage, as shown in the step-row of FIG.
or stored states.

The LSD of register TR is this one-digit left-shifted antgame.
1-O is automatically stored by the output O of A35.

Also, the clear signal of register ACC is AND gate A47.
Simultaneously using the output signals of
All digits of register ACC are cleared by arithmetic execution circuit 6 via 12.

This can be done using the same method as the clearing operation of register SR2, etc.

During this time, as is clear from FIG. 8B and FIG. 13C, none of the flip-flops FC1, FC2, etc. are set.

Next, other circuits do not operate except for storing data B in register ACC.

Next, press the ■ key and use the previous 1] key to register T.
Since the contents of the LSD+1 digit of R have been set to 0, Figure 13A
As shown in the figure, the same operation as when pressing the "Previous" key is performed, that is, PVSHDOWN processing of register SR2 and shift of register TR by one digit to the left.

This specific operation is the same as pressing the LOCK key, so it will be omitted.

However, in the case of the key, the only difference is that the addition code signal 1 defined in Fig. 5 is stored in the LSD of register TR in correspondence with the multiplication code signal 3 stored in the LSD of register TR with do.

Next, the input of data C is to convert the previous contents B of register ACC into C
Rewrite it to .

Next, when the ``-'' key is pressed, the 5TART signal is generated as before, and the flip-flop FC1 shown in FIG. 8B is set.

In this case, as shown in step C line of Figure 14, the register T
Since the addition code signal 1 is stored in the LSD+1st digit of R, the flip-flop FJ is not set this time, and therefore the flip-flop FC2 is also not set.

Instead, timing TE is determined by the reset output of flip-flop FJ and the set output of flip-flop FC1.
When the signal is W, the AND gate A50 opens and sets the flip-flop FC3.

This set output signal FCO3 is also held for one word time,
The digit contents of TRLSD+1 shown in d of FIG. 13A are determined.

Further, the detailed control pulse waveform at this time is shown in FIG. 12C.

Now, the content stored in the LSD+1st digit of the register TR is the addition code signal 1 as shown in step C line of FIG. 14, so
A signal is generated on the output line of LSD+1 of the discrimination circuit 4 in FIG. 8A.

Therefore, the signal generated on the output line of LSD+1 is the 8th
Open the AND gate A52 in figure B and flip-flop F.
Set +.

This set output FO+ and the reset output after the flip-flop FC3 has been set for one word time open the AND gate A+, and ADDEH in the arithmetic execution circuit 6 causes the contents C of the register ACC to be changed to the contents B of the register SR1.
An addition operation is performed using a well-known technique, and the resultant sum B+C is stored in register ACC.

Know the sum by outputting it to output device 0.

When this execution is completed, the operation end signal End is generated from the operation execution circuit 6 at the timing shown in FIG. 12C, and the addition flip-flop F+ is reset and the flip-flop FC4 is set.

This End signal generation circuit can be easily created using various well-known techniques.

Flip-flop FC4 is also set for one word time, or this set output signal FCO4 is the signal P and U which perform the pop-up process of the register SR group, and the AND gate A2.B in FIG. 8B. It is applied to A4°...etc.

Therefore, the contents of register SR5 are stored in register SR4.
The contents of R2 are moved to SR1 using the previously described pop-up process.

At this stage, as shown in the first line of step 14 in Figure 14, the line immediately after the generation of the set output signal FCO4, the sum B+C is stored in register ACC, and the contents A of registers SR and 2 are stored in register SR1. Pop-up processing is performed and stored.

At the same time, this set output signal FCO4 is connected to the ant game 1 with the negation signal of the 'I' LSD as the other input of FIG. 8A.
It is applied to OR game 1-OR5 through -A52, and is applied to AND gate A33.

The other input of this AND gate A33 is a register TR.
Since the output of LSD + 1st digit is applied, and the Antogame 1434 is closed by impark I22, the content of TR is shifted to the right and circulated in the range from time LSD + 1st digit to MSD, and this content is held. Ru.

As shown in the first line of line 7'II of Figure 14, up to this stage, the register TRI-J is shifted to the right by one digit and the LS
The expanded code signal O is stored in D at the LSD+1st digit.

Next, the set output signal FeO2 of flip-flop FC4
is also based on the OR gate OR8 in FIG. 8B, so the AND gate A44 opens and sets the flip-flop FC1.

At this time, since the code signal O is stored in the LSD+1 digit of the register TR by the previous shift to the right by one digit, the AND gate A48 is opened as described above, and the flip-flop FJ is set.

As a result, at the end of signal FCO1, flip-flop FC2 is also set as shown in FIG. 12C.

However, since the key pressed now is the ■ key, the output of the AND gate A51 is prohibited, and the bushdown signals P and D are not output.

Since the set output signal FCO2 of the flip-flop FC2 is applied to the AND gate A43 in FIG. 8A, it passes through the K] times signal gate 43 and is applied to the OR gate OR5.

Therefore, the register TR is shifted to the right by one digit in the same manner as when the set output signal FCO4 of the flip-flop FC4, which occurred earlier, is applied to the OR gate OR5 within the time period shown in FIG. 12C.

This stage is shown as the second step row in FIG. L.S.D.
The multiplication code signal 3 is stored in the +1 digit.

When the LOCKey is pressed, the same process as the LOCKey is performed as shown in FIG. B+C11
and the contents A of the register SR1 in the arithmetic execution circuit 6, and store the answer AX (B+C'') in the register ACC as shown in the step ■ line in Figure 14, and the contents of all other registers are zero. Complete the mathematical processing of AX(B+C')=.

Next, a third embodiment, which is different from the first and second embodiments, will be described with reference to FIGS. 16 to 31.

Here, definitions of terms used in the third embodiment are described below.

(1) - Primary: Constant, variable, or arithmetic expression enclosed in parentheses Example 3.14, RM, (5+2.5) RM is data called from memory and is treated as a variable.

(2) Factor (Factor) Nijiji or Factor ↑-Next child Example 4.56, 4.56↑3, RM2↑RM1;
(3) Term'factor or term/factor or term*
Factor example 2/3. RM1*3.5*4.5/RM2 (4) Arithmetic Expression'
): The term is ten terms or an arithmetic expression -1, 23, 5+3-4* (RMI-2).

2↑3+RM2/3 The execution order in the formula is (1), (2),
It is assumed that (3) and (4) become weaker in this order, and when operators of the same strength are lined up, they are executed from the left.

Also, from the definition in (4) above, addition and subtraction processing by pressing El and El 10-keys means converting term data into arithmetic expression data, and from definition (3), multiplication and division processing by pressing El and 9 keys means It means the difficulty of converting factor data into term data.

Detailed definitions of the above terms are provided by the Japanese Industrial Standards Committee (
Published by the Japanese Standards Association, revised issue March 1, 1972, ) JI
S computer language AL()OL (level 7000')
JIS, C, 6210, page 6.

FIG. 16 is a block diagram showing a third embodiment of the arithmetic device of the present invention, and 1 is a keyboard having various arithmetic command keys, a parenthesis key, an equal sign key, numeric keys, etc.

By simply pressing down each key on the keyboard in order directly according to the formula, even complex formulas can be easily calculated as in the first and second embodiments.

Reference numeral 20 denotes a control unit that performs various controls for arithmetic processing according to this formula.

6 is a control circuit for performing four arithmetic operations, and registers 7.
8. Controls the four arithmetic operations performed between 9 and 9.

Eight of them, ER, are accumulation registers (
7 registers BR with this register as the center.

The register CR 9 is controlled in a continuous manner to perform calculations, and in addition, the register 8 is also used as a register for storing the factor defined as described above according to this embodiment.

Of course, the factor register may be provided separately.

15 and 16 are normal memory registers used for special function calculations, constant multiplication, etc.

21 to 24 are the terms (Te
rm) as a storage register PR, and one term is stored in correspondence with one register.

In the movement between each register PR, AND gate Ag3.
Ag5. Open Ag7 and go from PR1 to PR2...
The process of sequentially storing PR(n-1)→PRn is called bushdown, and the AND gate Ag8. Ag6
．． A, 94. Open Ag2 and PRrr-+PR(n
-1)・・・・・・Pop up the reverse process like PR2 → PR1, store several things in order like this, and when you want to take them out, you can do it in the reverse order in which they were stored. As in the previous example, the stack consists of the last stored item or the first configured item that appears.

Registers 25 to 28 QR consist of a stack like PR,
Arithmetic expression according to the above definition (Ar i thmet i
cExpression) is stored.

29 to 32 are each 1-bit flip-flop FD, which also constitutes a stack.Among the operators defined above, sometimes ÷(
Only the calculation of 1) is stored.

Reference numeral 33 denotes a flip-flop FE having a 1-bit configuration and storing the operation value ↑).

AMI to AM4°Ag1 to Ai4 are AND gates that control movement between each register and between each flip-flop.

0g1 to 0g12 are also OR gates.

Using the total mathematical expression AX(B+C')= as an example, the configuration and operation of this third embodiment will be explained with reference to FIGS. 16, 19, and 20A.

First, press the clear key ■ Register P shown in Figure 16
The control unit 20 performs control to store the numerical data signal 1 in the LSD of R1 and clear and reset all other registers and flip-flops.

This can also be done by turning on the power key.

Next, data A is first entered and stored in register ER.

When the (2) key is pressed, processes A and B are performed in the control section 20 and stopped as shown in FIG. 19C.

In process A, as shown in FIG. 19J, the control section 20 determines whether the flip-flop FE is set or reset, and processes as shown.

That is, since the exponentiation key [Z] is not pressed this time, the flip-flop FE is not set and the process immediately returns to the process B shown in FIG. 19.

In process B, the control unit 20 determines whether the flip-flop FD1 is set or reset 1.

FDl is a flip-flop that is set when Issei - is pressed, and in this case it is in the reset state, so it goes to the bottom and goes to PR1*E? The processing of PR1 is performed by the arithmetic execution circuit 6.

This indicates that the contents of well-known registers PR1 and ER are multiplied by the arithmetic operation execution circuit 6, and the result is stored in PRl again.

Now, the contents of PR1 are as shown in the line of step A in FIG. 20A.<1 in the LSD digit, 0 in other digits. Since the content of ER is A, the multiplication result is also A, and the content of ER is A as before, but this A is a constant that is the -order of the data A of the -order or factor. Since it has been multiplied by 1, it is no longer a factor, but a term by the above definition.

Therefore, the term data A is stored in the register PR1 that stores term data.

The arithmetic control of this process B is one of the characteristics of this embodiment.

Next, a pushdown process is performed as shown in FIG. 19f when the [key is pressed, and then the same process as when the clear key "Y" is pressed in FIG. 19g is performed under the control of the control section 20.

The pushdown is the and gate as mentioned above, 13. A
This is shown in FIG. 19(m) by opening g5°A, l and storing data between each register.

As a result, the contents of register BR are 0. PRl's LSD or 1
The others are 0, and data A is stored in PH1.

Next, when data B is entered, it is stored in register ER,
Then, the lokey is pressed.

[Lokey processing is as shown in FIG. 19a.

Since process A does not involve exponentiation calculations as described above, the flip-flop FE is in the reset state, so the process moves to process B.

In process B (FIG. 19k), as described above, since flip-flop FD1 is not set, PR1*ER1 is performed.

As shown in step B of FIG. 20A, the contents of the register PR1 immediately before this are 1. Since the content of ER is B, a multiplication operation of IXB is performed, and factor data B is converted to term data B, which is stored in term storage register PR1.

When processing B is finished, as shown in Figure 19a, QR1+PR1→
QR1 is performed, the content B of PRI is added to the content 0 of the arithmetic expression storage register QR1, the term data is converted to arithmetic expression data, and the result is stored in the arithmetic expression storage register Q.
Store in R1.

This is because according to the above definition, addition processing was performed on the term data B and an arithmetic expression whose contents happened to be O, so O+B(
Since the arithmetic expression becomes the arithmetic expression (10 terms), the arithmetic expression data B is stored in the arithmetic expression storage register QR1.

Next, 1 is stored in the LSD digit of the register PR1 again, and the locking process is completed.

The contents of each register are as shown in step ``Maternity'' in Figure 20A.

Data B, which was assigned data C and stored in register ER, is cleared, and data C is stored in its place.

``When the old key is pressed, the process shown in FIG. 19i is performed.

Process A moves to process B since the flip-flop FE is reset as described above.

In process B, flip-flop FD is reset and PR
IXER→PR1 is executed.

In this case, register PR1 is 1 and register ER is stored with C, so a 1×C multiplication is performed and the factor data C
is converted into term data C and stored in result C or PRl.

Next, QR1+PR1→QR1 is performed.

Since C is stored in PRl and B is stored in QR1, B4
The addition operation of C is performed, and the result B+C is stored in QRI, and then this stored content is the arithmetic expression enclosed in (), so it is the second child or factor, and is transferred to the factor storage register ER. AND gate AJ' for register contents group
16,A,? 14, AgI2.

Open Agl0 and perform popup processing.

As a result, the data B+C stored in the QRI is erased, and the contents of the register become as shown in the second line of FIG.

When the equal sign key for obtaining the final result is pressed, processing as shown in Figure 19 is performed.

As described above, the process A performs the pass-through L process B.

In process B, FD reset also causes Perform PRI XER-+PR1.

Since the contents of each register are as shown in Figure 20A, multiplication by AX (B4C') is performed, and the result is A.
Since ×(B4C) is the term A*factor (B10), it is also term data and is stored in the term storage register PRI.

Next, perform QR1+PR1→QRI. Since the content of QRl is O, the addition result remains the same, or the data is converted from a term to an arithmetic expression, so the arithmetic expression A+(B+C') becomes Q.
It is stored in Rl.

Furthermore, AX (B4C) is stored in QR1→ER, the result is displayed or printed, and the arithmetic processing ends.

Thereafter, as shown in FIGS. 19g and 19h, post-processing similar to that performed when the clear key "mouth" is pressed is performed to prepare for the next mathematical expression processing.

This is a process in which 1 is stored only in the LSD digit of the register PR as described above, and all other digits, other registers, and flip-flops are cleared and reset.

In this way, even if you add the value O to some numerical data, the value is 1.
By skillfully taking advantage of the property that the value of numerical data does not change even when multiplied by , it is possible to calculate a mathematical formula by key operations that directly follow the mathematical formula, with a simple configuration and processing control. It is.

The above is an outline of the configuration and operation of the block diagram shown in FIG. 16, but FIG. 17 13H shows an example of the detailed specific circuit shown in FIG. 16.

The detailed structure and operation of the circuit shown in FIG. 17 will be explained below.

FIG. 17 mainly discloses internal details of the control section 20 shown in FIG. 16.

In the drawing, 0g14 to 0g38 are or gates, AJ'
25 to A, li'34 are AND gates, and F1 to F7 are the illustrated [EI, II, , , , , , [Z]
When the child key is pressed, the next key signal is +, 1, etc.
・Flip-flops that generate hKi, CFO to CF5
are flip-flops that generate basic control signals CCO to CC5 for controlling the opening and closing of each gate shown in FIG.

Registers PR2 to PR4 and registers QR2 to QR4 remain in the configuration shown in FIG. 16, and the data in register PR1 and register QRI are simply subjected to push-down and pop-up processing.

Note that, unlike the first and second embodiments, the third embodiment uses a static shift register and operates in an asynchronous manner, showing that the present invention can be realized using either circuit.

It should be noted that it is of course possible to configure the first and second embodiments in an asynchronous manner using static registers, and the third embodiment in a synchronous manner using static registers.

In addition, the operation execution circuit 6 shown in FIG. 17H and the multiplication, division,
The exponentiation, logarithm, addition instruction generation circuits 34 to 38, etc. can easily implement the present invention using conventionally known techniques, so detailed disclosure and explanation will be omitted.

However, to add a rough explanation, for example, when the multiplication instruction generation circuit Mult34 operates, A, DDER executes X*Y multiplication by repeating addition of X and Y input information according to its control, and the multiplication is output as ADDER's output ADDO. It is possible to obtain the product that is the result of the execution.

Next, the detailed circuit configuration will be explained.

In FIG. 17A, flip-flops F1 to F7 are flip-flops that are set when the X key is pressed. KX.

K÷, 2, K) KX, u.

All of these key signals except for the score pass through the OR game 1-014 and become the OR game output KOR.

Flip-flops CFO-CF5 have complex control gates between their stages, but are basically similar to a ring counter configuration, generating set output signals CCO-CC5 sequentially, never overlapping or occurring simultaneously. I don't do that.

The flip-flop FE is equipped with AND gates Ag26°Ag25, etc. at its set and reset inputs, and its set and reset inputs are
Reset is controlled.

Also, its set and reset outputs are AND gate A927
．． Applied to A92B, mainly control signal to CCO
It has a function to distinguish whether to generate from CC5 to CC5 or from CC3 to CC5 depending on whether or not the exponentiation key has been pressed.

The flip-flop FD1 connects an AND gate A to the set input terminal so that it is set when the division key is pressed.
g29 and an OR gate 2 at the reset input terminal.
0, and is reset under various conditions as shown in the figure.

FIG. 17 shows a gate configuration when a bushdown signal is generated.

As shown in the figure, when the key signal Kl or K] is generated, the pushdown signals F and P are generated at the time of the control signal CC3.
, D, PQ, P, D are generated.

FIG. 17C similarly shows the gate configuration when a pop-up signal is generated.

As shown in the figure, pop-up signals F, P, U, PQ, and PU are output in response to generation of control signal MCC5 or control signal CC2 when key signal K] is generated.

Figure 17 shows a configuration in which a general One John Multi O8 is activated and generates a clear signal KC when the clear key is returned after being pressed.

Figure 17 E, F, and G are factors ER and P.
R1 and gate 1 are connected to the input terminals of arithmetic register QR1, respectively, and are included in the control section 20 of FIG.

The individual functions of these gate groups will be gradually clarified in the subsequent explanation of their operations.

However, the operation of these gate groups is a particularly important part of this embodiment.

In FIG. 17E, the or gate 0g23°0g24.
AND gate Ag by the output of AND gate Ag35 etc.
37 is opened and the ADDER output ADDO of FIG. 17H is stored in the factor register BR.

Ant game 1-Ag38 is a circulation gate for self-holding the contents of the register ER, and the signal CC3 or CC4and
When K, j', open and circulate.

In FIG. 17F, the AND gate Ag39 is connected to the signal CC3.
When and KOR, an output signal is generated, and at this time or when Krand CC4, AND gate Ag40 is opened and the output ADDO of ADDER is stored in ring register PR1.

Also + for key signal. K-, K(, KC, are second-guessed and ant game is applied to LSD of register PRI before signal CC5.
1 to AL42, 1943 are opened and numerical data signal 1 is stored.

Also, when -, 1 is stored in LSD and Sig
Signal 1 is also stored in the nth digit, and the data stored in the register PRI is handled as a negative number and processed.

Also, pop-up signals PQ, P'. Uka Antogame-14
When applied to J'44, the contents of register PR2 are stored and popped up.

In FIG. 17G, when the key signal is + or -, the output ADDO of ADDER is stored in the arithmetic register QRI when the control signal CC4 is present.

Also, the pop-up signal opens the AND gate Aa945, and the contents of the register QR2 are returned to the register QR1.

Ant game 1 is connected to the × input terminal of ADDER in Figure 17g.
-A18. Ag47, or gate 0.934゜0g33
etc. are connected to the Y input terminal, and an OR gate O, ? is connected to the Y input terminal. 3
6,0g35, AND gate A, F50, etc. are connected.

AND gate Ag48 is the signal CCO, KORandCC
3. +, K -, = on the keys.

When the signal CC4 is generated when a signal such as K] is generated, it is opened and the output content PRIO of the disk PR1 is applied to the × terminal.

Also, when an output signal is generated in Antogame 1147, Antogame 1-A and F49 are opened and arithmetic register QR1 is output.
The output content QR10 is applied to the Y terminal.

Or the signal CCI input to the OR gate 0.935,
AND gate Ag50 before KOR, K”-CC4 etc.
is opened and the output content ERO of the factor register ER is applied to the Y input terminal.

Next, the specific operation will be explained based on the example of the mathematical formula A+gX(D+E')=.

As in the previous example, when the clear key C is pressed, the clear key shown in Figure 17 is turned on, the signal KCH is generated, and all registers and flip-flops in the computer are cleared and reset.

When the clear key is reset, the one-shot multi-bye break O8 is triggered by the rise of the signal KCH as described above, and the clear signal KC is generated from O8 as shown in FIG. 18A.

Since this clear signal KC is applied to the OR gate 016 in FIG. 17A, it sets the flip-flop CF3 via the OR gate 0g17 and sets the set output signal CC3.
After that, as shown in FIG. 18A, the set output signal C is generated.
At the falling edge of C3, the flip-flop CF4 is set and a set output CC4 is generated, and at the falling edge of this signal CC4, the flip-flop CF5 is also set, and the output signal CC4 is set.
Generates 5.

When the flip-flop CF3 is set to 1, no particular operation is performed, and the contents of the register ER shown in FIG. 17E are cleared during the time when the set output signal CC4 is generated when the next flip-flop CF4 is set. It will be done.

That is, at this time the clock pulse C to the register ER
If P is applied, the contents of register ER are all shifted to the right, and at this time, AND gates AJ'36 and Ag
Since 2S is not open, the shifted contents cannot be circulated, and therefore the contents of register ER are cleared again.

When the flip-flop CF5 is set, the output signal CC
5 is applied to one input terminal of the AND gate Ag43 in FIG. 17F, and the OR gate O! The clear signal KC applied to the AND gate 9'27 opens the AND gate 1-4J' 42 at the least significant bit time of the register PR1, so that the AND gate Ag43 outputs 000 in binary code.
The numerical data signal 1 is stored in the least significant digit (LSD') of the register PRI in 1, decimal code, and O is stored in all other digits.

Since the clock pulse CP is also generated at the time when the output signal CC5 is generated, the register QR1 in FIG. 17G is also cleared in the same manner as the above-mentioned clearing operation of the register PRI.

Since the signal CC5 also opens the AND gate Ag25 in FIG. 17A, it passes through the OR gate 0g20 and resets the flip-flop FD1.

Furthermore, the output signal of AND gate 1'25 is OR gate 0
The flip-flop FE is reset through g18.

With the above operations, all the processing after pressing the clear key in FIG. 19g is completed.

The appearance of control pulses generated at various locations is shown in FIGS. 12A and 12B.

Numerical data A is then stored in register ER in a well-known manner.

Next, the ■ key is pressed and the flip-flop F4 is set in FIG. 17A.

This set output signal is divided by the key signal, passes through an OR gate (1'14), and becomes its output signal KO, R, which passes through an OR gate og15 and is applied to an AND gate Ai7.

In this case, the exponentiation key [Z] is not pressed, so it is set, so the AND gate Ag27 does not open.

Instead, the reset output of the flip-flop FE opens the ant game 1-Al1, so when the above-mentioned clear signal KC passes through the OR gate 0g16, the OR gate 0g17 opens due to the same operation, and the flip-flop opens as shown in the 1-hour column of FIG. 18A. CF3゜CF4. CF5 is set sequentially, and output signals CC3, CC4, and CC5 are sequentially generated.

While the signal CC3 is being generated, the output signal K of the OR gate 0g14
OR is AND gate AJ'51, Ag5 in Figure 17H.
However, since the flip-flop FD1 is not yet set at this time, the AND gate A, 952
is opened, and the multiplication instruction generating circuit Mult 4 is activated.

At this time, OR gate 0g34 is generated by signal KO3/CC3.
Since an output signal is generated at the AND gate 1'48, the content output PR10 of the register PRI is applied to the × input terminal of ADDER in the arithmetic execution circuit 6. -1
-Ag50 is also opened, and the content output ERO of register ER is A.
Applied to the Y input terminal of DDER.

Therefore, ADDER is the multiplication instruction generation circuit Mult.
By controlling the output of 34, a multiplication operation by repeating addition is also performed using resistors BR, CR, etc.

That is, the multiplication operation of IXA is performed with the content 1 of register PRI and the content A of register ER, and the resultant product A is converted from a factor to a term as defined above, so a register PR1 dedicated to storing terms is used. is stored in

This is the AND gate in Figure 17F, B39. l'40 is opened and stored in PRl as the output ADDO of ADDER.

Nothing is done during the generation time of the subsequent signal CC4, and the AND gate Ag2 in FIG. 17A is activated by the generation of the next signal CC5.
9 is opened, and the flip-flop 'FD1 is set to remember that the division key 2 has been pressed.

When numerical data B is entered, the previous numerical data A stored in register ER is rewritten to B.

When the exponentiation key [Z] is pressed, the flip-flop FE that remembers that the [Z] child key has been pressed has not yet been set until just before that.
Antogame)-A, 1927 is not opened, and the flip-flops CF3 to CF4. CF5 and the above-mentioned upper signal CC
3, CC5 occurs.

Now, during the generation time of signal CC3, AND gate A, 931 in FIG. 17B is open, and its output signal is
PR5, the bushdown signals PQ, P, Dc of the register group QRI to QR5: become, Antogame 1-A in FIG.
,91,A,! i' 3 , A, 95° A, l and AND gate A, 99 , A & 11 , A, ? 13°Ag15 is applied, and the register groups PRI to PR5 and register groups QRI to QR5 are subjected to bushdown processing, respectively.

Also, the AND gate AJ'17. of the 1-bit stack FD1 to FD5. Ag19゜Ail, also to A13 Fig. 17B
A 1-bit output signal of AND gate Ag32 is applied, and bushdown processing is performed.

Therefore, the contents A of the register PR1 are transferred to the register PR2, and the 1-bit stack flip-flop FD1 is transferred to the register PR2.
The contents will also be transferred to FD2.

Also, FDl is AND gate A, ? Since a negative input is applied to 19, it is reset.

While the next signal CC4 is being generated, the logarithmic operation instruction generating circuit Log10x at 37 in FIG.
is opened and the content output ERO of register ER is applied to the Y input terminal of ADDER.

Also, at this time, there is no data signal input to the × input terminal of ADI)ER.

This ADD-ER is converted into a logarithm operation instruction generation circuit Log1oX
is activated by the output control of register BR to L.
It is converted into Og+oB and the resultant L o g 18B is stored in register PR1.

In the next signal CC5, the AND gate A of FIG. 17A, @2
6 opens, so G passes through AND gate Ag26 and sets flip-flop FB to the set output signal of flip-flop F7, which was set when key □ .

Next, data C is assigned, and the previous data content B in register ER is rewritten to C.

Up to this stage, as shown in step 0 line of FIG.
Ring data log 1°B and A are respectively stored in H1.

Next, when the ward key is pressed, the flip-flop F3 in FIG. 17A is set and generates an x in the key signal.

Since the flip-flop FB was set in the previous step, the analog gate 14J'27 is now opened, the flip-flop CFO is set, and the set output signal CCO is generated as shown in FIG. 18A.

When the signal CCO is generated, the OR gate (13
Since an output signal is generated at 7, the multiplication instruction generating circuit Mult34 is activated as in the case of the yaw key described above, and AND gate A and 18°AJ'50 are opened, so the X and Y input terminals are connected to the register PR1. The content output PR'IO (currently stored data is LogloB) and the content output ERO of register ER (currently stored data C) are applied, so use ADDER to Mult Logl, )B XC
34, and the resulting product CLo g
, oB (=Log16BC) are opened in the register ER by opening the AND gate 1'37 in FIG. 17E.

Next, when the signal CCO falls, the flip-flop CF1 is set and a set output signal CCI is generated.

Signal CCI is the exponentiation operation instruction generation circuit 10 in FIG. 17H.
Start X36.

Also, since the AND gate 1'50 is opened, the contents of the register ER (LogloBC) are multiplied by the exponentiation operation instruction generation circuit 10.
Under the control of X35, ADDER performs a 10X operation on the contents of register ER, that is, 10Log1 (IBC), generates the result Bc, and opens AND gate Ag37 in FIG. Store in ER.

When this is completed, flip-flop CF1 is reset and flip-flop CF2 is also set.

This set output signal CC2 is
g22, its output signal is applied to register group P
R, QR, 1-bit stack FD pop-up processing command signals PQ, P, U, F, P, U, so the AND gates A, ? 8. Ag6°Ag4. Ai (17th
AL44 in Figure E) and AND gate Ag16, AJ'
14, AJ'12. A, 910 (Ag4 in Fig. 17 G)
5), and ANDGATE A, 924. l'22. A.J.
'20. Open Ag18 and perform pop-up processing.

This means that since a bushdown process was performed when [Keylo] was pressed earlier, the state has been returned to the state before that process.

Further, since an output signal is generated at the OR gate 0g18 in FIG. 17A, the flip-flop F, [-1J is set, and the AND gate Ag28 is opened, so that the flip-flop CF3 is set at the same time as the signal C02 falls.

This set signal CC3 is applied to the AND gate A in FIG. 17H.
,? 51 and Ag52, but since the ■ key was pressed first and the flip-flop FD1 was set,
An output signal is generated at 151, which activates the division instruction generation circuit Div35.

Also, and gate A5+48. Since Ag50 is also opened, the output content A of register PR1 (l!l- output content Bc of register ER) executes the division operation (A+B0) in ADDER under the control of Div35, and the resulting quotient A7T3° is The data is stored in the register PRI by opening the gates 1-A and 10 in FIG. 17F.

Since this is ring data according to the above definition, it should be stored in the term storage register PRI.

The flip-flop FD1 in FIG. 17A is reset by the end signal End of this division operation.

During the next sequentially generated signals CC4 and CC5, no control or execution is performed.

Next, when the trolley is pressed, or game 1 in Figure 17A is pressed.
Since an output signal is generated at -0g16, the flip-flop CF3. CF4. CF5 sets sequentially, producing signals CC3, CC4, CC5.

When Shinbuki C3 occurs, the anime game in Figure 17B)Ag
31 opens, registers PR1 to PR5, register QR1
-QR5,1 Bushdown signals PQ, P, D, F, P, D are generated for the bit stacks FD1 to FD5, and the bushdown processing of each stack is performed in the same manner as described above.

Until this key is pressed, data B is stored in registers ER and PR1, respectively, as shown in step X line of FIG. 20C.
'jA+B' is stored and other registers PR2 to PR5
, QR1 to QR5 all have 0 stored contents.

Flip-flop FD1 is also in a reset state.

When this state is shuffled down, the contents A+B'' of PRl are stored in register PR2.

Further, the contents B0 of the register ER are temporarily stored in the register PRI by opening the AND gate lil1 shown in FIG.

However, since the register ER is set to store factors and the register PR is set to store terms, this data movement does not fall under the concept of bushdown processing.

In fact, the data B stored in register PRI is cleared by the multiplication C5 that occurs later.

Now, when the signal CC3 falls, the signal CC4 is generated as described above.

The OR gate 0g25 in FIG. 17E generates an output signal by the previous signal CC3, and the AND gate Ag38 opens to circulate and hold the contents of the register ER, so the contents B0 of the register ER are moved to the register PRI first. Since the data B0 still remains even if the signal CC3 falls, AND gate Ag39 is closed at the same time as the signal CC3 falls, and its contents are cleared by the operation described above by shifting it to the right with the clock pulse CP generated while the signal CC4 is being generated. do.

When the signal CC4 falls and the signal CC5 is generated as shown in FIG. 18A, the register PR1 is shifted to the right by the clock pulse CP generated during the generation time of CC5 in the same manner as described above, and its contents B0 are cleared. , also opens the AND gate A, 943, and sends the numerical data signal 1 to the register PR.
Store it in I's LSD.

Also, register QR1 is cleared by the same operation as when register PR1 was cleared.

Furthermore, since the AND gate AJ'25 in FIG. 17A opens in the same way, the flip-flop FDI is reset.
This has already been reset, so there is no change.

Similarly, the reset signal enters the reset state of the flip-flop FE, and there is no change in the reset state.

Next, when data D is entered, it is first cleared and the contents are stored in the empty register ER.

When the [Next] key is pressed, the flip-flop FE in FIG. 17A is in the reset state, so the flip-flop F1
The set output signal + opens AND gate A28 and sequentially generates signals CC3, CC4, and CC5.

When the signal CC3 is generated, the flip-flop FDI has been reset in FIG. 17H, so the AND gate Ag5 is generated.
2 opens and starts Mult34.

Also, AND gate Ag48. Since AJ50 also opens, PRI is set in ADDER under the control of Mult34 as described above.
Executes the multiplication of XER, that is, IXD, and stores antgame-14g39. in the term storage register PR1. A, using lO
The output of DDER is converted to ADDO and the resulting product is stored.

Further, the OR gate 0g25 in FIG. 17E also generates an output signal based on the signal CC3 and opens the AND gate l'38, so that the contents of the register ER are held as they are.

Next, when signal CC4 is generated, OR gate 0 of FIG.
Since + is applied to the key signal which is the set output of the flip-flop F1, an output signal is generated in F33, so that the analog gate (A) 17 is opened and the addition instruction generating circuit ADD38 is activated.

Further, AND gate Ag48 is opened, and AND gate Ag49 is also opened, so ADDER executes QR1+PR1 according to the addition control command of ADD38.

The current content of PRI. Since the content of QRl is 0, the result is 0+D=D, and the sum is stored in register QR1 by opening AND gate Ag46 in FIG.

This means that, as defined above, the data D is stored in the register ER as a factor, then is multiplied by 1 and converted into a term.
Since 0 was added to the ring data D and converted into an arithmetic expression, it was stored in the arithmetic expression storage register QR1.

When the next signal CC5 is generated, the register PR within that time
1 LSD time 'l' LSD least significant bit time (L
SD), the AND gate A,,12. A, 943 opens and stores numeric data signal 1 in the LSD of register PR1.

Figure 20C shows the contents stored in each register when this is completed.
The step country row shows.

That is, each data Ds 1 , A+B', and D are stored in registers ER, PRl, PH1, and QRl, and all others are 0.

Next, when data E is assigned, it is stored in register ER.

Next, when the {circle around (2)} key is pressed, the flip-flop FE in FIG. 17A has been reset, so the signals CC4 and CC56 are generated in order from CC3 as described above.

Also, since the flip-flop FD1 is also reset,
Signal CC3 opens AND gate A, 952 of FIG. 17H and activates Mult34.

And Gate A again! i'48. Since AJ'50 is also opened, execute <PRIXBR (=IXE) with ADDER as described above, and the product E is calculated using the AND gate A5' in Figure 17F.
40 is opened, so it is stored in register PR1.

The signal CC4 opens the AND gate Ag47 in FIG. 17H and activates the ADD38.

Also, since AND gate Ag48°Ag49 also opens, AD
QR1+PR1 (=D+E) is executed in DER, and the sum D+E is stored in the register ER since the AND gate AJ'35 in FIG. 17E is opened, and is output to the output device O.

This is the definition given above, and since the data D+E is an arithmetic expression and is enclosed in parentheses as (D+E), it returns to the -order or factor take, and is therefore stored in the factor storage register ER.

The signal CC5 is generated in the ant game-1-A of FIG. 17C, @
33 is opened, the pop-up processing command signals F, P, U,
PQ, P.

Therefore, as mentioned above, registers PR,1 to PR5,
Pop up QR1-QR5, 1-bit stack FDI-FD5.

This will restore the state that was previously pushed down by the ■ key, so as shown in the step-line in Figure 20, register PRI contains the contents of PH1, A+B0, and register PR2 contains the contents of register PR3. O is register Q
The contents O of register QR2 are moved and stored in R1.

Furthermore, the data D previously stored in the register QRI jumps out of the register QR1 and is erased.

Therefore, at this stage, the register ER. Data D1E and data A+B0 are stored in PRl, and all others are stored as O.

Now, finally, press the key. As before, the flip-flop FE has been reset, so the Antogame 1-AJ" 28 in Fig. 17A opens, and the signals CC3, CC4, CC5
occurs.

Since the signal CC3 is reset by the flip-flop FD1 in FIG. 17A, the AND gate 1'5 in FIG. 17H
2 and start Mult34.

Also, AND gate A, 948, 150 opens, so PRl
XER, that is, the multiplication operation Mu of A/B0x (D+E')
This is done with ADDER under the control of lt34.

As a result, the output ADDO is A/B0X(D+E),
This is stored in the register PR1 through the game hl'40 in FIG. 17F.

The next signal CC' 4 is ANDK A of FIG. 17H, .
? 47, start ADD38 again, and open AND gate A, 948°1949, so QR in ADDER
1+PR1 is performed.

Now the content of QRI is 0, so the content of PRl is A/B'X
The value of (D+E”) remains unchanged.

As mentioned above, since the addition process of O+ was performed, the contents of PRI should have been stored in the arithmetic expression storage register QR1, but since the key was pressed, the contents of PR1 A/B
'X(D+E) does not change its value from now on; therefore, it ceases to be an arithmetic expression and becomes a constant.

Since the constant is both a primary child and a factor, similarly when the key "mouth" is pressed, the AND gate Ag35 in Figure 17E is
is opened, and the AND gate AJ'37 is opened to store the output ADDO of ADDER, that is, the content A/B'X(D+E') of PRl, in the factor storage register ER.

When the signal CC5 is generated, in order to prepare for the next calculation, the operation is the same as that of the <[E] child key 3 key, that is, the registers PR1, QR1゜flip-flop F are activated as shown in Figure 19.
D1. Clear and reset each FB, register PR1
The numerical data 1 is stored in the LSD, and all processing ends.

This state is shown in the second row of steps in FIG. 20C.

Also, the intermediate results of calculations of these formulas are, for example, A9BQc.
EIEND ■ In the case of E[, E] key operations, A, B, C, Bo, 0, . D.E.

D1E, A/B0. (D+E) Can be displayed or printed.

This is done by connecting the output of register ER to output device 0 in FIG. 16.

When the subtraction key is pressed, the AND gate AJ'41 in FIG. 17F opens at the timing of the Sign digit of register 1, stores numerical data signal 1 in the Sign digit of register PR1, and performs subtraction processing .

Therefore, in FIG. 17H, there is a special subtraction instruction generation circuit SUB.
Even if the ADD 38 is not required, the ADD 38 can be used for both purposes, simplifying the overall circuit configuration.

As described above, this third embodiment converts term data into arithmetic expression data by pressing the a and a keys, converts factor data into term data by pressing the country key in Figure 1, and converts factors, terms, and arithmetic expressions. By storing the data in each data storage register and processing them in a push-down and pop-up manner, it is possible to automatically obtain the answers to complex mathematical expressions by key operations that directly follow the mathematical expressions.

Furthermore, the above definition that an arithmetic expression includes a term, a term includes a factor, and a factor includes a primary child ultimately means that the arithmetic expression also includes a primary child, and using this idea, Because of the process control, even complex mathematical expressions can be executed with simple key operations using an extremely simple circuit configuration by simply inputting mathematical expressions in a format that directly follows key operations.

Furthermore, in the first and second embodiments, the execution time for operators + and -5÷ is almost the same, so adding an operator (for example, ↑
), changes in other circuit configurations due to deletion, etc. can be minimized as much as possible.

In addition, the third embodiment can easily output the result during an operation, and unlike this embodiment, it does not require a register TR that stores all operators, but instead uses a flip-flop that stores at least either × or ÷. This can be achieved only with the FD1.

Constructing a stack such as FD1 to FD5 by using a large number of FDs is an extremely complicated mathematical formula, and even in the case of FIG. 20C of this embodiment, only two FDs are required.

Also, as defined above, when an arithmetic expression is wrapped in ), it becomes -, which is also a term with factors, and becomes an arithmetic expression again.By repeatedly using this rule, for example, ( [([......))))] etc., the answer can be obtained indefinitely by repeating the operation of a finite circuit configuration, making it economical and easy to miniaturize. It has the following.

[Brief explanation of drawings]

To give a brief explanation of the drawings, FIGS. 1A and 1B are diagrams illustrating the difference between the key operation method of a conventional computing device and the key operation method of the device of the present invention, and FIG. A block diagram of the embodiment, FIG. 3 is a detailed diagram of a part thereof,
FIG. 4 is a flowchart explaining the operation, FIG. 5 is a rule table determining the priority order of calculation execution in the first and second embodiments of the present invention, and FIGS. 6A to 6F are each of the embodiments in FIG. Figure 7 is a block diagram of the second embodiment of the present invention, and Figures 8A and B are one of them. FIGS. 9A and 9B are detailed circuit diagrams of the keyboard section, and FIG. 10 is a schematic diagram of the keyboard section that generates each key signal, and FIG. 11A is an example of the basic control signal generating circuit. B is an example of the control signal generated by the circuits in FIGS. 9A and B, FIG. 11C is a waveform diagram explaining how the key scoot signal is generated, and FIGS. 12A-D are the A×(B+C)- Figures 8 to 10 show the signals generated when calculating a mathematical formula, and are diagrams explaining their operations.
FIG. 10 is a timing chart explaining the operation of the second embodiment; FIGS. 13B and C are flowcharts explaining the times and order in which the flip-flops FC1 to FC4 are set corresponding to the flowchart; FIGS. 14-15; Figures 7 to 10 show register content movement in the case of concrete calculation examples of the second embodiment, Figure 16 is a block diagram of the third embodiment of the present invention, and Figures 17 A to H show its control. A concrete detailed circuit example of part 20, FIG. 18 A and B are formulas A+BCX(D+E)
- A timing chart explaining the operation when the calculation is performed in the third embodiment, FIG. 19 is a flowchart explaining the operation, and FIG. 20 A, B, and C are examples of mathematical formulas explaining the operation. The contents of the register are moved based on . In the drawing, 1...keyboard, 2...
...Encoder, 3...Instruction key signal storage register, 4...;...Comparison/discrimination circuit, 5, 20...
...Control unit, 6...Four arithmetic operation control circuit, 7-
9... Arithmetic register, 10-14.21-2
8...Register for storing numerical values, 29-33・river・
·flip flop.

Claims (1)

[Scope of Claims] 1. In an arithmetic device that is equipped with a numeric data key, a force subtraction/multiplication/division key, and a left/right parenthesis key and performs arithmetic operations by key operations according to a mathematical formula, numeric data is stored by operating the numeric data key, and A display register is connected to an output device in order to visually check the contents. Even if one of the addition, subtraction, multiplication, and division keys is operated after storing numerical data in the display register, the contents of the display register are held as they are, and the next numerical value is A first control means for controlling changing the contents of the display register by pressing a key, and a second control means for controlling storing a calculation result in parentheses in the display register by operating the right parenthesis key. A computing device characterized by: