JPS58179998A - Analog memory - Google Patents

Abstract

PURPOSE:To reduce the disturbance of noise due to uneven characteristics of cell, by changing the position of a memory cell and the correspondence of time series of signals recorded to a memory in terms of time. CONSTITUTION:The input signals are supplied to a basic memory cell group 2 and a redundant memory cell group 3 via a line 1. The output of each cell group is sent to a common line 4. At the same time, both writing and reading are controlled by a common writing and reading control lines 5 and 6 respectively. The cells of the group 3 are selected by redundant cell selecting lines 8-1-8-m (m: number of cells of group 2). An address circuit 9 produces signals to cell selecting lines 7i and 8i for reading and writing with signals applied from address lines 10-1-10-l and address control lines 11-1-11-k. The signal applied to a selecting line 10i designates (n) units of memory cells in response to the time series of the signal. The signal applied to a line 11 changes the correspondence with line 10, 7 and 8 in terms of time.

Description

[Detailed Description of the Invention] The present invention relates to an analog memory, and in detail, relates to an analog memory in which image signals are stored in a large number of analog signal storage elements having a combination of capacitors and switches. .

In image signal processing circuits for television signals and the like, a memory for recording multiple pixel information is sometimes required.

As a device that satisfies such requirements, an analog memory device is known in which an analog memory element is constructed by combining a capacitor and a switch, and a large number of such confectionery devices are combined. Especially MO8 Suyoko technology for switch and condenser +j? Since it can be used in actual applications, a small, low-cost analog memory can be realized, and future developments will be made possible.

However, when converting such an analog memory into an image signal such as a television signal, if the characteristics of many analog memory elements (e.g., troughs, etc.) are not the same, noise will occur in the readout signal, and extraneous screen I'll be standing next to you. This noise is generated due to the unique characteristics of the memory element, and since it occurs constantly at a specific position on the screen, it is easily noticeable and significantly deteriorates the image quality fr.

In order to eliminate such drawbacks, it is necessary to make the characteristics of multiple capacitors and switches the same, but what is the value of such capacitance? It is extremely difficult to match with high precision due to the structure, which increases manufacturing costs.

Therefore, an object of the present invention is to create an economical analog memory cell, that is, to tolerate irregularities in the characteristics of analog memory elements (cells), so that noise due to the irregularities is less noticeable to the human eye on reproduced images. The purpose is to refresh the analog memory that has been used in the past.

In order to achieve the above object, the present invention temporally maintains the correspondence between the positions of memory cells forming an analog memory group and the time series of signals recorded in the memory (for example, within one screen of an image signal). (changes depending on the area on the screen) to reduce interference caused by noise caused by misalignment of memory cells.

That is, in the present invention, the false form on 0fII(2) due to noise is caused by motion? It is said that if it is regular, it is easy to see, if it is irregular (2 random), it is visible if it is V-dense, if it is regular, it is easy to see if it is striped, and if it is checkered, it is not noticeable. It takes advantage of human visual characteristics.

The present invention will be explained in detail below using the drawings.

Figure m1 is a schematic diagram of the overall configuration of an embodiment of an analog memory according to the present invention. In the figure, an input signal is input to a basic memory cell group 2 and a redundant memory cell group 3 via an input line 1. Basic memory cell group 2r1. , a sufficient number of cells to store and process the 100 inputs, for example 11jI of one line of a television signal, and the redundant cell group 3 is intended to serve as a central Is the cell added to do this, a cell with the same specifications as basic cell group 2, but with a smaller number of cells than the number of basic cell group 2?
It includes. The outputs of the cells in these cell groups are output to a common output #4 and become an output signal. Both cell groups are also controlled to receive and continue to appear by a common honor control @5 and successive generation control N6.

The cells of basic memory cell group 2 are selected from basic cell selection 7-1.
7-2. 7-n (n is the number of cells included in basic cell group l), and the cells of redundant memory cell group 3 are selected by redundant cell selection edges s-i, s-2, ... g- m(m
is selected as red depending on the number of cells included in redundant memory cell group 2). Address circuit 9 is address Iwao 10-1.10
-2. ...10-l and address 匍" gosen 11-1.1
1-2. ...by the signal added from 11-k,
Top 6 cell selection for inserting or inserting #7-1
．． ...7-n, 8-1. ... This is a circuit for generating a signal at 1 of g-m.

Cell selection @! The signal g that is passed through signals 7 and 8 selects the cell corresponding to the signal that becomes high level among them (selection may also be made by 0-level), and is used to select a cell corresponding to a signal that becomes high level. Although it is possible to select them at the same time, usually only one is selected.

Therefore, only one signal has a level that designates selection. The signal applied to the address training 10 is a signal for specifying n memory cells corresponding to the temporal thread of the signal, and in the case of a binary signal, t is zog, n
is an integer greater than or equal to .

The signals applied to the address control $11 are the address NlO and cell selections #M7 and #8 in terms of time (in the case of image signals, by position l11 or frame on the screen). In this embodiment, since the television image signal is processed, - the image of the scanning line? Perform recording and output, i.e. wait and scan m
Configure a delay circuit.

It was previously thought that the position of a pixel on a scanning plane corresponds to the position of a memory element for recording in an analog memory.1 However, when the characteristics of the memory elements are not the same, If there is a variation of approximately P periods in , VC vertical stripe pattern noise will occur on the output screen as shown in FIG. On the other hand, in this embodiment, the same memory storage is used, and the vertical stripes are arranged in a checkered pattern as shown in FIG.

Before explaining the configuration and operation of FIG.
The recording and continuous output modes of memories 2 and 3 of 1g1 will be explained. For convenience of explanation, FIG. 3 shows the elements of the memories 2 and 3 arranged in the above-mentioned dimension in a circular arrangement.

It is assumed that the effective number n of pixels of the N4th scanning line is recorded in the memory 2. During the next scan 1IiA (N+1st), the signal recorded in the upper Nth scan is stored in the memory 2,
The wires are laid out in the order of ■, ■, . . . (indicated by RN in the figure). - Force simultaneous VcN + 1st scanning signal is in memory 3
' is stubbornly set to 66 until memory 2 @-m (WN
), - The process of running f# is completed. Similarly, during the charcoal running period, the memory 3 is read out from the 1' period until @ (RN
+1), during which the next running f edge N+2 signal of interest is n
It is sworn with -m as a dot (Ws+, J. This is the address of the read memory cell!! 7m116
1! The operation of writing to the memory at the # address is performed cyclically.

These operations are performed in the second worst address circuit 9 as follows. In the same figure, address No. 16 $11
0-1.10-2.・10-t is n. The digital addition/subtraction circuit 12 inputs (n+
It is a difference output with modulus (-, ]). As the subtraction input of the digital addition/subtraction circuit 12, the digital sword OJ! Consists of circuit 13 and register 14 (n+(i))
The output of the digital integration circuit 15 modulo is f/j approximately 1
6i is an input method, one input is a register 40, and its output 16 becomes a register 40 input, and a VC and a digital integration circuit 15.
The output is The clock input in register 4 includes a scanning line pulse P that generates one pulse during the blanking period.
is given.

The other input of the digital Uohana circuit 13, that is, the input of the digital integration circuit 15, is connected to the address control line ll(
Address control signals 11-1, l l-2, in FIG.
・l 1-kK compatible. However, a digital signal from a digital signal generation circuit 20 controlled by k=1) is added. Is this digital signal its binary value or address? When the 1+lJI&41 signal 11 is at a high level (-23), the koji is controlled so that it becomes zero when it is at a low level.

Output 81, 82° of digital addition/subtraction circuit 12 8t
+l(n+[), then 1ltt is sufficient) is selected by the decoder circuit 22.7-1.7-
2.・7-n and 8-1.8-2.・、.

8-[-] is attacked. Assuming that the signal r of the decoding circuit 221 is combined with the serial number 1 to n+[')v, the signal with the fc number that matches the binary value of the output S of the digital adder circuit 12 is set to a high level (or This circuit is selected as low level). Decode circuit 22
may be the same decoding circuit used in digital memory.

The address control line 11 signal is ! @ Figure 6 shows running im pulse P
and change as shown. That is, after the blanking period ends, the stage R) is set to a low level when memory cells are successively written, and the stage is set to a high level during writing (W). With Kf in this manner, the output S of the digital odor enhancer circuit 12 is a cell whose number is [-] bluer when writing (W) as a binary number than when reading (the output has finished). It will be held in Next, when the reading/writing is photon and the blanking period VC occurs, the address control number 118 is set to a high level. At this time, the front pulse P is generated, the output 16 of the digital addition circuit is held in the register 4, and the power 16 of the digital integration circuit 15 is increased by (i). Therefore, the output P of the digital addition/subtraction circuit
will decrease by [a], and in the next run X=,
Cells corresponding to writing will be output one after another. Also,
Cell pot PP P Therefore, if -z=(i) and n is a multiple of [i]
The condition of the beach is to be able to work on pixels of time that are not bounded by the screen.
This can be easily achieved by making it slightly larger.]
Then, as shown in FIG.
The foot slam noise becomes checkered and difficult to see. In addition,
Even if the above conditions are not strictly met, the effect of making the noise less visible is effective even if the checkerboard shape is slightly slanted.

In addition, in Fig. 2, register 4 VC forced initial setup Shiba Shinryu is added, and at each frame start point of the image,
[Σ] Unsuccessful initial 1i! ? If it is added to Regis Month 4, the checkered fixed pattern noise shown in Figure 5 will alternate in brightness and darkness for each frame, making it even more difficult to see due to the eye's integral effect.

In this way, cells are selected by the number of cells r for each scanning line.
This method is used to eliminate the fixed slam noise that occurs when a group of memory cells is divided into a single number of cell groups by series-parallel-series conversion to equivalently improve the operating speed. It is also suitable for making it difficult.

FIG. 7 shows a memory for a scan line delay circuit that makes the fixed buzz noise caused by the above series-parallel series quality difficult to see by shifting the phase of the phase by 1Fr period for each scan. It is a diagram showing the configuration of an example.

The number of running:i signals added from the input dl is (q-k) (q: positive!! Therefore, k: II number smaller than q including 0)
Cell group 2-1.2-2 including the above memory cells and address circuits corresponding to the above memory cells.・2
-rK parallel) Ju can be seen (r: positive integer of 2 or more).

Cell groups 2-1.2-2゜...2-r respectively have write control signals 5-1.5-2, 5-r and successive control signals 6-1.6-2, 6-rl addresses. No. 16 7-
1.7-2.・7-rVcX divided by s1, group output signal 4-1.4-2°...4-rk switching circuit 2
Outputs 3. The switching circuit 23 outputs group output signals 4-1, 4-2. . . . 24-1 VctB is output to the cascade-connected clock delay circuits 24-1° . Clock delay circuit 24-1, 24-1 (t:habo(-H0k
) r value number) is driven by the %lll1 cumulative clock pulse b, and the output '+t clock (tl
i Purple) Delay and use as output signal C. Clock delay circuit 24-1. ...24-t, a sampling and holding circuit or the like can be used.

Address signals di, d2. . . . dm are digital registers 25-1, 25-2, . . . 25-m common address signal e'=iH address register clock pulse fl, f2 . ... It is held and given by fm. The common address signal e is given by the output of an address counter 26 that counts every cycle of address clock pulses gt (Q-k). Address clock pulse gij, pulse terror generated by multiplying the scanning pulse h periodic to the scanning frequency by 2 (2Q +1) times by the multiplier circuit 27, 6° write control 1 signal 5-1.5-2. -5-m,
d 1 signal on output side 6 6-1.6-2. -6-r, 7 dovsu v register clock pulses: x, iz, . . . 1rll each address clock pulse g to r phase, r equally spaced phases generated by lock pulse generation circuit 28, 29, 30 This is the pulse of The double thread long pulse bri is a clock pulse corresponding to the pixel of the input signal l, which is a pulse multiplied by r by the address clock pulse gtn times s31. Moreover, the switching control signal a is the pixel clock pulse bfr
This is generated by a switching counter 32 that counts r cycles.

The switching counter 32 is synchronized with the address clock pulse gv so that its operation is in a phase relationship with the address clock pulse g.

Next, referring to the time chart diagram of FIG. 8, scan Ivj of the seventh factor! I will explain the operation of Gmemory for Sagagawa Announcer.

FIG. 8 shows that in the period of the address clock pulse g,
What is the time relationship of the main part when ' is set to 4? It shows. During the period of the address clock pulse g, r number of pixel clock pulses b (four) occur. The common address signal e is
It is synchronized with the address clock pulse g, and depending on the address register clock pulses ix, iz, ta, in,
The address signal di, whose phase is delayed by 1/4 period,
d2. ct3. It becomes d4. Address register clock pulses il, iz, ta, i4 are respectively address signals d1. d2. d3. It is arranged to occur at a time point corresponding to the change point of d4.

The store control signal 5-1.mu. and the address signal dl2 are generated in the first half of the cycle, and the reading control signal 6-1 is generated in the second half. Other roses? The phase of the Irll8a signal and the successive control signal are sequentially delayed in accordance with the address signal. Like this VC cell group 2-1.2
-2.2-a, 2-4, the cell group output 4-1.4-2.4-3.4-4ti outputs the correct read signal at the last part of the period of the corresponding address signal. do. Therefore, as shown in FIG.
However, the address signals du, d2 . d3. If we rub V to select the output corresponding to the last part of each cycle of d4, we get
The operating speed of the cell group is the address clock pulse cycle, and the memory circuit structure can be constructed so that the cell group operates at the pixel clock pulse cycle, which is four times faster as a whole.

Next, when looking at FIG. 7 as a scanning line delay circuit, since the frequency of the address clock pulse g is an odd multiple of half the scanning frequency, the address signal dl.

d2. d3. ...The phase of dr is shifted by half a cycle between adjacent scanning stocks. Therefore, cell group 2
-1.2-2. ...Direct tfE between 2-rVJ, I
The static bang noise caused by the hN difference takes on a checkered pattern as shown in FIG. 5 and becomes difficult to see. Note that the clock delay circuits 24-1...24-t are for compensating for the fact that the delay of (7i+k)r pixels is insufficient for scanning by using only the cell group. It doesn't matter if you include it in NlO lyrics. Further, if k=0, the amount of fi of the clock delay circuit can be reduced, which is generally desirable.

In addition, in the configuration shown in Figure 7, the write control signal is sent to the chest space not as a scanning line delay circuit, but as a memory that is written in the first half of the scanning line and read out in the second half. The headset control signal is generated only in the second half, and the address counter 2 is generated in accordance with the delay time.
It is good if the count period of 6 is 1 short or broken. In this case, if the amount of delayed polishing does not need to be determined for each pixel, the clock delay circuit 24-1. ...24-t is a must-have. Roughly speaking, the multiplier of the multiplier circuit 27? In the case of q, since the address signals are aligned across the scanning line V,
may be controlled for each scan so that the prior for the common address signal e in every other scan line becomes the address signal ej (an integer close to J+i).

In addition, in the above explanation of the memory for the scanning line delay circuit, we have explained the case where the fixed bang noise is periodic, but even if it is not periodic, it can be fixed by randomly shifting the cell selection depending on the scanning line. Tan noise can be made less visible. In this case, the digital signal generator 20
It is only necessary to generate a binary number that changes randomly for each scanning line.

In addition, in applications other than scanning line delay circuits, when the fixed knock noise is not fixed to one screen - C, by changing the cell selection r temporal VC vibration, the easily visible noise slam and temporal It is also possible to make it difficult to see Gakakura.

So far, we have focused on image signals, but we can also use other signals such as audio signals to reduce interference by changing the correspondence between memory cells and address signals over time. can be changed to less noise.

As explained above, according to the present invention, it is possible to reduce noise interference caused by variations in memory cells, so that the degree of integration and cusp angle of analog memory can be increased by 1.
The application range of analog memory can be expanded.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an analog memory according to an embodiment of the present invention, Fig. 2 is a block diagram of an address circuit that can be used in @i cause analog memory, and Fig. 5g3 is an operational mode of the address circuit shown in Fig. 2 above. A diagram explaining ji! Fig. 44 shows an example of the noise pattern generated on the screen by a conventional analog memory, and Fig. 5 shows an example of the noise pattern generated on the screen by the analog memory of the present invention shown in Fig. 1 using the address circuit of Fig. 2. For example, FIG. 6 is a waveform diagram showing an example of the time change of the address control signal of the address circuit of the second cause, FIG. 7 is a configuration diagram of an analog memory according to another embodiment of the present invention, and FIG. 7 is a waveform diagram showing the operation of the analog memory of FIG. 6. FIG. l...Input signal line, 2...Basic memory cell group, 3
... Redundant memory cell group, 7-1 to 7-n... Basic cell selection signal, 8-1 to 8-m... Redundant cell selection signal, 9... Address circuit, 10-1-10 -1...address signal, 111...address control signal, 12...
・Digital addition/subtraction circuit, 13. Digital calo calculation circuit, 14... Register, 15... Digital integration circuit, 20... Digital signal generation circuit, 22... Decoding circuit, 23... Switching circuit, 24-1 to 24-l
···clock)! ! Extension circuit, 26... Address counter, 27° 31... Multiplier circuit, 28, 29.30.
...m-phase pulse child II￥] Fig. 3

Claims (1)

[Claims] 1, f, and [, and an address circuit for selectively writing and starting signals to the plurality of analog memory cells in all time series, wherein the address circuit writes the signals to the plurality of analog memory cells and An analog memory characterized in that the correspondence between time series and memory cells is configured such that memory cells are selected by changing temporally.