JPS58179826A - Driving method of liquid crystal display - Google Patents

Driving method of liquid crystal display

Info

Publication number
JPS58179826A
JPS58179826A JP6316182A JP6316182A JPS58179826A JP S58179826 A JPS58179826 A JP S58179826A JP 6316182 A JP6316182 A JP 6316182A JP 6316182 A JP6316182 A JP 6316182A JP S58179826 A JPS58179826 A JP S58179826A
Authority
JP
Japan
Prior art keywords
liquid crystal
signal
voltage
potential
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6316182A
Other languages
Japanese (ja)
Inventor
Shuji Maezawa
前沢 修爾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP6316182A priority Critical patent/JPS58179826A/en
Publication of JPS58179826A publication Critical patent/JPS58179826A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the variation in contrast, to increase the degree of multiplexing and to enable the display of medium contrast, by suppressing the fluctuation in the effective voltage of a liquid crystal layer. CONSTITUTION:A signal electrode signal SIGN has the same potential as the potential of a scanning electrode signal SCAN for the same time as a selection period before the selection period of each scanning electrode and the signal SIGN and a waveform V (Mn, N) of the voltage applied on picture elements are obtained with respect to the case (a) in which only the picture elements (M, N) turn on and all the picture elements on the same signal electrode are off, the case (b) in which only one picture element is alternately on and off, and the case (c) in which all the picture elements on the same electrode are on. Potentials LV1-LVN, LVC are formed by the resistance division having analog switches 111, 112 at both ends and the output of the switch 111 is the peak value VD of the driving voltage at ''0'' of 32Hz and the min. value GND at ''1''. The output of the switch 112 is reverse thereto. As a result, each potential is an alternating wave having 32Hz period and the fluctuation in the effective voltage of the liquid crystal layer is suppressed.

Description

【発明の詳細な説明】 本発明は非線型特性を有する素子を甲いた液晶表示装置
の駆動方法に関するものである。非線型孝子とけ、バリ
スタ素子、金属−絶縁体−金属(MlM)素子、ダイオ
ード素子、放電管素子などを指し、低電圧領域で高抵抗
、高電圧領域で低抵抗となる非線型特性を有するもので
ある◎第1図に電圧−電流特性の例を示したe 通常の液晶表示体に比べて、非線型素子を少なくとも一
方に有する液晶表示体は、マルチプレックス駆動をする
場合に多重度を極端に増やすことが可能である@第2図
は1画素すなわち1走査電極と1@号電極の交差する部
分、の叫価回路図である・液晶層の容1i(OLa)1
、抵抗(PLO)2、非線型素子の等佃1容量(C!M
L)3.等価抵抗(Rap ) 4  から構成される
・’BNL  が第1図に示される非線型特性を壱する
・第3図は多重度64(1/64デユーテイ比)、11
5バイアス法の電圧平均化法の駆動波形の例であるーた
だし、走査電極の選択の一順期間すなわち1フレーム周
期内では交流とならないで、2フレ一ム局期で交流とな
り、これを1走査周期とする。走査電極5および走査電
極信号を80ANと称17、その添文字はフレーム周期
内の走査電極の選択順序を示している・信号電極6およ
び信号電接信号をB工Gと称し、その添文字は位置によ
る区別を示すn第3図のS工GNは、画素(M、N)が
廃灯し、他の5IGN上の画素が非点灯の信号である・
y番目の走査電極信号EIOANMと同期しt走査期間
、すなわち80ANMの選択期間で、選択電位をとり、
他の走査電極の選択期間では非選択電位をとっている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a liquid crystal display device that uses an element having nonlinear characteristics. Refers to nonlinear elements, varistor elements, metal-insulator-metal (MlM) elements, diode elements, discharge tube elements, etc., which have nonlinear characteristics such as high resistance in the low voltage region and low resistance in the high voltage region. ◎ Figure 1 shows an example of the voltage-current characteristics.e Compared to ordinary liquid crystal displays, liquid crystal displays that have a nonlinear element on at least one side have extremely high multiplicity when performing multiplex drive. It is possible to increase the number to
, resistance (PLO) 2, nonlinear element isotsukuda 1 capacitance (C!M
L)3. Consists of equivalent resistance (Rap) 4 ・'BNL exhibits the nonlinear characteristics shown in Figure 1 ・Figure 3 shows multiplicity of 64 (1/64 duty ratio), 11
This is an example of a drive waveform for the voltage averaging method of the 5-bias method. Scan period. The scanning electrode 5 and the scanning electrode signal are called 80AN17, and the subscript indicates the selection order of the scanning electrode within the frame period.The signal electrode 6 and the signal electrical contact signal are called B, G, and the subscript is In the S-GN in Figure 3, which shows differentiation by position, the pixels (M, N) are out of light, and the pixels on the other 5 IGNs are non-lighting signals.
In synchronization with the y-th scanning electrode signal EIOANM, a selection potential is taken during a t scanning period, that is, a selection period of 80 ANM,
During the selection period of other scan electrodes, the non-selection potential is maintained.

この時、画素(M、N)に印加される電圧V(M、N)
け80ANM−8IGNで与えられる。
At this time, the voltage V (M, N) applied to the pixel (M, N)
80ANM-8IGN.

第4図の実線は、第3図に示すV(M、N)が第2図の
非線型素子と液晶画素に印加された場合の、非線型素子
の電圧波形V)II−と、液晶層の電圧波・形vTJo
  を示しているーまた、破線は非線抗電圧を印加し次
場合の、VNLとVl、Oを示している・V)11− 
が低抵抗領域にはいると・駆動電圧がほとんど液晶層に
印加され、液晶層が充電されるーこの時の時定数は第2
図の等価回路からPLO+FINL で与えられるaVLo  の変イヒけ、まずOLOとO
NLによる容量により分割された電圧となり、次にBt
、OとRNLにより分割された電圧に極限で近づく0非
線型素子の抵抗変化が0と無限大の間で生じるとして、
模式的に示したのが第51kl (a ) 。
The solid line in FIG. 4 shows the voltage waveform V)II- of the non-linear element and the liquid crystal layer when V(M, N) shown in FIG. 3 is applied to the non-linear element and the liquid crystal pixel in FIG. Voltage wave/shape vTJo
In addition, the broken line shows VNL, Vl, and O in the following case when non-linear coercive voltage is applied.V)11-
When enters the low resistance region, most of the driving voltage is applied to the liquid crystal layer, and the liquid crystal layer is charged.The time constant at this time is the second
From the equivalent circuit shown in the figure, the change in aVLo given by PLO+FINL, first, OLO and O
The voltage is divided by the capacitance due to NL, and then Bt
, assuming that the resistance change of the nonlinear element approaches the voltage divided by O and RNL between 0 and infinity,
The 51st kl (a) is schematically shown.

(b)である0非線型素子の抵抗が0ならば、(a)の
ように過渡的に電流1が流れ、OLOを充電する。電圧
はすべて液晶層にかかつている0次に非選択期間にはい
ると、Rba ((FHiLとなって過渡的に流れる電
流1のほとんどは、(b)のようにPLOを通して流れ
るようになるO近似的な時定数は τ−(OIIa+0aL)xRr、a で与えられる・一般に電界効果型の液晶表示装置に使用
されている液晶のFtLOけ太きく、τを走査周期程度
にとることは十分可能である。破線で示し几非選択の場
合ij、VNh  がピーク時でも低抵抗領域にけいら
ないので液晶層の充電が行なわれずVLOが低電圧のま
まである。−′t″々わち、選択と非選択のVLOの実
効値比は、M 41J+から理解されるように単なる電
圧平均化法より大きく、液晶表示のコントラストが実効
値に依存することを考慮すると、より高い多重度のマル
チプレックス駆動が実現されることに4る。
If the resistance of the 0 nonlinear element shown in (b) is 0, a current of 1 flows transiently as shown in (a), charging the OLO. When entering the zero-order non-selection period in which all voltages are applied to the liquid crystal layer, most of the current 1 that becomes FHiL and flows transiently flows through the PLO as shown in (b). The approximate time constant is given by τ-(OIIa+0aL)xRr,a. Generally, the FtLO of the liquid crystal used in field-effect liquid crystal display devices is thick, and it is quite possible to set τ to about the scanning period. In the case of non-selection as shown by the broken line, ij and VNh do not go into the low resistance region even when they are at their peak, so the liquid crystal layer is not charged and VLO remains at a low voltage. As understood from M41J+, the effective value ratio of the non-selected VLO is larger than the simple voltage averaging method, and considering that the contrast of the liquid crystal display depends on the effective value, multiplex driving with a higher multiplicity is required. I hope it will be realized.

本発明の目的は、非線型素子液晶表示装置のより完成度
の高いマルチプレックス駆動の方法を提供することであ
る6%に、信号波形の差をコントラストに影響させかい
方法と、制御しやすい中間調表示の方法を提供すること
である6 表示の大容量化が可能となる非線型素子液晶表示装置で
はあるが、従来の電圧平均fヒ法によるマルチプレック
ス駆動では、非選択期間の信号電極の信号により液晶層
に印加する実効電圧の変動が生じる。第6図(a)、(
b)、(c)、け同一信号線上で、(a)1画素ON、
他画素OFF。
The purpose of the present invention is to provide a more complete multiplex driving method for a non-linear element liquid crystal display device. 6. Although non-linear element liquid crystal display devices are capable of increasing the display capacity, in multiplex driving using the conventional voltage average fhi method, the signal electrodes during non-selection periods are The signal causes a fluctuation in the effective voltage applied to the liquid crystal layer. Figure 6(a), (
b), (c), on the same signal line, (a) 1 pixel ON,
Other pixels are OFF.

(b)交互にON、0IFF、((り全[ii%0N(
7”1冬場合の画素印加電圧V(M、N)を破線で、液
晶層に印加する電圧VLa  を実線で示したものであ
る。(a)、(b)、(c)の各場合のvr、。
(b) Alternately ON, 0IFF, ((RI[ii%0N(
The pixel applied voltage V (M, N) in the case of 7"1 winter is shown by the broken line, and the voltage VLa applied to the liquid crystal layer is shown by the solid line. vr.

の実効電圧をKa、Eb、Kcとすると明らかにKa)
Eb、>Ecとなっていることがわかる。これは、同一
信号電極上の他画素のON 、OFFの影響を受けるこ
とを意味している・よって従来の方法では、ONの実効
電圧の最小値を液晶の飽和電圧よりも大きく、OFFの
実効電圧の最大値を液晶のしきい値電圧より小さく取ら
なければならない・当然ながら、非線型素子の特性も厳
しく要求されることにかるし、fffl、中間的な実効
電圧で中間調を表示する場合には、他画素の影響をより
受けやすくなる・本発明けかかる欠点を解消するもので
、実効電圧の変動を抑制し、コントラストのばらつきを
防止し、多重度を増加させ、さらに中間vt4表示を可
能とするものであるの次に実施例に従い、本発明のうち
の実効電圧の変動の抑制について述べる一第7図は本発
明の駆動波形の例である〜前述の電圧平均化法の例と同
じ(1/64デユーテイ、115バイアス波である・通
常の電圧平均化法と異なり、各走査1肇の選択時間の前
または後に、走査電極と信号電極に印加する電位を同値
とする時間を設定しである一実施例では各走査電極の選
択時間の前に、選択時間と同じ時間分を同値時間として
設定しであるC第7図のSOANMはM番目の走査電極
信号であり、通常のものに比べて相対的に走査電極の選
択時間が半減し、見かけ上17128デユーティの走査
電極信号の1つおきと等しい−8IGNとして代表され
る信号電極信号は、各走査電極の選択期間の前に、選択
期間と同一時間分は走査電極信号と同一電位となってい
るー結果として、画素(M、N)だけがONで同信号電
極上の他の画!が全てOFFの場合(a)、−画素毎に
交互にON。
Letting the effective voltages of Ka, Eb, and Kc be clearly Ka)
It can be seen that Eb>Ec. This means that it is affected by the ON and OFF states of other pixels on the same signal electrode. Therefore, in the conventional method, the minimum value of the ON effective voltage is set larger than the saturation voltage of the liquid crystal, and the OFF effective voltage is The maximum value of the voltage must be smaller than the threshold voltage of the liquid crystal.Of course, the characteristics of the nonlinear element are also strictly required, and when displaying halftones with an intermediate effective voltage, is more susceptible to the influence of other pixels.This invention solves the drawbacks of this invention.It suppresses fluctuations in effective voltage, prevents variations in contrast, increases multiplicity, and enables intermediate VT4 display. Next, according to an embodiment, suppression of fluctuations in effective voltage according to the present invention will be described. Figure 7 is an example of the drive waveform of the present invention - the same as the example of the voltage averaging method described above. (1/64 duty, 115 bias wave) - Unlike the normal voltage averaging method, a time is set before or after the selection time of each scan to make the potential applied to the scan electrode and the signal electrode the same value. In one embodiment, before the selection time of each scan electrode, the same time as the selection time is set as the equivalent time. Compared to this, the selection time of the scan electrodes is relatively halved, and the signal electrode signal represented by -8IGN, which is apparently equal to every other scan electrode signal with a duty of 17128, is selected before the selection period of each scan electrode. For the same time as the period, the potential is the same as that of the scanning electrode signal - As a result, if only the pixels (M, N) are ON and all other pixels on the same signal electrode are OFF (a), - for each pixel Turn on alternately.

OFFの場合(b)、同信号電極上の全ての画素がON
の場合(c)について、第7図のように、信号電極信号
S工GNと画素印加電圧波形V(M、N)が得られる・ 第8図は破線で示すV(M、N)が印加され几時の液晶
層に印加する電圧波形を実線で、第7図と同じ順に、示
している・ここで第6図に示した通常の電圧平均fP法
の場合と比較してみると、第8図のVLOの波形は、微
少変動を無視すれば、相互に等しい放電波形を描いてい
ることがわかるーこうして、本発明により液晶層の実効
電圧の変動が抑制されるのである。すなわち、VLOの
ON波形間、OFF波形間の実効値の差がほとんどなく
なり、多重度が増加できるn!!施例でけ64多31[
のマルチプレックス駆動であっても、実質的に128多
重度のマルチプレックス駆動に似てくるが、非線型素子
液晶表示装置の場合は、走査電極選択期間内に十分な値
せで液晶層の容量cLaが充電される時間であれば問題
はない・従来の電圧平均化法による中間調表示は次の様
に行なうのが一般的であった一信号電極信号の各l1i
FII素に対応する走査電極選択期間を細分し、選択期
間内のデユーティ比を変化させる6gA1えば16階調
の中間調を表示しようとすれば16通りのデユーティ比
の変化を生じさせる0他の走査電極のデユーティ比は、
1フレ一ム周期内の実効値の変イヒになら永いので、各
画素では階調に応じた実効値の電圧が印加されるOとこ
ろが、各走査電極の選択期間毎に選択電位と非選択電位
の中間電位をもって中間調を表示しようとすると、他の
走査電極の中間値の選択が、1フレ一ム周期内の実効値
の変化と力って、各画素の独立が階調の選択が不訃と表
る。非線型素子液晶表示装置においては上述の状況が全
く異たる− 次に本発明のうちの中間調の制御について述べる0第9
図は本発明の中間調を表示する駆動波形の例であるOこ
れも1164デユーテイ、i15バイアス法の前述の駆
動方法を基本としている2′l;、信号電極信号は、各
走査電極選択期間に選択電位と非選法電位の中間電位を
設定する一一で18階調を設定し、6種の中間電位があ
り、第1階−を完全OFFとし、第8階−を完全ONと
する・第1から第8までの階調の繰返しで画素(M、N
)は第61Sli調の場合(a)、第2と第5の階調の
繰返しで、(M@ N )は第2階調の場合(b)、全
ての画素が第4階調の場合(c)について、第9図の信
号電極信号S工GNと画素印加電圧波形■(M、N)を
得る。
In the case of OFF (b), all pixels on the same signal electrode are ON
In case (c), as shown in Fig. 7, the signal electrode signal S/GN and the pixel applied voltage waveform V (M, N) are obtained. In Fig. 8, V (M, N) shown by the broken line is applied. The voltage waveforms applied to the liquid crystal layer during the cold state are shown as solid lines in the same order as in Figure 7.Comparing this with the case of the normal voltage average fP method shown in Figure 6, It can be seen that the VLO waveforms in Figure 8 depict mutually equal discharge waveforms, if minute fluctuations are ignored - thus, the present invention suppresses fluctuations in the effective voltage of the liquid crystal layer. In other words, there is almost no difference in effective value between the VLO ON waveform and OFF waveform, and the multiplicity can be increased n! ! There are 64 examples and 31 [
Multiplex driving with a multiplicity of 128 is substantially similar to multiplex driving with a multiplicity of 128, but in the case of a non-linear element liquid crystal display device, the capacitance of the liquid crystal layer can be increased by setting a sufficient value within the scanning electrode selection period. There is no problem as long as it is the time when cLa is charged. - Halftone display using the conventional voltage averaging method is generally performed as follows.Each l1i of one signal electrode signal
6gA1 subdivides the scan electrode selection period corresponding to the FII element and changes the duty ratio within the selection period.For example, if you want to display 16 gray levels, the duty ratio will change in 16 ways.Other scans The duty ratio of the electrode is
Since it takes a long time for the effective value to change within one frame period, a voltage with an effective value corresponding to the gradation is applied to each pixel. However, the selection potential and non-selection potential are If you try to display a halftone with the middle potential of the other scanning electrodes, the selection of the middle value of the other scanning electrodes will affect the change in the effective value within one frame period, and the independence of each pixel will cause the selection of the halftone to be impossible. Expressed as deceased. In non-linear element liquid crystal display devices, the above-mentioned situation is completely different. Next, we will discuss halftone control in the present invention.
The figure shows an example of a driving waveform for displaying halftones according to the present invention. This is also based on the aforementioned driving method of the 1164 duty, i15 bias method. The signal electrode signal is applied to each scanning electrode selection period. Setting the intermediate potential between the selection potential and the non-selection potential, 18 gradations are set in 11, and there are 6 intermediate potentials, the 1st floor is completely OFF and the 8th floor is completely ON. Pixel (M, N
) is the 61st Sli tone (a), the second and fifth tone are repeated, (M@N) is the second tone (b), and all pixels are the fourth tone ( Regarding c), the signal electrode signal S/GN and the pixel applied voltage waveform (M, N) shown in FIG. 9 are obtained.

第10図は破線で示すV(M、N)が印加された時の液
晶層に印加する電圧波形を実線で、第9図と同じ順に示
しているO実線のvbo  の波形は、微少変動を無視
すれば、階調に応じた放電波形を描いていることがわか
るo V (M 、 N )で現われ交信画素の影響に
よる波形の変化は、すべて非線型素子の高抵抗領域であ
る几め、VLOには影響しなくなる・ 通常の電圧平均化法で用いられたデユーティ比の変化に
よる中間調表示の方法は、非線型素子では不適当となる
。それは、走査電極選択期間の長短は、一定の時定数内
であれば、液晶層の(3LOの充電にはあまり影響を及
はさなく力るから制御しにくくなるのである0もちろん
極痛に短時間の選択期間を設定していけば不可部ではな
いが、その場合には時定数の微少のばらつきが大きく影
響するので好ましくない。
Figure 10 shows the voltage waveform applied to the liquid crystal layer when V (M, N) is applied, which is shown as a broken line, and the solid line shows the waveform of the voltage applied to the liquid crystal layer when V (M, N) is applied. If ignored, it can be seen that the discharge waveform is drawn according to the gradation. The changes in the waveform that appear at o V (M, N) and due to the influence of the communicating pixels are all due to the high resistance region of the nonlinear element, VLO is no longer affected. - The method of displaying halftones by changing the duty ratio, which is used in the normal voltage averaging method, is inappropriate for non-linear elements. The reason is that the length of the scanning electrode selection period does not have much effect on the charging of the liquid crystal layer (3LO) within a certain time constant, but it becomes difficult to control because it forces the charging of the liquid crystal layer (3LO). Although it is not impossible to set the time selection period, it is not preferable in that case because minute variations in the time constant have a large influence.

次に本発明の実施例の駆動波形の形成の回1liKW!
1成について述べる□市販されているMOEI・工9等
を利用して最も簡単に構成しt−例であり、これ以外の
構成ももちろん可能である・第11ツ・。
Next, the process of forming the drive waveform according to the embodiment of the present invention 1liKW!
□ This is the simplest example of the configuration using commercially available MOEI/Engine 9, etc., and other configurations are of course possible.

第12図、第15図に分けて説明するが、信号名の何々
Fitzという信号は、数値で示す周波数をもつ九基本
矩形波であり、すべて立下りのタイミング一致している
ものとする・さて、第11図は駆動円・の電源回路であ
り、両端にアナログスイッチ111.112を有する抵
抗分割により電位、LVI 、LVs 、・”−、LV
s 、LvN 、LV(3を形成する。アナログスイッ
チケ市販のPcA・CD4053などを使用すればよい
・アナログスイッチ111の出力は、32Hz9″O1
1で駆動電圧のピーク値VDとなり、“1′で最低値G
NDと々る一アナログスイッチ112の出力はその逆で
ある・この結果、各電位は32Hzの周期をもつ交流的
な亀のに々る・LVOは走査電極信号の選択電位であり
、LVMけ非選択電位である一LV、け信号電接の完全
選択電位であり、LV・は完全非選択電位であシ、LV
、〜L V vけ中間胴選択電位である0図の抵抗値の
例は、115バイアスを前提とし2、中間調電位間を等
間隔とし次ものであって、他の値であってもよい。場合
によっては中間調電位を千尋間隔とすることもありうる
The explanation will be divided into Figs. 12 and 15, but it is assumed that the signal named So-and-so Fitz is a nine fundamental rectangular wave with a frequency indicated by a numerical value, and all of them have the same falling timing. , Fig. 11 is a power supply circuit for a drive circle, in which the potentials LVI, LVs, .''-, LV are determined by resistor division with analog switches 111 and 112 at both ends.
s, LvN, LV (forms 3.Analog switch - Commercially available PcA/CD4053 etc. can be used. -The output of the analog switch 111 is 32Hz9''O1
1 is the peak value of the drive voltage VD, and 1' is the lowest value G.
The output of the ND toru one analog switch 112 is the opposite. As a result, each potential is an alternating current turtle with a period of 32 Hz. LVO is the selection potential of the scanning electrode signal, and the LVM LV is the selection potential, and LV is the complete selection potential of the signal connection, and LV is the complete non-selection potential.
, ~L V v is the intermediate torso selection potential, and the example of the resistance value in Figure 0 assumes a 115 bias, 2, and equal intervals between the intermediate tone potentials, and other values are also possible. . In some cases, the halftone potentials may be set at staggered intervals.

第12図は走査電極信号S CA N s 〜80 A
 Nasの形成回路であり、6ビツト対64ビツトのデ
コーダー121とアナログスイッチ122がら構成され
るaデコ−’+1’−121ij市販のCD4514を
5個とインバータ回部で作成でき、アナログスイッチ1
22け市販のCD4055を22個で作成できる。デコ
ーダーの入力信号は下位ビットから2048Hz、10
24Hz、512Hz。
FIG. 12 shows the scanning electrode signal S CA N s ~80 A
A deco-'+1'-121ij is a circuit for forming the Nas, and is composed of a 6-bit to 64-bit decoder 121 and an analog switch 122.It can be created using five commercially available CD4514s and an inverter circuit, and the analog switch 1
22 commercially available CD4055s can be created with 22 pieces. The input signal of the decoder is 2048Hz, 10
24Hz, 512Hz.

256Hz、128Hz、64Hzであり、インヒビッ
ト入力は4094Hzである・この結果、出力Ss〜5
saKけ約m12e巾のパルスが同一時刻の間隙をもっ
て順に64Hzの周期で出てくる・これらの出力はアナ
ログスイッチ122のコントロール信号01〜Oa4と
して入力され・アナログ入力LVMとLVOを選択[て
、アナログ出力01〜0−4に出力されるーこれらが走
査W衡信丹S CAN、〜8 C! A N @4とな
る。
256Hz, 128Hz, 64Hz, and the inhibit input is 4094Hz - As a result, the output Ss ~ 5
Pulses of saK width m12e are output in sequence with a period of 64 Hz with the same time interval. These outputs are input as control signals 01 to Oa4 of the analog switch 122. Analog inputs LVM and LVO are selected [and the analog Outputs 01 to 0-4 - These are the scan W CAN, ~8 C! A N @4.

第13図は信号電極信号8IG1〜8IG64の形成回
路であるー走査電極数と信号電棒数は同じであるが、説
明上回じにしであるので、信号電5et−t4つと増や
してよい◎アラログスイッチ131、デーダ出力回1@
132、ラッチ用クロック回路135.64個のラッチ
回路154.64個のマルチプレクサ−135から!l
i成される・アナログスイッチ131け市販の4053
を3個で作成でき、アナログ人力L V l−L ’i
 mと、アナログ人力LVMとf4096Tlzで切換
え、走査電極信号と同電位時間を吃つ電源8mk出力す
る・データ出力口−152は特定していない・これは画
像情報をメモリーするROM回酪回路はRAM回路で本
よいし、テレビのビデオ信号をデジタル化して出力する
回路でもよい自クロック回路135はデータ出力口Wの
出力内容に同期して、ラッチ回路164でランチするク
ロック信号を形成する本のであり、データ出力回路16
2の種類に応じて構成される・ラッチ回i’!’ 15
4ii市Q)a D 4042で作成できるものであり
、信号電極に3ビツト出力が1個ずつ対応している・走
査電極の選択時間に応じて内容を変え出力する。マルチ
プレクサ−155は市販のCD4051で作11J丈で
き、8種のアナログ入力をコントロール信号C1。
Figure 13 shows the circuit for forming the signal electrode signals 8IG1 to 8IG64 - The number of scanning electrodes and the number of signal electrodes are the same, but since the explanation is at the beginning, you can increase the number of signal electrodes 5et-t to 4 ◎Aralog switch 131, data output time 1 @
132, latch clock circuit 135.64 latch circuits 154.64 multiplexers from 135! l
131 commercially available analog switches 4053
can be created with three pieces, and analog human power L V l-L 'i
m, analog human power LVM, and f4096Tlz to output a power supply of 8mk with the same potential time as the scanning electrode signal.・Data output port-152 is not specified.・This is a ROM that stores image information.The recirculating circuit is a RAM. The self-clock circuit 135 may be a circuit or a circuit that digitizes and outputs a television video signal.The self-clock circuit 135 is a circuit that forms a clock signal that is launched in the latch circuit 164 in synchronization with the output content of the data output port W. , data output circuit 16
2. Latch times i'! '15
4ii City Q) a D It can be created with 4042, and one 3-bit output corresponds to each signal electrode.The content changes and outputs according to the selection time of the scanning electrode. The multiplexer 155 can be made with a commercially available CD4051 and has a length of 11J, and connects 8 types of analog inputs to the control signal C1.

a、、C,に従って1種選択し、て出力するアナログス
イッチである。この結果として各出力はBNG’i 〜
5IG64となル・ 以上述べた回路構成で、安定した中間調表示の非線型素
子液晶表示装泗の駆動が実現できる。もちろん一実施例
の回v−*成であるので、他にも構成できることけいう
までも々い― 本発明によれば、コントラストを充分制御できる非線型
素子液晶表示装齢を構成できるので、テレビ画像の表示
が可能となり、小型薄型テレビ受像機やVTI′1モニ
ターテレビかどの応甲にすぐれたものが実現できること
になる1−/
This is an analog switch that selects and outputs one type according to a, , and c. As a result, each output becomes BNG'i ~
5IG64 With the circuit configuration described above, it is possible to drive a non-linear element liquid crystal display device with stable halftone display. Of course, this is just one example configuration, and it goes without saying that other configurations are also possible.According to the present invention, a non-linear element liquid crystal display device that can sufficiently control the contrast can be configured, so that television images can be 1-/

【図面の簡単な説明】[Brief explanation of drawings]

第1図は典型的な非線型素子のV−1特性である・ 第2図は非線型素子液晶表示装置の醇価回路である。 第3図は従来の電圧平均化法による液晶表示装置の駆動
波形である− 第4rgJは非線型素子液晶表示装置の動作波形を示す
。 第5図は非線型素子液晶表示装置の動作概念を模式的に
示したものであるー(1)は非線型素子がOWした場合
、(b)けOFFした場合・第6図は非線型素子液晶表
示装置の画素印加電圧波形を破線で、液晶層印加波形を
実線で示したものである。 第7図は本発明による駆動波形を示す一第8図は第7図
の波形を適用り文場合の液晶層に印加される電圧波形を
示すものであるの第9図は本発明による中間p1表示の
駆動波形を示す・ 第10図は第9図の波形を適用し几場合の液晶層に印加
される電圧波形を示すものであるO第11図1.第12
図、第13図は実施−の駆動波形の形成の回路構成につ
いて示す0 112.113〜アナログスイツチ 121〜デコーダー 122〜アナログスイツチ 131〜アナログスイツチ 152〜デ一タ出力回路 133〜ランチ用クロック回路 154〜ランチ 135〜マルチプレクサ− 以上 出願人 株式会社 隷訪鞘工舎 代理人 弁理士 最 上  務 柩2回 第4−同 ((L3                     
          (bン発5図 臓8冒 (aJr−’ 、:。 (Ib>     ’−一“ 一一−七 (c >     r−’ (α)「−B Lj 〔b> 「−: 一一一! (C) 「−: 第120
Fig. 1 shows the V-1 characteristic of a typical non-linear element. Fig. 2 shows the valence circuit of a non-linear element liquid crystal display device. FIG. 3 shows driving waveforms of a liquid crystal display device using the conventional voltage averaging method.4 rgJ shows operating waveforms of a non-linear element liquid crystal display device. Figure 5 schematically shows the operating concept of a non-linear element liquid crystal display device - (1) when the non-linear element is turned on, (b) when it is turned off - Figure 6 shows the case when the non-linear element is turned off. The pixel applied voltage waveform of the liquid crystal display device is shown by a broken line, and the liquid crystal layer applied waveform is shown by a solid line. FIG. 7 shows the driving waveform according to the present invention. FIG. 8 shows the voltage waveform applied to the liquid crystal layer when the waveform in FIG. 7 is applied. FIG. 9 shows the voltage waveform applied to the liquid crystal layer when the waveform in FIG. 10 shows the voltage waveform applied to the liquid crystal layer when the waveform of FIG. 9 is applied. 12th
FIG. 13 shows the circuit configuration for forming the drive waveform in the implementation. ~Lunch 135~Multiplexer- Applicant: Reiwa Sayakosha Co., Ltd. Patent attorney: Muhitsu Mogami 2nd No. 4-(L3
(Ib>'-1" 11-7 (c >r-' (α) "-B Lj [b>"-: 111! (C) “-: 120th

Claims (1)

【特許請求の範囲】[Claims] 1、 液晶表示体を構成する少なくも一方の基勝に非線
型特性を有する素子を膜製しt液晶表示装置のマルチプ
レックス駆動において、各信号1葎の信号は、通常の電
圧平均化法による選択電位と非選択電位の中間電位に、
各走査電極の選択時間について電位を設定し、て中間調
表示を行なうことを特徴とする液晶表示装置の駆動方法
・2、 液晶表示体を*vLする少なくとも一方の基板
に非線型特性を有する素子を設W L、た液晶表示装置
のマルチプレックス駆動において、各走査電シの選択時
間の前または後に、走査電極と信号電極に印加する電位
を同値とする時間を設定したことを特徴とする液晶表示
装置の駆動方法・
1. In the multiplex drive of a liquid crystal display device, each signal is processed by a normal voltage averaging method. At the intermediate potential between the selection potential and the non-selection potential,
A method for driving a liquid crystal display device characterized by setting a potential for a selected time of each scanning electrode and performing halftone display. 2. An element having nonlinear characteristics on at least one substrate that causes *vL of a liquid crystal display body. In a multiplex drive of a liquid crystal display device, a time is set before or after the selection time of each scanning electrode to make the potential applied to the scanning electrode and the signal electrode the same value. Display device driving method/
JP6316182A 1982-04-15 1982-04-15 Driving method of liquid crystal display Pending JPS58179826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6316182A JPS58179826A (en) 1982-04-15 1982-04-15 Driving method of liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6316182A JPS58179826A (en) 1982-04-15 1982-04-15 Driving method of liquid crystal display

Publications (1)

Publication Number Publication Date
JPS58179826A true JPS58179826A (en) 1983-10-21

Family

ID=13221233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6316182A Pending JPS58179826A (en) 1982-04-15 1982-04-15 Driving method of liquid crystal display

Country Status (1)

Country Link
JP (1) JPS58179826A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304229A (en) * 1987-06-04 1988-12-12 Seiko Epson Corp Driving circuit for liquid crystal panel
JPH05333364A (en) * 1992-05-27 1993-12-17 Hamamatsu Photonics Kk Spatial light modulation device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63304229A (en) * 1987-06-04 1988-12-12 Seiko Epson Corp Driving circuit for liquid crystal panel
JPH05333364A (en) * 1992-05-27 1993-12-17 Hamamatsu Photonics Kk Spatial light modulation device

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