JPS5817584A - Address setting system - Google Patents
Address setting systemInfo
- Publication number
- JPS5817584A JPS5817584A JP11535781A JP11535781A JPS5817584A JP S5817584 A JPS5817584 A JP S5817584A JP 11535781 A JP11535781 A JP 11535781A JP 11535781 A JP11535781 A JP 11535781A JP S5817584 A JPS5817584 A JP S5817584A
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- address signal
- board
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Abstract
Description
【発明の詳細な説明】
本発明はメモリボードのアドレス設定方式に関す為もの
ｅ６る。更に詳しく言えに、各メ毫リポートの物理的挿
入位置ととに、予め物理的にアドレスが決定されて−る
メ篭９メートＯアドレス殴ｙ７Ｒ７１弐に係る一〇であ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address setting method for a memory board. More specifically, the address is physically determined in advance at the physical insertion position of each mail report.
従来、物理的挿入位置に対して、各メ４９が一ドの７ド
レスを設定する方式では、７４ｇボードの挿入位置に対
し、メ４９ボードＯメ４９容量をを基にアドレスが連続
すゐ様にパックぽ一ドｏＩＩａ続を周定的に定めである
。従って技術的に条ノ毫すポートＩｌｋｌＪｅ１ｍ積度
（記憶容量）を増加させる事が可能と謙っても、パック
ｌ−ドを改造しｔｋ−＠）、会メ４ｇＭ−ドＯメ４９容
量を増設する事が不１１ｆ鐘で６）、＄／ステムＯメ篭
ψ春量を増膜する事が不可能である。す凌わち、従来設
置１ｍているシステムＯメ４９容量をメモリダートのみ
権）換える事によ為メモり容量の増設が不可能である。Conventionally, in the method of setting 7 addresses of one card for each 74g board in relation to the physical insertion position, the addresses would be consecutive based on the capacity of the 74g board O 49 board. The continuation of the pack is periodically determined. Therefore, even if it is technically possible to increase the capacity (storage capacity) of the port IlklJe1m, by modifying the pack l-do, the capacity of the port IlklJe1m can be increased. 6) It is impossible to increase the amount of spring on the 11th floor bell. In other words, it is impossible to increase the memory capacity by replacing the 49 capacity of the conventionally installed system Ome 49 with memory dart.
本ｌｉ＠は従来ｏａｔｓが上述の加電不利益を有するζ
七に一挙提案される％０であって、本発−Ｏ主＊＊■約
はメ４１！Ｉ量Ｏ変更が中途で発生し良鳩舎でも、Ａツ
タポードを変更すること象（、連続アドレスＯ榔虞をと
）うみアドレス設定方式を纏塞す為ＪｊｆＫあ為。This li @ is ζ where conventional oats have the above-mentioned disadvantage
It is %0 that is proposed all at once in seven days, and the main issue is 41! Even if the I quantity O change occurs midway and the pigeon house is in good condition, it is possible to change the A ivy port (there is a risk of continuous address O).
以下、本発′＠Ｏ夷麹飼を添付ｇｉｉｉｉに従って詳細
に詭−す為。The following is a detailed explanation of the original ``@Oi Kojikai'' according to attached iii.
第１■はメ峰曹装置全体の構成間で６３１．メモＷｌ−
ＦＯｒ＃１ＩＩｆＩ！３を位置によ）アドレスを決定す
る禽め０％・で番為。番メ４９ボード脆、域、Ｍ冨＝
Ｍｍは、そ０４１ＩｌｌｌｌＩＩ１３１に位置で決鷹る
先願アドレスＯＩｌ定ＩＩ報をパックが−ドｌから供艙
畜れる。叙全て等しく、各メモリ容量が飼えば１６にバ
イトとすれば、各メモりボード”ａ 、Ｍｔ −Ｍａｌ
を連続アドレス構成とするえめにはメ４１１−ド鳩０先
願アドレスは・番地、メモ９Ｉ−ド＆ ０それａｌＬＯ
・・番地、ｊ’ ” ＊ ｄｌ’−）”ＭｌＯそれは３
３０００１地とな）、壺メ篭Ｗ＆−ド０先頭アドレスは
メ４すｌ−ドＯメ４曹容量分ずつ段階的に増加して−（
ことＫｔｋる。The first part is 631. Memo Wl-
FOR#1IIfI! 3 according to the position) Determine the address by using 0%. Number 49 board fragile, area, M wealth =
Mm receives the prior application address OIl determination II information determined at the location 041IllllII131 from the pack. If the memory capacity of each memory board is equal to 16 bytes, then each memory board "a", Mt-Mal
To make it a continuous address structure, the memo 411-doto 0 first application address is address, memo 9I-do & 0 it alLO
...address, j' ” * dl'-)”MlO that is 3
30001 area), the first address of the urn mego W&-do 0 is increased step by step by the amount of the 4th capacity.
That's Ktkru.
継雪■は、第１１１１２）会メ４豐ポードに対するアド
レス入力の構成を示すブーツタ図である。ナ傘わち、各
メモリポード０バックボードによ）ＩＩ定畜れえ入力（
アドレス）は、番号ｓＫよる入力てｈ）、令メ４１０挿
入位置ととに与えられて％ｆｈＪｂ０書＊ｙ＆ｉ、壺メ
毫リヘ＾過に与えられるメ４菅アクセスＯえめ０アドレ
ス信号でｈ為。Tsuyuki (2) is a boot star diagram showing the structure of address input for the 11112) meeting port. (In other words, each memory port 0 backboard) II fixed input (
The address) is input by the number sK, and the address signal is given to the insertion position and the address signal is given to the 410 insertion position, and the address signal is given to the address signal. .
嬉３１１ｍ１は、＃−ｙ選択選択用アドレス信号一度ア
ドレス麦換装置９に入力し、変換ＩＩＯアドレス償４／
＃１・をＩＩ為ブｐツタ図であ為、アドレス変換装置・
嬬、メ４豐装置全体Ｏ柳威によって決まる変換ＩＩＯア
ドレス償１３１）を出力する丸めＯもＯで、飼工ば壷メ
４マポードＯメ篭り容量を１１１［パイ）０場食に紘羨
換ＩＩＯアドレス償−Ｊ１１・はボード遥択層アドレス
信−ＩＩと同じ内容とし、メモリ容量がＳ怠ＫＡ４ｋＫ
）鳩舎には（メ４蓼容量の拡大のえめにはアドレス線に
ｈま）があることが条件でｈｈ）、変換後のアドレス信
号１０はボーＦｊｌ択層アドレス儒漫を３倍し大内容と
１為、こＯ炭換ＩＩＯアドレス償４１１＠とアドレス信
号７′を比較−踏部にて比軟を行−一致信号８を得、バ
ックが−ド１０ポーｒ遥択信号を形成する。６４にパイ
、トにメモ９審量を拡大する鳩舎は、ぽ−ド遥択用アド
レス信号５を４倍し大内容とすればよい。The 311m1 inputs the #-y selection address signal once to the address conversion device 9, and converts the IIO address conversion 4/
Since #1 is II, the address translation device is
嬬、Me4谐The whole device O Liu Wei determines the conversion IIO address compensation 131) is output rounding O is also O, and if the feeder is used, the capacity of the 4 mapo Ome is converted to 111[pi] 0 place food. The IIO address signal J11 has the same content as the board selection layer address signal II, and the memory capacity is S KA4kK.
) The pigeonhole must have (h) on the address line in order to expand the capacity (hh), and the address signal 10 after conversion is tripled by the address line of the address signal 10 and has a large content. 1, therefore, the address signal 7' is compared with the IIO address compensation 411@ and the pedal performs a ratio soft operation to obtain the match signal 8, and the back side forms the -do 10 pole selection signal. For a pigeonhole that expands the size of pie and memo 9 to 64, it is sufficient to multiply the address signal 5 for port selection by 4 to make it larger.
本発明社以上Ｏように構成されかつ動作する大めメモ９
Ｉ−ドＯメ篭り容量を途中で変更する必要が生じえとき
、装置全体Ｏ構成を大−に変更することなく対−できる
ばかヤでなく、メ４１１−ドに上詠し九構成と機能をも
えせるだけでメモ９Ｉ−ドを大容量０％ＯＫ変換するこ
とがで１為。A large memo 9 constructed and operated as described above by the present inventor
When it becomes necessary to change the capacity of the I-DO and O-memories midway through, it is possible to do so without making major changes to the entire O-configuration of the device; 1. You can convert Memo 9I-Card with large capacity 0% OK just by burning it.
従って本＊＋ｉ＋ｉａ将来Ｏ事態に対処で暑る極めて柔
軟なアドレス設定方式を提供できるものである。Therefore, it is possible to provide an extremely flexible address setting method that can be used to deal with future situations.
１１１ｇはメ４９装置全体Ｏ構成園、
嬉意図は第Ａｍ１）各メモ９Ｉ−ドに対するアドレス人
力Ｏ構威を示すプロッタ図
第３１１は本発明の一実施例を示すボード選択■路ｏｙ
ｍツク図である。
ここで、５−ｙ−ド遺択用アドレス信号、７′、−アド
レス信号、１０−（変換後の）アドレス信号である。
特許出願人 中ヤノ／株式余社111g is a plotter diagram showing the overall configuration of the memo 49 device, and the plotter diagram showing the address manual configuration for each memo 9I board.
This is a mtsuku diagram. Here, 5-y-address signal for selection, 7'-address signal, and 10-(converted) address signal. Patent applicant Nakayano/Yosha Co., Ltd.
Claims (1)
択層アドレス信号を襞換するえめＯアドレス変換装置を
備え、皺アドレス変換装置で変換しえアドレスとメ４Ｗ
アドレスとを比較して特定Ｏメ４９が一ドを遥択するこ
とを＊＊とするアドレス設定方式。Although the physical location of the memory port is fixed, it is equipped with an O address translation device that folds the -R selection layer address signal, and converts the address and the 4W address with the wrinkle address translation device.
An address setting method in which ** indicates that the specific address 49 selects one address by comparison with the address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11535781A JPS5817584A (en) | 1981-07-24 | 1981-07-24 | Address setting system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11535781A JPS5817584A (en) | 1981-07-24 | 1981-07-24 | Address setting system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5817584A true JPS5817584A (en) | 1983-02-01 |
Family
ID=14660521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11535781A Pending JPS5817584A (en) | 1981-07-24 | 1981-07-24 | Address setting system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5817584A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62114053A (en) * | 1985-11-13 | 1987-05-25 | Yokogawa Electric Corp | Information processor |
| JPS63168895A (en) * | 1987-01-06 | 1988-07-12 | Mitsubishi Electric Corp | Memory element module |
-
1981
- 1981-07-24 JP JP11535781A patent/JPS5817584A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62114053A (en) * | 1985-11-13 | 1987-05-25 | Yokogawa Electric Corp | Information processor |
| JPS63168895A (en) * | 1987-01-06 | 1988-07-12 | Mitsubishi Electric Corp | Memory element module |
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