JPS58175115A - Signal detecting circuit - Google Patents

Abstract

PURPOSE:To shape a waveform accurately, by comparing the width of a compared pulse with a prescribed width and controlling the reference voltage of a comparator so that the difference between them is always zero. CONSTITUTION:Latch data of a latch circuit 5 is subjected to D/A conversion to obtain a DC output. This output is given to a comparator 7 and is compared with a reference voltage E2 set to a voltage corresponding to a prescribed phase, and the error output is obtained. If the pulse width of a reproduced waveform is wider than a prescribed width, a positive voltage is added to the voltage of a reference voltage source E1, and therefore, the voltage of a comparator 1 rises, and the pulse width on the plus side of the output of the comparator 1 becomes wider. Since this operation is always performed, the output pulse has a correct duty. Even if there are asymmetrical components in the level of the input reproduced signal, an optimum pulse shaping is always performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data signal detection circuit for a digital disk or the like. When playing digital discs, pulse code modulation (CPCM) cheap recorders, etc. that record and reproduce signals by pulse-coding the signals recorded on discs and tape recorders, the signals reproduced have high-frequency components due to the influence of the frequency of the disc or recording medium. The waveform becomes a lost sine wave, but in order to read such waveform data in a binary number state, it is necessary to shape the waveform into a digital pulse state.To achieve this purpose, a core valator is used. The data is sliced and shaped into pulses at a standard level.
However, at this time, if the DC level of the data moves, it cannot be sliced at the center of the data standard, resulting in data errors. etc. must be placed before the comparator, and even in this case, the state of the disc (for optical type, etc., the bit C hole of the disc)
In the case of 0% discs, there are disadvantages such as not only the playback level changing but also the duty of 1.0 depending on the relative difference between the size of the disc and the diameter of the optical spot of the playback head. Is the playback level different because of the wear and tear? "(There is a drawback that the duty of #O# is different, and the data W is different for each disk.
The change in A rate was large.

The present invention was made in view of the above-mentioned drawbacks, and in order to always obtain accurate waveform shaping, a comparator is used. It is designed to be controlled.

An embodiment of the present invention will be described in detail below with reference to FIGS. 1 and 2.

Figure 1 is a system diagram of the present invention, and Figure 2 is! Fig. s1 is a waveform explanatory diagram of Fig. 1, in which an important signal is added to the input signal TIK in Fig. 1; The input signal is a disk or tape recorder.
This is the reproduced signal from etc. The long sword terminal TI is connected to the positive terminal of the core parator 1 of W, l, and the series circuit of the reference voltage @E1 and the resistor R1 is connected to the negative input terminal.
ing. Furthermore, the output of the second comparator 7 is connected to the resistor R3.
is connected to the negative input terminal of comparator 1 of ml through a capacitor CI whose one end is grounded.

The resistor RJx and capacitor C1 are time constant elements for gradual control without being affected by dropouts or the like. The output terminal of the first comparator l is the output terminal T!
It is connected to the differential circuit 2 as well as to the differential circuit 2. The output of the differentiating circuit 2 is taken out as two output pulses generated at the rising edge and falling edge of the input pulse, and the differentiating circuit 2
The two output terminals 10,000 are color/return circuit 4 and register 8.
The other is used as a clock for the latch circuit 5, and latches the counter value of the counter circuit 4. Reference numeral 3 designates a reference launching circuit for the counter circuit, which is connected to the counter circuit 4iC, and further provided with the center value of the counter circuit, and the output of the counter circuit g4 is given to the register 8 and the launch circuit 5. The signal is supplied to a digital-to-analog conversion circuit (hereinafter referred to as D/A) 6 through a latch circuit. The D/
The output of the A variable circuit is connected to the positive terminal of the second cono-parator 7, and is applied to the second cono-parator 7.
The voltage across the shield is compared to the voltage E2 corresponding during the reference pulse. Note that T3 is a data output. To explain the operation of the above circuit configuration in more detail, the reproduced signal shown in FIG. Suppose that is zero ■. Here, FIG. 2(a)' shows different reproduction signal waveforms of the tutee.

Such a reproduced signal is sliced by the first comparator 1 using a signal obtained by superimposing the voltage from the reference voltage source E1 and the feedback signal from the second comparator 7, but as mentioned above, the reference voltage and the feedback signal are zero. Therefore, there is one mouth in Figure 2 (b).
The output of the differentiating circuit 2 is a pulse obtained by the rising and falling edges of the waveform of the first conoparator 1, such as C, 2 or H', 2' in FIG.

The counter circuit 4 is loaded to the center value of the counter circuit 4 by the pulse C or 8'. In this way, the counter circuit 4 counts up and becomes zero when it reaches a predetermined count value, and such an operation is repeated. The period of the counter circuit at this time corresponds to the clock period of the reproduced data. Therefore, if the latch circuit 5 latches with the down pulse 2, 2', it will be latched at the phase with respect to a predetermined pulse in the positive region of the reproduced signal data. Figure 2 6111 cr)
is an analog representation of the output of the counter circuit 4. Since the load data D is set to the center value of the counter circuit 4, if the latch pulse has the correct phase, the latch value will be exactly equal to the data D. The larger the pulse, the larger the value is latched.

When the latch data of the latch circuit 5 is subjected to D/A conversion, a DC output is obtained as shown in FIG.

Such an output is given to the second conover regulator and compared with a reference voltage Ex set to a voltage corresponding to a predetermined phase, resulting in an error output (G, G' in FIG. 2(G)). If the pulse width of the reproduced waveform is larger than a predetermined width, a positive voltage is added to the voltage of the reference voltage source E1.
The city pressure increases and the output of the first comparator 1 increases by +1
1! It spreads during the lI pulse. Since such an operation is always carried out, the output pulse shown in FIG. 2(b) always has a correct tutee. Further, the sensor 8 extracts the signal shown in FIG. 2(b) by the color/return circuit 4 and outputs the digital reproduction data to the output terminal.

The present invention is configured as described above, and is capable of producing an 8'I.Even if there is an asymmetrical component in the level of the manually reproduced signal, the present invention can always perform optimal pulse shaping, and the cutting shape can be adjusted like a digital disc. It is possible to improve the problem of large data errors even when the reproduction input changes due to deafness, and to reproduce signals without errors.

In the above embodiment, a digital counter circuit is used as the phase detection means, but the phase detection means may also be an analog sawtooth wave, a sample hold circuit, or the like.

Furthermore, it is of course possible to extract only the minimum width without extracting the inverted output of all the data.
It is sufficient to operate a monostable multivibrator etc. using the pulses shown in the figure below to emit only the minimum width pulses, excluding long period pulses.With this configuration, the pulse inversion is very long. It is possible to eliminate errors due to differences in DC speed between the clock and input data. In addition, in the first embodiment, the error signal shown in FIG.
It is clear that the polarity may be reversed and the signal may be fed back to the signal side of the first comparator.

[Brief explanation of the drawing]

Figure 1 is a system diagram of the signal detection circuit of the present invention, Figure 2 is @1
It is a waveform explanatory diagram of a figure. In the figure, 1 is the first comparator, 2 is the differential circuit, 3 is the reference oscillation circuit, 4 is the counter circuit, 5 is the latch circuit, and 6 is the D
/A conversion circuit, 7 is a second comparator.

Claims (1)

[Claims] The output of the cono-parator means for comparing the reproduced signal in which the high frequency component has been lost with the reference voltage, and the output of the time-setting means for generating a predetermined base by using the outputs with different polarities and edge intervals from the comparator means and the excavation circuit etc. A signal detection circuit, characterized in that it controls the reference voltage of said comparator means by comparison.