JPS5817432B2 - trigger circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a trigger circuit, and particularly to a trigger circuit that generates a trigger force signal synchronized with an input waveform regardless of the positive or negative slope of the input waveform.

In electronic devices such as oscilloscopes, waveform digitizers, and transistor recorders, it is necessary to generate a trigger signal synchronized with the input waveform in order to stably display or record the input waveform. Obtained by applying voltage to the circuit.

A conventional trigger circuit includes, for example, a current switch comparator, a slope selector, and a reference (as shown in FIG.
(i.e. trigger) level controller.

The current switch type comparator is composed of elements 10 to 22, the emitters of a pair of transistors 10 and 12 are commonly connected through resistors 14 and 16, respectively.
The connection point is a high resistance resistor 1 which acts as a constant current source.
8 to a negative voltage source.

The collectors of transistors 10.12 are connected to a positive voltage source via load resistors 20, 22, respectively.

On the other hand, the switch 24 acts as a slope selector.
The two fixed contacts are respectively connected to the collectors of the transistors 10, 12, and the movable contact is connected to the output 26 of the circuit.

An input signal is applied to the pace of the transistor 10 from an input terminal 28 of the circuit, and a reference level is applied to the base of the transistor 12 from a reference level controller (potentiometer) 30.

When the positive slope of the input signal exceeds this reference level,
Transistor: Since the transistor 10 becomes conductive and the transistor 12 becomes non-conductive, the collector voltage of the transistor 12 changes from a low level to a high level.On the other hand, when the negative slope of the input signal falls below the reference level, the collector voltage of the transistor 10 changes from a low level to a high level. The voltage goes from a low level to a high level.

Therefore, the positive or negative slope can be controlled by the switch 24.
By selecting the mode and adjusting the potentiometer 30, a trigger signal synchronized to the desired level of either the positive or negative slope of the input signal can be obtained.

Further, when the elements 10 to 22 constitute a differential amplifier and a Schmitt circuit is connected to the output terminal 26, a similar operation is performed.

However, with the conventional trigger circuit shown in FIG. 1, it is difficult to detect abnormal phenomena such as glitches that have both positive and negative polarities, and it is also difficult to set the detection sensitivity to the maximum.

Furthermore, with the measuring instrument incorporating the conventional trigger circuit shown in Figure 1, the slope mode cannot be made positive and negative at the same time, so it is impossible to observe the leading and trailing edges of the input square wave at the same time. Met.

Therefore, an object of the present invention is to provide a trigger circuit that overcomes the drawbacks of the prior art described above.According to the trigger circuit according to the present invention, an abnormal phenomenon having both positive and negative polarities such as a glitch can be detected. Moreover, the maximum detection sensitivity can be set accurately and easily.

Furthermore, since trigger signals synchronized with both the positive and negative slopes of the input waveform can be obtained at the same time, the leading edge and trailing edge of the input rectangular wave can be observed simultaneously.

FIG. 2 is a block diagram showing an overview of a first embodiment according to the present invention.

The input 32 of the circuit is connected to the non-inverting input of a comparator 34 and the inverting input of a comparator 36 through a buffer amplifier 38, such as a voltage follower.

The inverting outputs of comparators 34 and 36 are connected to switches 42 and 42, respectively.
44 to the output 40 of the circuit.

The switches 42 and 44 are composed of mechanical switches, logic gates, and electronic switches such as CMO8 (complementary metal oxide semiconductor).

The output terminal 40 is connected to an external circuit 46 such as a sweep circuit of an oscilloscope.

Positive and negative voltages are applied across the series connected resistors 48, 52.56 and the potentiometer 50, and the connection point of the resistor 52.56 is connected to a mechanical or electronic switch 58.
It is grounded through.

Note that the resistance value of the resistor 52 is set to a low value of about 50Ω, for example.

The reference level control means, i.e. the variable tap of the potentiometer 50, is connected to the voltage follower 60 and the inverter 6.
2, respectively the inverting input of comparator 34 and comparator 3
Input and feedback resistors 64 and 66 of equal resistance value are connected to the inverter 62.

Since the input impedance of the operational amplifiers 60, 62 is very high, the voltage at the variable tap of the potentiometer 50 is directly proportional to its displacement.

The switch control means 68 opens the switch 58 when closing one of the switches 42 and 44, and closes the switch 4.
2. Switches 42 and 44 so that when both of them are closed, switch 58 is also closed.

58.

The operation of the first embodiment shown in FIG. 2 will be explained below.

The non-inverting input of the comparator 34 receives an input signal via a buffer amplifier 38, and the inverting input of the comparator 34 receives an input signal via a voltage follower 6.
0 through potentiometer 50, comparator 34 generates a negative pulse when the positive slope of the input signal exceeds the first reference level.

On the other hand, the non-inverting input terminal of the comparator 36 has the first reference level inverted by the inverter 62 with a gain of 1 (i.e., the first
Since the inverting input terminal of the comparator 34 receives the same input signal as the non-inverting input terminal of the comparator 34, the negative slope of the input signal becomes Below the reference level, comparator 36 generates a negative pulse.

Therefore, switch 42 is closed and switch 44.58 is closed.
Opening switches 42 and 58 puts the switch in positive trigger slope mode, while closing switch 44 and opening switches 42 and 58 puts it in negative trigger slope mode.

In either case, switch 58 is open so that positive and negative voltages are applied across potentiometer 50.

In this case, since the potential difference across the potentiometer 50 is set to be greater than the voltage change of the input signal, it is possible to generate a negative pulse from the comparator 34 or 36 in response to the desired level of the input signal.

On the other hand, to enter the positive/negative trigger slope mode, switches 42 and 44 are closed, and switch 58 is also closed.

Therefore, it is possible for the bird to generate a signal in response to abnormal phenomena such as glitches that have positive and negative polarities.

Furthermore, when the input waveform is a rectangular wave, it is clear that both the leading and trailing edges of the rectangular wave can be observed.

In this case, switch 58 is closed and the resistance of resistor 52 is small (e.g., about 50 ohms), so it is possible to respond to the slight glitch by moving the movable contact of potentiometer 50 to the lowest position in the diagram. It can be the maximum detection sensitivity that can generate a trigger signal.

Therefore, the operator can easily achieve the maximum detection sensitivity by simply turning the knob linked to the movable contact of the potentiometer 50, for example, fully counterclockwise, without relying on guesswork.

The reason for inserting the resistor 52 is that the comparator 34°3
This is to avoid adding 0■ to the inverting input terminal and non-inverting input terminal of each of the six inverting input terminals.

That is, when Ov is applied, the outputs of the comparators 34 and 36 are completely complementary, and the outputs of the comparators 34 and 36 are simultaneously applied to the output terminal 40.
．． This is because the output is generated from 36, so it cannot be supplied to the external circuit 46 as a correct trigger signal.

Therefore, in positive and negative trigger slope modes, the reference level does not change to both positive and negative voltages as in normal mode (i.e., positive or negative mode), but within a positive or negative voltage (
In other words, it is necessary to control the distance (not including Ov).

As can be seen from the above explanation, it is clear that in the positive/negative mode, the potentiometer 50 functions as a trigger signal detection sensitivity adjuster.

The signals from the comparators 34, 36 are applied to an external circuit (eg, a sweep circuit) 46 to generate a ramp signal synchronized to the input signal.

FIG. 3 is a detailed circuit diagram specifically illustrating the embodiment of FIG. 2 according to the present invention.

For simplicity's sake. Identical parts are designated by the same numbers.

An input 32 of the circuit is connected to an input of a buffer amplifier 38;
The output terminal of this buffer amplifier 38 is connected to the input resistor 70.72.
via the non-inverting input of comparator 34 and comparator 3, respectively.
It is connected to the inverting input terminal of 6.

Comparator. The inverting and non-inverting output terminals of 34 are respectively NAN
Connect to one input terminal of D game 1-74, 76, and connect this N
The other input terminals of the AND gates γ4 and 76 are directly connected to each other and are included in the switch controller 68 to the negative mode fixed connection of a switch 78 having a movable grounded contact.

connected to the dots.

NAND gate 74. The outputs of γ6 are connected to the non-inverting and inverting inputs of comparator 34 via feedback resistors 80, 82, respectively.

A reference (trigger) level voltage is applied to the inverting input of comparator 34 from voltage follower 60 through input resistor 84 .

On the other hand, the non-inverting and inverting output terminals of the comparator 36 are NA
It is connected to one input terminal of the NAND gate 86.88, and the other input terminal of the NAND gate h86.88 is directly connected to each other and connected to the positive mode fixed contact of the switch 78.

The output terminals of the NAND gates 86 and 88 are connected to the inverting and non-inverting input terminals of the comparator 36 via feedback resistors 90 and 92, respectively, and the non-inverting input terminals are connected to the input resistor 94.
A reference level voltage having a reverse phase relationship with the reference level from the voltage follower 60 is applied from an amplifier (inverter) 62 with a gain of 1 through the voltage follower 60 .

Since the outputs of NAND gates 1-74, 76 and 86.88 are fed back to the input terminals of comparators 34 and 36, respectively, comparators 34 and 36 have hysteresis.

In other words, comparators 34 and 36 operate similar to Schmitt trigger circuits.

NAND gates 74.76 and 86.88 are the second
1 corresponds to switch 42 and 44 in the figure, output terminal 40 of the circuit
are connected to each other via a diode 96°98.

The combination of one comparator and two NAND gates is
For example, an integrated circuit type 529 manufactured by Signetics may be used.

The negative mode fixed contact of switch 78 is connected to a positive voltage source through a resistor 100 and further connected to the base of transistor 102 through a diode 104 and resistor 106.

On the other hand, the positive mode fixed contact of the switch 78 is connected to the resistor 108.
It is further connected to a positive voltage source through a diode 110 and to the contacts of a diode 104 and a resistor 106.

Note that the positive/negative mode fixed contacts of the switch 78 are open.

A positive voltage is applied to the emitter of the transistor 102,
Its collector is connected via a resistor 114 to the base of a switching transistor 112, and via a resistor 116 to a bias circuit consisting of a resistor 118 and a Zener diode 120.

A bias voltage is applied to the emitter of the transistor 112 from the bias circuit, and the collector is connected to the load resistor 12.
2 to a positive voltage source.

Note that opening and closing of the switches 54 and 58 are controlled by the collector voltage of the transistor 112.

The switches 54,58 are, for example, integrated circuits of the CD4066 type with four FET (field effect transistor) switches, in which case the switch 54 is a CD4066 type integrated circuit with four FET (field effect transistor) switches.
One FET of 066 is used, and the switch 58 connects the remaining three FETs in parallel.

Switches 54, 58 are closed and closed when the collector voltage of transistor 112 is at low and high levels, respectively.

A predetermined voltage is applied to the upper end of the potentiometer 50 by a voltage divider consisting of resistors 48 and 124.

The lower end of resistor 52 is connected via switch 54 to the connection point of series-connected resistors 126 and 128, and also to the connection point of series-connected resistors 130 and 132.

Therefore, when switches 54,58 are open,
A predetermined negative voltage is applied to the lower end of the resistor 52.

The reason for providing the resistors 126, 128 and the switch 54 is as follows.

That is, in general, the resistance value when the FET is conductive is not zero, and this resistance value differs depending on the parts used, which becomes an obstacle in specifying the maximum detection sensitivity explained with reference to FIG.

Therefore, a sufficient current is caused to flow through the lower end of the resistor 52 through the switch 54 to eliminate the error caused by the resistance value when the switch 58 is turned on, and when the switch 54 and 58 are closed,
This is to sufficiently lower the voltage at the lower end of the resistor 52 to around O■.

Now, when the negative slope mode is set by the trigger slope selection switch 78, the transistor 10
2, the base potential decreases and becomes conductive, and the collector potential increases.

Transistor 112 is therefore conductive and its collector is at a low potential, and as mentioned earlier, switch 54.5
Open 8.

On the other hand, in this case, the NAND gates 74 and 76 are. Since one input terminal of each is grounded, it becomes inoperable, but NAN
D gates 86.8B are in an energized state because a positive voltage is applied to one input terminal of each.

Therefore, when the negative slope of the input signal is below the reference level from potentiometer 50, the comparator.

A positive pulse is generated from the non-inverting output of 36, which is inverted by NAND gate 86 and applied to external circuit 46.

On the other hand, if the movable contact of switch 78 switches to the positive mode contact, then in the negative slope mode described above.

Similarly, the switches 54 and 58 remain open, but this time, one of the input terminals of the NAND gates 86 and 88 is grounded, so the NAND gates 86 and 88 are inactive; is in an energized state.

Therefore, when the positive slope of the input signal exceeds the reference level applied to the inverting input of comparator 34, a positive pulse is generated from the non-inverting output of comparator 34, and this positive pulse is inverted by NAND gate 76. and is applied to the external circuit as a negative pulse.

By the way, when the movable contact of the switch 78 comes to the position of the positive/negative mode fixed contact, the circuit of FIG. 3 enters the positive/negative trigger slope mode.

In this case, the collector voltage of transistor 112 will be high, so switches 54, 58 will be closed.

Therefore, the lower end of the resistor 52 is maintained at approximately 0.

Note that since all the NAND gate doors 4,76,86,88 are in the energized state, the positive and negative slopes of the input signals exceed the first reference level from the voltage follower 60, respectively.
Alternatively, when the voltage falls below the second reference level from the inverter 62, the external circuit 46 receives and receives the trigger signal, respectively.

Since the trigger circuit shown in FIG. 3 uses two reference levels having mutually opposite phases, it has a so-called dead zone in which input signal levels between these reference levels are not triggered.

FIG. 4 is a circuit diagram showing another embodiment according to the present invention.

Since this embodiment is similar to the embodiment shown in FIG. 2, the same parts are denoted by the same reference numerals, and for the sake of simplicity, only the differences between the two will be explained.

In the embodiment shown in FIG. 2, one of the reference levels is inverted, but in the embodiment shown in FIG.
The same effect as in the figure is obtained.

For this reason, an inverter 140 is inserted between the output terminal of the buffer amplifier 38 and the non-inverting input terminal of the comparator 34, except for the voltage follower 60, inverter 62, and resistors 64 and 66 shown in FIG.

Therefore, it is clear that the above-mentioned dead zone exists also in this embodiment.

Embodiments of the present invention can generate trigger signals in response to abnormal phenomena having both positive and negative polarities, such as glitches, by using positive and negative trigger slope modes, as previously described in detail. It is suitable for use in measurement devices such as oscilloscopes that observe such phenomena.

Furthermore, maximum sensitivity can be easily and accurately set, so
It has features such as not requiring the operator's intuition when setting the maximum sensitivity.

Although the present invention has been described in detail above, various changes and modifications based on the above-described embodiments will be obvious to those skilled in the art.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional trigger circuit, Fig. 2 is a block diagram of a trigger circuit according to the present invention, Fig. 3 is a detailed circuit diagram of the block diagram of Fig. 2, and Fig. 4 is a circuit diagram of a trigger circuit according to the present invention. FIG. 2 is a block diagram of another such circuit. 34, 36... Comparator, 42, 44, 58...
. . . switch control, 50 . . . variable level generation means, 68 . . . switch control means.

Claims (1)

[Claims] 1 variable reference level generation means for generating a variable reference level; first comparison means for generating an output signal corresponding to the reference level with a positive slope of the input signal; a second comparison means for generating a corresponding output signal, and two switch means respectively connected between the output terminals of the first and second comparison means and the output terminal of the circuit; A tri-circuit, characterized in that only one side is selectively closed, or both are closed at the same time, to obtain a trigger signal synchronized with an input signal from an output terminal of the circuit.