JPS58172765A - Data processor - Google Patents

Abstract

PURPOSE:To prevent a processor device from deteriorating in performance owing to a fault of another processor, by making the contents of a tag part invalid only when every processor detects an error and a main storage device detects no error. CONSTITUTION:For writing from a processor 2B to the main storage 1, an address signal is sent from a cash memory 4B to an address bus 3AD. This address signal is set in a parity checking circuit 10 and an invalid address register 6A. A parity checking circuit 7A makes a parity check on this address signal and when there is no error, the contents of a tap part 5A are made ineffective. If an error signal is outputted from the circuit 7A, signal with a logical level 1 is outputted from an AND gate 9A only when the output of an inverter 8A has the logical level 1, performing in validation processing. The circuit 10, on the other hand, makes a parity check on the address signal; when there is no error, the requested writing is carried out and when an error is found, the invalidation processing is not performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device having a high speed buffer storage device (hereinafter referred to as cache memory).

2. Description of the Related Art Configuration and Operation of Prior Art A plurality of processor devices each having a cache memory may share one main storage device to process data. In such a case, when one processor device writes to a certain address location in the main memory, it is necessary to notify the other processor devices of the address where the convolution was performed. This means that if another processor's cache memory holds a copy of the main memory before the address was written, the write invalidates the data at the address in the cache. (+7 rad)
This is because it is necessary to process the fact that it has become.

Cache memory invalidation processing is performed block by block, with 9, for example, 16 bytes as one block, and when any byte within one block is written, the entire block is invalidated. A processor device that wishes to write to the main memory sends an address signal indicating the address to be written to the main memory, and at the same time that address signal is set in the invalid address registers of all other processor devices. The main memory first performs a parity check on the sent address signal, and if there is no parity error, the requested write is performed, but if there is an error, it notifies the requesting processor electronics that an error has occurred. No writing is performed.

Disadvantages of the Prior Art Conventionally, in other processor devices, if the block with the address set in the invalid address register is in the cache memory, that block is unconditionally invalidated. A drawback is that the cache memory is only invalidated even if the signal becomes a parity error in the main memory and no writing is actually performed.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional books as described above.In each processor device, a parity check is performed on the contents of the invalid address register to detect and eliminate errors. The purpose of the present invention is to provide a data processing device in which the processing capacity of the processor device is disabled unnecessarily due to an abnormality in a processor other than the processor device, by disabling the main memory only when no error is detected. It is said that

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings. The drawing is a block diagram showing an embodiment of the present invention, in which (1) is a main memory, (2A) and (2B) are processor units, (3) is a common bus, and bus (3; is an address bus (
3AJ)), data bus (3DA), control information line (3
(31)) is an error reporting line in the control information line (3C). (4A) and (4B) are the cache memories, respectively, and (5A) and (5B) #'i are the tag parts of the data held in the cache memories (4A) and (4B), respectively, in the main storage device (1). Address is stored. (6A) and (6B) are invalid address registers, respectively (7A).

(7B) U parity check circuit% (8A
) #(8B) t'i each inverter, (9A) e
(913) are an AND gate, and (1G is a retai check circuit in the main memory device TILL), respectively.

Assuming that the operational processor device (2B) of the present invention performs a convolution to the main memory device (1), it sends out an address signal indicating the address to be written from the cache memory (4B) to the address bus (3AD). This address signal is input from the address bus (3AD) to the parity check circuit and is set in the invalid address register (6A). The parity check circuit (7A) performs a parity check on the address signal set in the register (6A), and if there is no error, the block of addresses determined by the contents of the register (6A) is sent to the tag section (5A).
Disable this when it is inside. If an error signal (in the case shown in the figure, the error signal is logic "L") is output from the parity check circuit (7), the inverter (8
Only when the output of A) is logic "1", a logic "1" signal is output from the AND gate (nine people) and invalidation processing is performed.

Parity check circuit αaFi checks the parity of the input address signal, and if there is no error, performs the requested write, and if there is an error, sends an error report line (3D)
The error signal of logic rlJ is sent to.

In this case, the output of the inverter (8A) becomes logic "0", so no invalidation process is performed.

Another embodiment of the invention Figure 'rjn shows a case where there are two processors,
The same is true when there is a plurality of arbitrary processor devices and which processor device makes a commitment to the main storage device.

Effects of the Present Invention As described above, according to the present invention, by adding a simple circuit, it is possible to reduce the effect of performance deterioration of one's own processor device due to an abnormality in a processor device other than the own processor device. .

[Brief explanation of drawings]

The drawing is a block diagram showing an embodiment of the present invention. (1)... Main memory % (2A), (2B)...
・Processor device, (4A), (4B)...cache memory, (6A), (6B)-" ・Invalid address register, (7A), (7B)...1 parity check, +lO1...・Parity check circuit in the main memory. Agent Nobu Kuzumachi -

Claims (1)

[Claims] In a data processing device in which a plurality of processor devices use a common main memory device, an address signal specifying an address position to be written to the memory in the main memory device from one of the processor devices is sent via an address bus to the main memory device. a parity check circuit within a main memory IFC that performs a parity check on the address signal in the main memory when it is sent to the device; and a parity check circuit provided in the valley processor device that specifies a write address from another processor device on the address bus. When a parity check circuit in the processor device performs a parity check on the next address signal sent to the address signal, and when a parity error is detected in the parity check circuit in the processor device, a parity error is detected in the parity check circuit in the main memory device. A data processing device comprising means for invalidating a portion of the high-speed buffer storage device of the processor device associated with the address specified by the address signal only when the processor device is not used.