JPS58172265U - fax machine - Google Patents
fax machineInfo
- Publication number
- JPS58172265U JPS58172265U JP6890782U JP6890782U JPS58172265U JP S58172265 U JPS58172265 U JP S58172265U JP 6890782 U JP6890782 U JP 6890782U JP 6890782 U JP6890782 U JP 6890782U JP S58172265 U JPS58172265 U JP S58172265U
- Authority
- JP
- Japan
- Prior art keywords
- transmission mode
- conversion circuit
- circuit
- black
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるファクシミリ装置の要部概略構成
を示すブロック図、第２図及び第３図はその動作説明の
ための信号波形図である。
１・・・Ａ／Ｄ変ｔＡ回路、２〜．４・・・ラインメモ
リ、５・・・符号化回路、６・・・制御回路、７・・・
デジタルモデム回路、８・・・アナログモデム回路。FIG. 1 is a block diagram showing a schematic configuration of main parts of a facsimile apparatus according to the present invention, and FIGS. 2 and 3 are signal waveform diagrams for explaining its operation. 1...A/D variable tA circuit, 2-. 4... Line memory, 5... Encoding circuit, 6... Control circuit, 7...
Digital modem circuit, 8... analog modem circuit.
Claims (1)
非圧縮中間調伝送を行なうファクシミリ装置に於いて、
読取手段から得たアナログ画信号を圧縮符号化伝送モー
ドでは白黒２値信号に変換し中間調伝送モードでは多階
調を表わすバイナリ′ −信号に変換すべく動作するＡ
／Ｄ変換回路と、このＡ／Ｄ変換回路と符号化回路及び
アナログモデム回路との間に設けられた複数個のライン
メモリと、前記二つのモードに応じて上記Ａ／Ｄ変換回
路を前記各動作に切換えると共に、前記各メモリの書込
み、読出しを制御する制御回路とを備え、圧縮符号化伝
送モードでは前記Ａ／Ｄ変換回路からの白黒２値信号を
前記各メモリに１ライン分ずつ循環的に格納し、中間調
伝送モードでは前記Ａ／Ｄ変換回路からのバイナリ−信
号を前記各メモリに１桁分ずつ格納するようにしたこと
を特徴とするファクシミリ装置。In a facsimile machine that performs compression encoding transmission of black and white binary image signals and uncompressed halftone transmission of analog image signals,
A that operates to convert the analog image signal obtained from the reading means into a black and white binary signal in the compression encoding transmission mode and into a binary '-signal representing multiple gradations in the halftone transmission mode.
A/D conversion circuit, a plurality of line memories provided between the A/D conversion circuit, the encoding circuit, and the analog modem circuit; and a control circuit that controls writing and reading of each of the memories, and in the compression encoding transmission mode, cyclically sends a black and white binary signal from the A/D conversion circuit to each of the memories one line at a time. 2. A facsimile apparatus according to claim 1, wherein the binary signal from the A/D conversion circuit is stored in each memory one digit in halftone transmission mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6890782U JPS58172265U (en) | 1982-05-11 | 1982-05-11 | fax machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6890782U JPS58172265U (en) | 1982-05-11 | 1982-05-11 | fax machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58172265U true JPS58172265U (en) | 1983-11-17 |
| JPS6329333Y2 JPS6329333Y2 (en) | 1988-08-08 |
Family
ID=30078655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6890782U Granted JPS58172265U (en) | 1982-05-11 | 1982-05-11 | fax machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58172265U (en) |
-
1982
- 1982-05-11 JP JP6890782U patent/JPS58172265U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6329333Y2 (en) | 1988-08-08 |
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