JPS58171155A - System for testing circuit - Google Patents

System for testing circuit

Info

Publication number
JPS58171155A
JPS58171155A JP57053404A JP5340482A JPS58171155A JP S58171155 A JPS58171155 A JP S58171155A JP 57053404 A JP57053404 A JP 57053404A JP 5340482 A JP5340482 A JP 5340482A JP S58171155 A JPS58171155 A JP S58171155A
Authority
JP
Japan
Prior art keywords
test
circuit
signal
terminal
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57053404A
Other languages
Japanese (ja)
Inventor
Hideo Kasahara
笠原 英夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57053404A priority Critical patent/JPS58171155A/en
Publication of JPS58171155A publication Critical patent/JPS58171155A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00Arrangements for monitoring or testing data switching networks
    • H04L43/50Testing arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To diagnose the normality between a center and each terminal in a circuit connected by a multi-drop means by adding a testing circuit to a circuit side interface for an MODEM in a general data communication terminal device. CONSTITUTION:When a multi-drop circuit is to be tested by detecting a communication trouble through some means during communication, a center device 100 separates an MODEM 102 logically and a test controlling device 103 indicates a test and actuates a test mode switching circuit 104. A test signal generating circuit 103-2 sends a test starting signal to a terminal station device 200 for a fixed period. In each terminal station device 204, a signal discriminating circuit 203-3 detects the test starting signal and a signal branching circuit 204 turns the mode to the test mode. In the center device 100, a test signal generating circuit 103-2 sends a test signal assigned to each terminal station device successively for a fixed period and then monitors a response signal from a response signal generating circuit 203-2 in the terminal station device and diagnoses the circuit state.

Description

【発明の詳細な説明】 本発明はデータ通信方式に関し特にマルチドロップ接続
の回線試験診断方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data communication systems, and particularly to a line test and diagnosis system for multi-drop connections.

従来、マルチドロップ接続された回線との通信に於て2
通信障害が発生した場合、1つの方法として2分岐され
た各端末は物理的には常時複数個接続され、センタから
遠隔制御によシ個別に端末の制御/監視を行おうとした
場合、変復調装置を介し試験データを流して試験を行う
か、iた他の験者によシ物理的に切シ離しそ該試験端末
との間で例えば端末のディノタルルーゾパ、りをセット
する等して折シ返し試験を行う方法があった。しかしな
がら、上記前者の方法では2回線が故障なのか変復調装
置が故障なのかを判別できない所謂階層分けが困難とな
り、また後者の方法では、試験者を必要とするなど手間
が掛かるという欠点があった。
Conventionally, in communication with multi-drop connected lines, 2
In the event of a communication failure, one method is to physically connect multiple terminals that are branched into two at all times, and if you attempt to control/monitor each terminal individually by remote control from the center, the modulation/demodulation equipment Perform the test by transmitting the test data via the test terminal, or have another tester physically disconnect the test terminal, for example by setting the terminal's Dinotal Luzopa, etc. There was a way to do a repeat test. However, the former method described above has the drawback that it is difficult to distinguish between two lines or the modem which is faulty, so-called hierarchical classification, and the latter method requires a tester and is time-consuming. .

本発明の目的は、遠隔地にマルチドロツノ接続された複
数個の端末との間に於て、一般のデータ通信用端末装置
の変復調装置の回線側インタフェースに試験用回路を付
加することにより、センタと各端末との間の正常性を変
復調レベルと階層を分離し、且つセンタからのリモート
制御により試験可能とするシステムを提供することにあ
る。
An object of the present invention is to add a test circuit to the line side interface of the modem of a general data communication terminal device between a plurality of terminals connected to a center in a remote location. It is an object of the present invention to provide a system that separates the modulation/demodulation level and hierarchy of normality between terminals and allows testing by remote control from a center.

本発明によれば、センタ装置と、該センタ装置に従属し
て同一回線に接続された少なくとも1つの端局装置とか
ら構成される通信システムに於て。
According to the present invention, a communication system includes a center device and at least one terminal device subordinate to the center device and connected to the same line.

前記センタ装置は1回線試験を指示し該試験結果を受け
る制御部と、前記端局装置に共通に試験開始・終了信号
を発しまた該端局装置に個別に割り当てられた試験信号
を選択的に発する試験信号発生回路と、前記端局装置か
らの前記試験信号に対応する応答信号を検出する試験信
号検出回路と。
The center device issues test start and end signals in common to a control unit that instructs a single line test and receives the test results, and the terminal device, and selectively sends test signals individually assigned to the terminal device. a test signal generation circuit that generates a test signal; and a test signal detection circuit that detects a response signal corresponding to the test signal from the terminal device.

一般通信と試験通信の切9分けを行なう試験モード切替
回路とを具備し、前記各端局装置は、一般通信と試験通
信の信号分岐を行なう信号分岐回路と、iIJ記試験開
始・終了信号を受けまた前記試験信号を識別する信号回
路と、前記センタ装置に前記応答信号を発する応答信号
発生回路とを具備した回線試験方式が得られる。
Each terminal device is equipped with a test mode switching circuit that separates general communication and test communication, and each terminal device has a signal branching circuit that branches signals between general communication and test communication, and a signal branching circuit that branches signals between general communication and test communication, and a signal branching circuit that branches signals between general communication and test communication, and A line test system is obtained which includes a signal circuit for receiving and identifying the test signal, and a response signal generation circuit for issuing the response signal to the center device.

本発明では、何らかの手段によシ通信異常を検出し該回
線の試験を行う場合、センタ装置は変復調装置を論理的
に切離し、制御部によシ試験指示を行い試験モード切替
回路を作動させる。次に。
In the present invention, when a communication abnormality is detected by some means and the line is tested, the center device logically disconnects the modem, issues a test instruction to the control unit, and activates the test mode switching circuit. next.

試験信号発生回路より端局装置に対し一定時間試験開始
信号を送出する。各端局装置は、信号識別回路で該試験
開始信号を検出し、信号分岐回路で試験モードに移行す
る。次に、センタ装置では。
The test signal generation circuit sends a test start signal to the terminal equipment for a certain period of time. Each terminal device detects the test start signal with a signal identification circuit, and shifts to a test mode with a signal branch circuit. Next, the center device.

試験信号発生回路から順次各端局装置に割シ当てられた
試験信号を一定時間送出後、該端局装置の応答信号発生
回路からの応答信号を監視し2回線状態を診断する。全
端局装置の回線状態の診断が終了すると、センタ装置は
、全端局装置に共通な試験終了信号を一定時間送出し、
端局装置を一般通信モードに切戻す。その後、センタ装
置に於ても制御部の制御の下に、試験モード切替回路を
復旧させる。
After the test signal generation circuit sequentially transmits the test signal assigned to each terminal device for a certain period of time, the response signal from the response signal generation circuit of the terminal device is monitored to diagnose the two-line state. When the diagnosis of the line status of all end station devices is completed, the center device sends a test end signal common to all end station devices for a certain period of time,
Switch the terminal equipment back to general communication mode. Thereafter, the test mode switching circuit is restored in the center device under the control of the control section.

次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

第1図は1本発明によるセンタ装置と端局装置との接続
形態を示すシステム構成図であり、センタ装置100に
複数の端局装置200,300が回線分岐装置500を
介してマルチドロツノ接続されている。本実施例では端
局装置として4線式のハイレベルデータリンク伝送制御
手順を用いたファクシミリ装置を使用した。
FIG. 1 is a system configuration diagram showing a connection form between a center device and a terminal device according to the present invention, in which a plurality of terminal devices 200 and 300 are connected to a center device 100 via a line branching device 500. There is. In this embodiment, a facsimile machine using a four-wire high-level data link transmission control procedure is used as the terminal equipment.

センタ装置は、大別すると中央処理装置101゜又端局
装置は、端末装置201,301.4線式変復調装置2
02,302.試験回路203゜:303及び信号分岐
回路204,304から構成される。
The center equipment can be roughly divided into the central processing unit 101, and the terminal equipment includes the terminal equipment 201, 301.4-wire modulation/demodulation equipment 2.
02,302. It consists of a test circuit 203°: 303 and signal branch circuits 204, 304.

第2図は本発明によるセンタ装置の一実施例の構成を示
したブロック図である。
FIG. 2 is a block diagram showing the configuration of an embodiment of the center device according to the present invention.

通信中に何らかの障害等によシ回線試験の申告があった
場合センタ装置100では、中央処理装置101に付属
しているタイシライタに該回線に対する回線試験コマン
ドを投入する。中央処理装置101では、該コ゛−マン
トにより該回線に接続される端局装置に対し回線切断コ
マンドを出し且つ変復調装置102に対しR8信号のO
FFを行う。
If a line test is requested due to some kind of failure during communication, the center device 100 inputs a line test command for the line to a tie writer attached to the central processing unit 101. The central processing unit 101 uses the command to issue a line disconnection command to the terminal equipment connected to the line, and sends the R8 signal O to the modem unit 102.
Perform FF.

端局装置は回線切断信号を受信し且つCD信号OFF検
出により初期状態になる。
The terminal device receives the line disconnection signal and enters the initial state upon detection of the CD signal OFF.

次に、センタ装置100では、中央処理装置101の指
示により、試験制御装置103は試験モード設定する為
リレーを動作し、切替回路104を破線の様に試験制御
装置103に切替える。
Next, in the center device 100, the test control device 103 operates a relay to set the test mode in response to an instruction from the central processing device 101, and switches the switching circuit 104 to the test control device 103 as shown by a broken line.

次に、試験制御装置103では、中央処理装置101の
制御の下に、制御回路103−1によシ試験信号発生回
路103−2にマルチドロツノ接続された各端末共通の
試験開始信号の送出を指示する。
Next, in the test control device 103, under the control of the central processing unit 101, the control circuit 103-1 instructs the test signal generation circuit 103-2 to send out a test start signal common to each terminal connected by multiple terminals. do.

本システムでは試験信号は第4図に示した様に一般の押
しボタン電話機に使用されている標準のPBMF信号を
利用した。
In this system, the test signal used was a standard PBMF signal used in general push-button telephones, as shown in FIG.

第3図は本発明による端局装置の一実施例の構成を示し
たブロック図である。
FIG. 3 is a block diagram showing the configuration of an embodiment of the terminal equipment according to the present invention.

端局装置200では、信号分岐回路204の分岐増幅器
204−1を介して該試験開始信号を試験回路203に
伝達される。試験回路203では。
In the terminal device 200, the test start signal is transmitted to the test circuit 203 via the branch amplifier 204-1 of the signal branch circuit 204. In the test circuit 203.

信号識別回路203−3により該試験開始信号を識別し
、試験制御回路203−1へ通知することによりリレー
を起動させ、受信線切替回路204−3を終端回路20
4−4に切替えるとともに、送信線切替回路204−2
を試験回路203に切替える。
The signal identification circuit 203-3 identifies the test start signal, and notifies the test control circuit 203-1 to activate the relay, and switches the reception line switching circuit 204-3 to the termination circuit 20.
4-4, and the transmission line switching circuit 204-2.
is switched to the test circuit 203.

次に、センタ装置100では試験開始信号を一定時間送
信後に一定タイミングのインタバルヲトった後に、試験
信号発生回路103−2よシ分岐接続された第1位の端
局装置200への試験信号を一定時間送出する。
Next, in the center device 100, after transmitting the test start signal for a certain period of time and waiting at a certain timing interval, the test signal is sent to the first terminal device 200 which is branch-connected from the test signal generation circuit 103-2. Send time.

端局装置200に於ては第4図に示された様にノ 予め設定された自端末用の試験信号の検出を信号識別回
路203−3で行い、試験制御回路203−1に通知す
る。試験制御回路203−1で該信号を受信すると、自
局に割シ当てられた応答信号を一定時間応答信号発生回
路203−2を介してセンタ装@100に送出する。
In the terminal device 200, as shown in FIG. 4, the signal identification circuit 203-3 detects a preset test signal for its own terminal, and notifies the test control circuit 203-1. When the test control circuit 203-1 receives the signal, it sends the response signal assigned to its own station to the center device @100 for a certain period of time via the response signal generation circuit 203-2.

センタ装置100では、試験信号検出回路103−3で
端局装置200からの応答信号検出を行い、その結果を
試験制御回路103−1を介して中央処理装置101へ
伝達する。このとき、センタ装置100が一定時間内に
端局装置200からの応答が正常受信出来ない場合、タ
イムアウトし次位の端局装置(図示せず)への試験信号
送出へ移行する。
In the center device 100, the test signal detection circuit 103-3 detects a response signal from the terminal device 200, and transmits the result to the central processing unit 101 via the test control circuit 103-1. At this time, if the center device 100 cannot normally receive a response from the terminal device 200 within a certain period of time, it times out and shifts to sending a test signal to the next terminal device (not shown).

同一回線に収容する全ての端局装置の試験を完了すると
、中央処理装置101の制御の下に、試験制御装置10
3を介し、試験信号発生回路103−2から試験終了信
号を一定時間送出する。全ての端局装置は、該試験開始
信号を受信し一般通信モードへ切戻しを行う。次に、セ
ンタ装置100では。
When the test of all the terminal equipment accommodated on the same line is completed, the test control equipment 10 under the control of the central processing unit 101
3, a test end signal is sent from the test signal generation circuit 103-2 for a certain period of time. All terminal devices receive the test start signal and switch back to the general communication mode. Next, in the center device 100.

試験終了信号送出完了後一定時間経過後、一般通信モー
ドへ切戻しを行う。
After a certain period of time has elapsed after sending the test end signal, the communication mode is switched back to normal communication mode.

上記の実施例では、各端局装置の試験信号と応答信号を
個別に割シ当てて実現したが、試験信号のみを個別に割
り当て応答信号を共通化することにより1回線に9個の
端局迄収容可能となる。
In the above embodiment, the test signal and response signal of each terminal equipment were individually assigned, but by individually assigning only the test signal and sharing the response signal, nine terminal stations can be connected to one line. It can be accommodated until

以上の説明で明らかなように1本発明では、マルチドロ
、ゾ接続された回線を汎用のP BMFセンダ/し/−
・ぐを組合せた簡単な方式で遠隔地から診断することが
出来るという効果がある。
As is clear from the above description, in the present invention, the multi-channel connected line is connected to a general-purpose P BMF sender/-
・It has the effect of being able to diagnose from a remote location using a simple method that combines

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるセンタ装置と端局装置との接続形
態を示したシステム構成図、第2図は本発明によるセン
タ装置の一実施例の構成を示したブロック図、第3図は
本発明による端局装置の一実施例の構成を示したブロッ
ク図、第4図は本発明の一実施例に用いられる試験信号
例を示した図である。 記号の説明:100はセンタ装置、101は中央処理装
置、102は変復調装置、103は試験制御装置、10
3−’1は制御回路、103−2は試験信号発生回路、
103−3は試験信号検出回路。 104は試験モード切替回路、200は端局装置。 201は端末装置、202は変復調装置、203は試験
回路、203−1は試験制御回路、203−2は応答信
号発生回路、203−3は信号識別回路。 204は信号分岐回路、204−1は分岐増幅器。 204−2は送信線切替回路、204−3は受信線切替
回路、204−4は終端回路、300は端局装置。 301は端末装置、302は変復調装置、303は試験
回路、304は信号分岐回路、500は回線分岐装置を
それぞれあられしている。 第2図 第3図
FIG. 1 is a system configuration diagram showing a connection form between a center device and a terminal device according to the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the center device according to the present invention, and FIG. FIG. 4 is a block diagram showing the configuration of an embodiment of the terminal equipment according to the invention, and FIG. 4 is a diagram showing an example of a test signal used in the embodiment of the invention. Explanation of symbols: 100 is a center device, 101 is a central processing unit, 102 is a modem device, 103 is a test control device, 10
3-'1 is a control circuit, 103-2 is a test signal generation circuit,
103-3 is a test signal detection circuit. 104 is a test mode switching circuit, and 200 is a terminal device. 201 is a terminal device, 202 is a modulation/demodulation device, 203 is a test circuit, 203-1 is a test control circuit, 203-2 is a response signal generation circuit, and 203-3 is a signal identification circuit. 204 is a signal branch circuit, and 204-1 is a branch amplifier. 204-2 is a transmission line switching circuit, 204-3 is a receiving line switching circuit, 204-4 is a termination circuit, and 300 is a terminal device. 301 is a terminal device, 302 is a modem, 303 is a test circuit, 304 is a signal branching circuit, and 500 is a line branching device. Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 1、 センタ装置と、該センタ装置に従属して同一回線
に接続された少なくとも1つの端局装置とから構成され
る通信システムに於て、前記センタ装置は1回線試験を
指示し該試験結果を受ける制御部と、前記端局装置に共
通に試験開始・終了信号を発しまた該端局装置に個別に
割シ当てられた試験信号を選択的に発する試験信号発生
回路と。 前記端局装置からの前記試験信号に対応する応答信号を
検出する試験信号検出回路と、一般通信と試験通信の切
シ分けを行なう試験モード切替回路とを具備し、前記各
端局装置は、一般通信と試験通信の信号分岐を行なう信
号分岐回路と、前記試験開始・終了信号を受けまた前記
試験信号を識別する信号識別回路と、前記上/り装置に
前記応答信号を発する応答信号発生回路とを具備した回
線試験方式。
[Claims] 1. In a communication system comprising a center device and at least one terminal device subordinate to the center device and connected to the same line, the center device performs a single line test. a control unit that gives instructions and receives the test results; and a test signal generation circuit that commonly issues test start and end signals to the terminal equipment and selectively issues test signals individually assigned to the terminal equipment. . Each of the terminal devices includes a test signal detection circuit that detects a response signal corresponding to the test signal from the terminal device, and a test mode switching circuit that separates between general communication and test communication, and each of the terminal devices includes: a signal branch circuit that branches signals between general communication and test communication; a signal identification circuit that receives the test start/end signal and identifies the test signal; and a response signal generation circuit that issues the response signal to the uplink device. A line test method equipped with
JP57053404A 1982-03-31 1982-03-31 System for testing circuit Pending JPS58171155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57053404A JPS58171155A (en) 1982-03-31 1982-03-31 System for testing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57053404A JPS58171155A (en) 1982-03-31 1982-03-31 System for testing circuit

Publications (1)

Publication Number Publication Date
JPS58171155A true JPS58171155A (en) 1983-10-07

Family

ID=12941887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57053404A Pending JPS58171155A (en) 1982-03-31 1982-03-31 System for testing circuit

Country Status (1)

Country Link
JP (1) JPS58171155A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5362913A (en) * 1976-11-17 1978-06-05 Fujitsu Ltd Self-diagnosis system for transmission device
JPS5483304A (en) * 1977-12-15 1979-07-03 Nec Corp Control system for automatic circuit folding
JPS55147857A (en) * 1979-05-03 1980-11-18 Ibm Test and warning device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5362913A (en) * 1976-11-17 1978-06-05 Fujitsu Ltd Self-diagnosis system for transmission device
JPS5483304A (en) * 1977-12-15 1979-07-03 Nec Corp Control system for automatic circuit folding
JPS55147857A (en) * 1979-05-03 1980-11-18 Ibm Test and warning device

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