JPS58168390A - Compensating device of time axis - Google Patents

Abstract

PURPOSE:To pull-in a control system quickly and stably with a simple constitution, by controlling the titled device so that a signal corresponding to an input signal from a signal generating means is synchronized with a reference period signal. CONSTITUTION:A phase comparator 16 compares the phase of a turning signal corresponding to the turning phase of a recording disc 7 which is outputted from a rotation detector 18 with that of a vertical synchronizing signal from a vertical synchronizing signal separating circuit 15 and the output of the comparator 16 controls a motor 12. The output of a light detector 9 is inputted to a reproducing signal processing circuit 27 and demodulated. A phase comparator 26 compares the phase of an output from a horizontal synchronizing signal separating circuit 28 with that of a signal from a voltage controlling oscillator 24 and the output signal of the phase comparator 26 is transmitted to a switch 29, a pull-in detecting circuit 30 and a control circuit 31. The time axis is compensated by a control loop consisting of the phase comparator 26, the control circuit 31, a composing circuit 22, a phase compensating circuit 23, and the voltage controlling oscillator 24 and a control loop consisting of the phase comparator 26, the switch 29, a phase compensating circuit 32, a driving circuit 33, an element 10, the reproducing signal processing circuit 27, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for correcting a time axis fluctuation component of a reproduced signal used in a reproduction apparatus or the like that reproduces a signal from a record carrier.

A suitable device to which the present invention is applied is an optical still image recording/reproducing device.

An optical still image recording/reproducing device uses a first rotor to rotate a disc-shaped record carrier (hereinafter referred to as a recording disc) at a predetermined number of revolutions (for example, 1.800t, p, m in the case of the NTSC system). a moving means for recording signals on the recording disk and a conversion means for reproducing the signals recorded on the recording disk; ), a reproduction synchronization signal detection means for extracting an image synchronization signal (for example, a horizontal synchronization signal) from the reproduction signal, and a conversion means such that the scanning position of the conversion means is always located on the track. It has a traverse kingi control means for controlling the rotation speed, and a transport means for transporting the entire or a part of the converting means in the radial direction of the recording disk.

The conversion means in the apparatus described in 1-2 includes an optical system for converging and irradiating a light beam generated from a light source such as a semiconductor laser onto the recording disk, and an optical system for detecting reflected light from the recording disk. The scanning position of the converting means means the position of the light beam irradiating the recording disk.

The above device is configured so that one image (one frame) is recorded on one concentric circle of the recording disk, and a large number of images can be filed. One important function is to search for a desired image from among images, and this search is strongly required to be fast and stable.

The time required for a search (search time) is the time it takes for a desired image to be played from the time the search is started.
In the above-mentioned apparatus, the reproduced signal includes time axis fluctuations, and this is the time required until the time axis fluctuations are corrected and an accurate image signal is reproduced.

Time axis fluctuations occur because the relative speed between the recording disk and the conversion means when recording a signal is different from that when reproducing the signal, and mainly due to eccentricity caused by the installation of the recording disk or the eccentricity caused by the rotation of the recording disk. This is caused by uneven rotation of the moving means.

Furthermore, the signals recorded on the recording disk are not recorded in exactly the same state, for example, there may be uneven rotation of the first moving means, or differences between the reference synchronization signal for rotating the first moving means and the recording signal. Due to a phase shift or device compatibility, the synchronization signals are not recorded in a consistent manner in the radial direction of the recording disk (hereinafter this will be referred to as H shift). For example, when recording a signal from a video tape recorder (hereinafter referred to as a VTR) that performs intermittent recording, the first moving means cannot be rotated by a reproduction synchronization signal of the VTR. In such a case, the VTR and the first moving means are operated with the same reference synchronization signal to record the reproduction signal of the VTR on the recording disk. VTR
The playback signal itself includes time axis fluctuations, and the constant phase shift between the reference synchronization signal and the VTR playback synchronization signal varies greatly depending on the device, recording and playback conditions, etc.
~2H (H is the period of the horizontal synchronizing signal, and in the case of the N'rSC method, it is 636 μm) in some cases. Therefore, signals recorded on a recording disk may be recorded with a constant H deviation of about 2H between one track and the adjacent track. When trying to correct the constant H deviation of 2H using the second moving means, the NTS
In the case of the C method, the light beam on the recording disk must be moved approximately 2600 μm at a position with a diameter of 200 mm on the recording disk.

However, it is extremely difficult to move the light beam on the recording disk by 2600 μm due to problems with the optical system such as the effective diameter of the converging lens or mechanical problems with the second moving means.

Regarding how time axis fluctuations have been corrected in the past, since time axis fluctuations cannot be corrected only by the second moving means, a reference synchronization signal and a reproduction synchronization signal from the recording disk are used. By comparing the phase of The time axis fluctuations were corrected using both means of transportation. At this time, among the time axis fluctuation components, the low frequency component is corrected by the first moving means,
The configuration is such that high frequency components are corrected by the second moving means, and when correcting time axis fluctuations, first the signal from the phase comparing means is In addition to the first moving means, the signal from the phase comparison means is added to the second moving means after the first moving means becomes stable.

The disadvantage of the conventional example is that when correcting time axis fluctuations is performed, the responsiveness of the first moving means is poor, so it takes time to pull in the control system, which increases the search time. In addition, the control system has a complicated mechanism and is expensive in order to avoid being affected by the dynamic balance of the recording disk, wind damage, load on the motor rotating shaft, vibration of the device, etc. When the control system is pulled in at a high speed, the control system becomes unstable, and for this reason, various complicated circuits have to be added.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide a time axis correction device that has a simple configuration and can perform fast and stable control system pull-in. a converting means for reproducing a signal; a first moving means for relatively moving the scanning position of the record carrier and the converting means in the trunk direction; and a first moving means for moving the scanning position of the record carrier and the converting means relatively in the track direction. a second moving means for moving the object over a narrow range, a first control means for controlling the first moving means to be driven in synchronization with a reference synchronization signal, and a regeneration means for the conversion. reproduction synchronization signal detection means for detecting a synchronization signal representing the relative position of the recording carrier and the scanning position of the conversion means from the signal; signal generation means for generating a signal with a frequency corresponding to the input signal; a second control means for controlling the signal of the generation means to be synchronized with the reference synchronization signal; a phase comparison means for comparing the phases of the signal of the reproduction synchronization signal detection means and the signal of the signal generation means; and a phase comparison means. a third control means for adding the signal to the control system of the second control means and controlling the phase of the signal of the signal generation means according to the signal of the phase comparison means; and a fourth control means for controlling the moving means of the first moving means, and is intended to correct the time axis fluctuation without using the first moving means.

The present invention corrects time axis fluctuations of low frequency components among time axis fluctuations by a third control means, and corrects time axis fluctuations of high frequency components that are not corrected by the third control means using a fourth control means. Therefore, the time axis fluctuations actually corrected are only those corrected by the fourth control means, and the reference synchronization signal and the reproduction signal have time axis fluctuations of low frequency components. There is.

However, with recording methods such as the low frequency conversion method or Ben'J nodochroma method, which are generally known as recording and playback signal processing methods for color video signals, there is almost no effect on the image due to time axis fluctuations in low frequency components. . The low-frequency conversion method is, for example, converting a 358 MHz color signal to 630 MHz.
It is a method of recording by converting it to a low frequency such as KHz and mixing it with an FM modulated luminance signal. For example, the perinodochroma method is a method that converts the signal to a low frequency such as KHz and records it by mixing it with an FM-modulated luminance signal.
This method converts the signal to a low frequency such as FM, modulates it together with the luminance signal, and records it.

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the same numbers will be used to describe the same parts in the drawings.

FIG. 1 shows an embodiment of the present invention. To explain the outline of the device, a light beam 2 generated from a light source 1 such as a semiconductor laser, etc.
is made into parallel light by a coupling lens 3, passes through a beam splitter 4, is reflected by a reflecting mirror 5, and is converged onto a recording disk 7 by a converging lens 6. Record disk 7
The reflected light 8 passes through the converging lens 6 again, is reflected by the reflection@6 and the beam splitter 4, and is irradiated onto the photodetector 9. The converging lens 6 is the driving element 1o
The drive element 10 is configured to scan the light beam in the track direction by moving the converging lens 6 in the track direction on the recording disk 7.

The optical system and element 10 are attached to a transfer table 11 and configured to be able to move in the radial direction of the recording disk 7 together with the transfer table 11.0 Light converged on the recording disk 7 Beam 2 is focused and controlled so that the beam diameter is always constant.
Further, tracking control is performed so that the light beam 2 is always positioned above the trunk on the recording disk 7, but since this is not directly related to the present invention, a detailed description thereof will be omitted.

The recording disk 7 is attached to a rotating shaft 13 of a motor 12, and the motor 12 rotates [η] in synchronization with a reference synchronization signal.

To explain the rotation control of the motor 12, the vertical synchronous signal U separation circuit 1 is
A phase comparator 16 extracts a vertical synchronizing signal through a signal generator 5, and compares the phase of a signal obtained by dividing this vertical synchronizing signal by 1/2 with a rotation signal corresponding to the rotational phase of the recording disk 7 from a rotation detector 18. 11 The signal from the phase comparator 16 is applied to the motor 12 via the motor drive circuit 17 to control the motor 12 (this control loop is
is called the control loop. ]. A mark is placed on the recording disk 7, which is detected by a rotation detector 18 (for example, a photocoupler).
, and one rotation signal is obtained per rotation. Therefore, the signal obtained by dividing the vertical synchronization signal into 1/2 and the rotation detector 1
Since the motor 12 is rotated by comparing the phase with the rotation signal of 8 by the phase comparator 16, the motor 12 and the recording disk 7
is controlled to rotate in synchronization with the signal from the composite signal generating circuit 14.

Correction of time axis fluctuation will be explained. A part of the composite signal from the composite signal generation circuit 14 is input to the horizontal synchronization signal separation circuit 19 for extracting the horizontal synchronization signal, and the output signal of the horizontal synchronization signal separation circuit 19 is passed to the frequency dividing circuit 2o to 1/N. (N is an integer greater than or equal to 1).

21 is a phase comparator, 22 is a combining circuit, 23 is a phase compensation circuit, 24 is a voltage controlled oscillator, and 26 is a frequency dividing circuit that divides the input signal into 17N. Phase comparator 21 is frequency dividing circuit 2
0 and the phase of the signal from the frequency dividing circuit 26 are compared, and a signal corresponding to the phase difference is transmitted to the combining circuit 22.

The output signal of the combining circuit 22 is input to the voltage controlled oscillator 24 via the phase compensation circuit 23, and the voltage controlled oscillator 2
4 oscillates at a frequency according to the input signal. The signal of this voltage controlled oscillator 24 is input to a frequency dividing circuit 25 and a phase comparator 26.

The output of the photodetector 9 is input to a reproduced signal processing circuit 27, where it is demodulated into an image signal.

The horizontal synchronization signal separation circuit 28 extracts the reproduced horizontal synchronization signal from the signal of the reproduction signal processing circuit 27 and inputs this signal to the phase comparator 26. The phase comparator 26 compares the phases of the output signal of the horizontal synchronizing signal separation circuit 28 and the signal of the voltage controlled oscillator 24, and outputs a signal corresponding to the phase difference.

The output signal of the phase comparator 26 is sent to the switch 29 . The signal is transmitted to the pull-in detection circuit 3o and the control circuit 31. After a desired track is searched, a time axis correction command signal is inputted to the input terminal A to correct the time axis fluctuation, and the input terminal A is connected to the pull-in detection circuit 3.
0 and the control circuit 31, the synthesis circuit 22 synthesizes the output signal of the phase comparator 21 and the output signal of the control circuit 31, and transmits this signal to the phase compensation circuit 23. The signal from the pull-in detection circuit 3o is input to the input terminal for opening and closing the switch 29 and to the control circuit 31, and the signal from the phase comparator 26 is transmitted to the phase compensation circuit 32 via the switch 29, and the signal is transmitted to the phase compensation circuit 32 for phase compensation. The signal of circuit 32 is connected to element 10
The signal is transmitted to the element 10 via a drive circuit 33 for driving the signal.

Although the pull-in detection circuit 30 and the control circuit 31 will be described in detail later, the pull-in detection circuit 30 determines whether the signal of the phase comparator 2e falls within a certain value after the time axis correction command signal is input to the input terminal A. When the time axis correction command signal is input to the input terminal A, the control circuit 31 transmits the signal including the high frequency component of the phase comparator 26 to the synthesis circuit 22, and detects the pull-in. circuit 30
The configuration is such that only the low frequency component of the signal 26 from the phase comparator 2e is transmitted to the combining circuit 22 by the signal .

When the time axis correction command signal is not input to the input terminal A, the phase compensation circuit 2 is set so that the output of the control circuit 31 becomes zero.
3. The voltage controlled oscillator 24 and the frequency dividing circuit 26 constitute a second control loop, and the signal of the voltage controlled oscillator 24 outputs a signal that is synchronized with the output signal of the horizontal synchronization signal separation circuit 19 and has the same frequency. The phase compensation circuit 23 is for compensating the phase of the control system.

When the time axis correction command signal is input to the input terminal A, the signal of the phase comparator 26 is transmitted to the synthesis circuit 22 including the high frequency component via the control circuit 31f.

Phase comparator 26. The control circuit 312, the synthesis circuit 22, the phase compensation circuit 23, and the voltage controlled oscillator 24 constitute a third control loop, and the voltage controlled oscillator 24 is connected to the phase comparator 26.
The phase of the output signal is controlled according to the signal. Input end A
Immediately after the time axis correction command signal is manually inputted, the control circuit 31 instantaneously transfers the signal including the high frequency component of the signal from the phase comparator 26 to the horizontal synchronization signal separation circuit 22. The phases of the signal of the voltage controlled oscillator 24 and the signal of the voltage controlled oscillator 24 are controlled to have a predetermined relationship. When the phases of the signal of the horizontal synchronizing signal separation circuit 28 and the signal of the voltage controlled oscillator 24 are controlled to have a predetermined relationship, the pull-in detection circuit 30 short-circuits the switch 29, and the control circuit 31 changes the phase of the signal of the phase comparator 26. Of these, only the low frequency component is transmitted to the synthesis circuit 22, and the phase of the voltage controlled oscillator 24 is controlled according to the low frequency component of the signal from the phase comparator 26. switch 29
is shorted, the signal of phase comparator 26 is switched to switch 29
, phase compensation circuit 32. The light is transmitted to the element 10 via the drive circuit 33, and the element 10 moves the converging lens 6 in the track direction on the recording disk T, thereby moving the light beam 2 converged on the recording disk 7 in the track direction. Phase comparator 26. Switch 292 Phase compensation circuit 32. Drive circuit 33° element 10. The optical system including the photodetector 9, the reproduction signal processing circuit 27, and the horizontal synchronization signal separation circuit 28 constitute a fourth control loop. The phase compensation circuit is for compensating the phase of the fourth control system.

The time axis correction device of the present invention is the second one. It is composed of a third and a fourth control loop, and these three control loops are interrelated.

The signal of the voltage controlled oscillator 24 in a state where time axis correction has not been performed is synchronized with the signal of the horizontal synchronization signal separation circuit 19 by the second control loop. Therefore, although the signals from the horizontal synchronization separation circuit 28 and the voltage controlled oscillator 24 have a phase difference, they are very close in frequency.
When the time axis correction command signal is input to the A terminal, the third control loop pulls in faster and more stably.

After the third control loop retracts, retraction detection [-
1 path 30, the control circuit 31 operates to pass only the low frequency component of the signal from the phase comparator 26. In this state, the loop gain in the low frequency region of the third control loop is The loop gain is configured to be larger than the loop gain in the low frequency region of the second control loop. Therefore, the voltage controlled oscillator 24 is mainly controlled by the third control loop in the low frequency range, and controlled by the second control loop in the high frequency range. Even if the voltage controlled oscillator 24 itself has high frequency fluctuations, it generates an extremely stable signal because it is controlled by the second control loop.

In the present invention, the signal of the voltage controlled oscillator 24 is an extremely important signal for measuring time axis fluctuations, and therefore the role of the second control loop is also important.

After the third control loop has pulled in, the fourth control loop is operated by the pull-in detection circuit 3o to correct the time axis fluctuation, but in the present invention, the loop of the third control loop is The gain is configured to be larger than the loop gain of the fourth control loop. Therefore, in the time axis fluctuations of the signals of the horizontal synchronization signal separation circuits 19 and 28, the low frequency components are mainly
The high frequency components are mainly controlled by the fourth control loop.
control loop. As described above, only the 11111111 fourth control loop actually corrects the time axis fluctuation.

The pull-in detection circuit 3o will be explained with reference to FIG.

The pull-in detection circuit 3o is composed of comparators 41 and 42, an inversion circuit 43, and AND circuits 44 and 45. The relationship between FIG. 1 and FIG. 2 will be explained. The input terminal A is the input terminal A shown in FIG. 1, and the time axis correction command signal is inputted, the signal of the phase comparator 26 is inputted to the input terminal B, and the signal of the output terminal C is inputted to the switch 29 and the control signal. They are respectively input to the circuit 31. Input terminal B is connected to comparators 41 and 4
It is connected to the input terminal of 2. Comparators 41 and 4
Comparators 2 each have different threshold levels, and are configured so that when a signal greater than the threshold level is input, the output becomes HIGH. The threshold level of the comparator 41 is set lower than that of the comparator 42.

The signal of the comparator 42 is input to an inverting circuit 43 for inverting the input signal, and the signal of the comparator 41 and the signal of the inverting circuit 43 are input to an AND circuit 44, respectively. The signal of the AND circuit 44 becomes HIGH when the signal at the input terminal B is higher than the threshold level of the comparator 41 and lower than the threshold level of the comparator 42. Input terminal A and AND circuit 4
The four signals are input to an AND circuit 46, respectively.

The signal at the output terminal C of the AND circuit 46 is such that the input terminal A is HIGH.
HIGH when the signal from the AND circuit 44 is HIGH.
H, short-circuiting the switch 29 in FIG. 1 and operating the control circuit 31 at the same time. As mentioned above, the pull-in detection circuit detects that the signal of the phase comparator 2e falls within a certain range, and then operates the fourth control loop, so the element 10 does not swing significantly and the fourth control loop is activated. The control loop No. 4 operates stably. Particularly in optical recording and reproducing devices, if the element 10 swings significantly, the focusing control or tracking control may be lost, but according to the present invention, the element 10 does not swing significantly, so the focusing control and tracking control are extremely stable. Operate.

The control circuit 31 will be explained in conjunction with FIG. To explain the relationship between FIG. 1 and FIG. 3, input terminal A is the input terminal A shown in FIG.
The signal from the pull-in detection circuit 3° is input to K, the signal from the phase comparator 26 is input to the input terminal, and the signal from the output terminal E is input to the combining circuit 22. R1-R4 are fixed resistors, C1 is a capacitor, 51 and 52 are differential amplifiers with large amplification factors and input impedances, 53 and 64 are switches, 66 is a constant voltage circuit that generates a constant voltage signal, and 66 and 67 are constant voltage circuits that generate constant voltage signals. This is an inverting circuit that inverts the input signal. The input end is connected to one end of the fixed resistor R1, and the other end of the fixed resistor R1 is connected to the inverting input end of the differential amplifier 51. The inverting input terminal and output terminal of the differential amplifier 610 are connected through a fixed resistor R2, and the signal from the constant voltage circuit 66 is input to the non-inverting input terminal of the differential amplifier 61. The output terminal of the differential amplifier 61 and the inverting input terminal of the differential amplifier 52 are connected via a fixed resistor R3, and the output terminal of the differential amplifier 51 is input to a switch 63, and the output terminal of the switch 53 is fixed. It is connected to one end of the resistor R4, and the other end of the fixed resistor R4 is connected to the differential amplifier 6.
The inverting input terminal and output terminal of the 0 differential amplifier 62 connected to the inverting input terminal of the switch 64 are connected via the capacitor C1, and the inverting input terminal of the differential amplifier 62 is further connected to the output terminal of the switch 64. The input terminal of the switch 64 is connected to the output terminal of the differential amplifier 62. Differential amplifier 52
The non-inverting input terminal of is set to zero potential. The signal at the input terminal A is input to an inverting circuit 57, and the signal from the inverting circuit 57 is input to an input terminal for opening and closing the switch 54. Further, the signal at the input terminal C is input to the inverting circuit 66, and the signal from the inverting circuit 56 is input to the input terminal for operating the switch 63 to open and close.

When time axis fluctuation correction is not performed, input terminal A
and C signals are LOW, and switches 63 and 6
4 is shorted. Therefore, the output of the differential amplifier 52 is at zero potential. When the signal at the input terminal A becomes HIGH in order to correct the time axis fluctuation, the switch 54 is opened and the third control loop is activated. When the third control loop is drawn in, the signal at the input terminal C becomes HIGH, so the signal at the inverting circuit 56 becomes LOW, and the switch 63 becomes open.

When the switch 64 is shorted, the output of the differential amplifier 62 is at zero potential, and the time differential amplifier 52 with the switch 64 open operates as an integrating circuit and outputs a signal obtained by integrating the signal of the differential amplifier 61. .

When the switch 64 is open and the switch 63 is short-circuited, the differential amplifier 62 uses the parallel resistance value (R
3 x R4/(R3+R4) resistance value) and capacitor 0
Operates as a quick-response integrating circuit with a capacitance value of 1,
When the switches 53 and 54 are open, the differential amplifier 62
operates as an integrating circuit with slow response due to the resistance value of the fixed resistor R3 and the capacitance value of the capacitor C1. Therefore, the response of the third control loop is fast from the time when the third control loop operates until the third control loop is drawn in, and the third control loop is drawn in at high speed. Further, after the third control loop is inputted, the third control loop becomes a control loop with slow response. In a steady state where the third control loop is drawn in and stable, the control system includes an integrating circuit, so the lower the frequency, the higher the loop gain of the control system, and the output of the differential amplifier 61 is It operates so that the potential is zero on average. At this time, the level of the input terminal, that is, the signal of the phase comparator 26 is
The third control loop will be most stable if it is set to approximately the middle value of the output range. If the signal from the constant voltage circuit 66 is applied in this way, and the median value of the output range of the phase comparator 26 is approximately zero potential, then the constant voltage circuit 65
The non-inverting input terminal of the differential amplifier 61 can be brought to zero potential without using the differential amplifier 61.

In FIG. 3, switch 64 is removed and differential amplifier 5
A switch is provided between the output terminal of the differential amplifier 62 and the output terminal E, and when correction of time axis fluctuation is to be performed, this switch is short-circuited and the signal of the differential amplifier 62 is transmitted to the output terminal E via the switch. When configured, the differential amplifier 52 always operates as an integrating circuit. With this configuration, when the switch is short-circuited and the third control loop is operated, an extremely large signal may be transmitted to the output terminal E, making the pull-in of the third control loop extremely unstable.

Therefore, as shown in FIG. 3, when the third control loop is not operating, the output of the differential amplifier 62 is at zero potential, and when the third control loop starts operating, the output of the differential amplifier 62 is zero. If the signal from the differential amplifier 61 is integrated starting from the potential, the third control loop will be extremely stable.

In FIG. 1, the opening and closing of the switch 29 is controlled by the phase comparator 26.
This is done by detecting that the output of the signal has converged within a certain range, but it is also possible to close the switch 29 after a certain period of time after the time axis correction command signal is input to the input terminal A. good. Similarly, the limiting circuit 31 is configured to transmit only the low frequency component of the signal from the phase comparator 26 to the combining circuit 22 after a certain period of time from when the time axis correction command signal is input to the input terminal A. You may.

One embodiment of the phase comparator 26 shown in FIG. 1 will be described with reference to FIG. 4.

To explain the relationship between FIG. 1 and FIG. 4, the signal from the horizontal synchronizing signal separation circuit 28 is input to the input terminal F, the signal from the voltage controlled oscillator 24 is input to the input terminal G, and the output terminal I is connected to the switch. 29. It is connected to the respective input terminals of the pull-in detection circuit 30 and the control circuit 31. 61 is a constant voltage circuit that generates a constant voltage, 62 is an inversion circuit for inverting the signal at the input terminal G, 63, 64, 65 and 69 are switches, and 66, 67 and 68 have a large amplification factor and input impedance. In the differential amplifier, R5 is a fixed resistor, C2, C3, and C4 are capacitors, and 70 is a monostable multipipulator (hereinafter referred to as monomulti) that operates at the rising edge of the signal at the input terminal F. The output of the constant voltage circuit 61 is input to the switch 63, the output terminal of the switch 63 and the inverting input terminal of the differential amplifier 66 are connected via a fixed resistor R6, and the inverting input terminal of the differential amplifier 66 is connected to the switch 63. 64
The output ends of the differential amplifiers 66 are connected to the input ends of the switches 64, respectively. The output terminal and the inverting input terminal of the differential amplifier 66 are connected via a godensor c2, and the non-inverting input terminals of the differential amplifier 66 are set at one potential. The output end of the differential amplifier 66 is connected to the input end of the switch 66, the output end of the switch 66 is connected to the non-inverting input end of the differential amplifier 67, and the non-inverting input end of the differential amplifier 67 is connected to one end of the capacitor 03. The other end of the capacitor 03 is set to zero potential. Differential amplifier 6
The inverting input terminal and output terminal of the differential amplifier 67 are connected to each other, and the output terminal of the differential amplifier 67 is connected to the input terminal of the switch 69.
The output terminal of the differential amplifier 68 is connected to the non-inverting input terminal of the differential amplifier 68, and the non-inverting input terminal of the differential amplifier 68 is connected to one end of the capacitor 04. The other end of the capacitor 04 is set to zero potential, and the inverting input terminal of the differential amplifier 68 and its output terminal I are connected. The input terminal G is an input terminal for operating the opening/closing of the switch 63 and the input terminal of the inverting circuit 62, the output terminal of the inverting circuit 62 is an input terminal for operating the opening/closing of the switch 64, and the input terminal F is the input terminal for operating the opening/closing of the switch 65. At the input end for operating the opening/closing and the input end of the mono multi 7°,
The Q output terminals of the monomulti To are connected to the input terminals for opening and closing the switch 69, respectively. To explain the operation of the differential amplifiers 66, 67, and 68, when the switch 63 is short-circuited and the switch 64 is open, the differential amplifier 66 operates as an integrating circuit with the fixed resistor R6 and the capacitor 02, and the constant voltage circuit 61 operates as an integrating circuit. A signal obtained by integrating the signal is output, but the output range of the differential amplifier 66 is limited, and a signal exceeding this output range is not output, but is clipped to a constant voltage. Further, the output of the differential amplifier 66 becomes zero potential when the switch 63 is open and the switch 64 is short-circuited.

The differential amplifier 67 outputs the same signal as the signal of the differential amplifier 66 when the switch 66 is short-circuited, and when the switch 66 is open, it holds the signal of the differential amplifier 66 immediately before the switch 66 was opened ( hold). The differential amplifier 68 operates similarly to the differential amplifier 67, and the switch 6
When the switch 9 is short-circuited, the same signal as that of the differential amplifier 67 is outputted, and when the switch 69 is open, the signal of the differential amplifier 67 immediately before the switch 69 is opened continues to be held.

This will be explained along with the timing chart shown in the figure. Figure 5 is the third
This shows a state in which the signal of the phase comparator 26 is kept at a certain value by the control loop of , where the waveform (,) is the signal waveform of the input terminal G, and the waveform (b) is the output waveform of the differential amplifier 66. , waveform (C) is the signal waveform of input terminal F, waveform (d)
is the output waveform of the differential amplifier 67, waveform (e) is the output waveform of the monomulti 70, and waveform (f) is the output waveform of the differential amplifier 68. Monomulti 70 in Figure 4. switch 6
9. If the output of the differential amplifier 67 is regenerated and sampled and held by the differential amplifier 68 and the capacitor 02, the waveform (f) shown in FIG. Extremely accurate phase comparison can be performed.

Although the phase comparator 21 can have the same structure as the phase comparator 26 shown in FIG. 4, it will be explained in conjunction with FIG. 6.

To explain the relationship between FIG. 1 and FIG. 6, the signal of the frequency divider circuit 26 is input to the input terminal
The output terminal is connected to the input terminal of the synthesis circuit 22. 81 is a constant voltage circuit that generates a constant voltage; 82 is an inverting circuit that inverts the signal at the input terminal;
83, 84° 86 and 89 are switches, 86.87 and 8e are differential amplifiers with high amplification factor and input impedance, fixed resistors are connected, C5, C6 and C7 are capacitors, and 9o is a signal riser at input terminal I. It is a monomulti that works on the downhill. The output of the constant voltage circuit 81 is input to a switch 83, and the output terminal of the switch 83 and the inverting input terminal of the differential amplifier 86 are connected via a fixed resistor R6. : The output terminal of the switch 84 and the output terminal of the differential amplifier 86 are connected to the input terminal of the switch 84, respectively.

The output terminal and inverting input terminal of the differential amplifier 86 are connected to capacitor 0.
6, and the non-inverting input terminal of the differential amplifier 86 is set to zero potential. The output terminal of the differential amplifier 86 is connected to the input terminal of the switch 85, the output terminal of the switch 86 is connected to the non-inverting input terminal of the differential amplifier 87, and the non-inverting input terminal of the differential amplifier 87 is connected to one end of the capacitor ff1-06. The other end of the capacitor C6 is set to zero potential. The output terminal of the differential amplifier 87 and the inverting input terminal are connected to each other. A non-inverting input terminal of dynamic amplifier 8B is connected to one end of capacitor C7. The other end of the capacitor 07 is set to zero potential, and the inverting input end of the differential amplifier 88 and its output end are connected. The input terminal is an input terminal for opening and closing the switch 83 and the input terminal of the inverting circuit 830, and the output terminal of the inverting circuit 83 is the switch 84.
The input terminal ■ is the input terminal for operating the opening and closing of the switch 85 and the monomulti 90
At the 0Å power end, the Q output end of the mono multi 90 is the switch 89.
are connected to the input terminals for operating the opening/closing operation. Differential amplifiers 86 , 87 .

The operation of 88 is similar to that of differential amplifiers 86, 67, and 68 of FIG. 4, and will not be described in detail.

The operation of the phase comparator 21 shown in FIG. 6 will be explained with reference to the timing chart shown in FIG. 7. FIG. 7 is a waveform diagram when the frequency dividing circuits 2o and 25 are 1/3 frequency dividing circuits, where the waveform (q) is the signal waveform of the horizontal synchronization signal separation circuit 19, and the waveform (h) is the signal waveform of the horizontal synchronization signal separation circuit 19. The signal waveform of the frequency dividing circuit 20, waveform (i) is the signal waveform of the differential amplifier 86, the waveform (i) is the signal waveform of the voltage controlled oscillator 24, and the waveform (k) is the signal waveform of the frequency dividing circuit 25, waveform (gradient). is the signal waveform of the differential amplifier 87, waveform (E)
is the signal waveform of the monomulti 9o, and waveform (P) is the signal waveform of the differential amplifier 88.

The waveform (q) is a signal with information on the rising edge,
The waveform (h) is a signal obtained by dividing the waveform (q) into ⅓.

Waveform (i) increases at a predetermined slope from the rising edge of waveform (h), and reaches zero potential at the falling edge of waveform (d).

Waveform (1) has information on the rising edge, and waveform (k) has information on the falling edge. Waveform (k) is waveform (i)
is divided into 1/3. The waveform (Il,) is a signal obtained by sampling and holding the waveform (i) with the waveform (k), and the LOW period of the waveform (k) is the hold period. The waveform (p) is a signal obtained by sampling and holding a waveform (force into a waveform).

Second. When the third and fourth control loops are operating, the phase of the signal (waveform (j)) of the voltage controlled oscillator 24 changes according to the low frequency component of the time axis fluctuation, as described above. Therefore, the phase of the signal (waveform (k)) of the frequency dividing circuit 26 changes according to the phase of the signal of the voltage controlled oscillator 24, and the output (waveform (force)) of the differential amplifier 87 also changes. The symbol it indicates the period during which the waveform (i) increases, and the period t is also the controllable range of the second control loop.In other words, the waveform (i) shown in FIG. From the state of , the waveform (k) is
moves and exceeds the period t, the second control loop is disturbed. Therefore, if the phase of the waveform (k) changes beyond the period t, the time axis fluctuation cannot be corrected accurately. Frequency divider circuit 2
.degree. and 26 serve to expand the controllable range of the second control loop. , the second control loop will not be disturbed if the frequency dividing ratios of the frequency dividing circuits 2o and 25 are set to be wider than the range of time axis fluctuation of the device. The larger N mentioned above, the wider the controllable range of the second control loop becomes. However, since the frequency of the frequency divider circuit 26, that is, the sampling frequency becomes lower, the responsiveness and control accuracy of the second control loop become smaller. decreases. Therefore, it is desirable to avoid making Ni larger than necessary. Also, if there is little variation in the time axis, it can be set to N-1, which means that
This is the same as omitting the frequency dividing circuits 2o and 25.

The present invention is in no way limited to the embodiments described above.

For example, in FIG. 1, the signal from the phase comparator 21 and the signal from the control circuit 31 are combined by the combining circuit 22, and the voltage-controlled oscillator 24 is controlled by the signal from the combining circuit 22, but the difference shown in FIG. The signal from the dynamic amplifier 86 and the signal from the control circuit 31 may be combined, and the combined signal may be input to the switch 85 to control the voltage controlled oscillator 24.

For example, instead of the horizontal synchronization signal included in the image signal, a signal with a constant frequency for correcting time axis fluctuations is recorded, and this signal is used to correct the time axis fluctuations that occur during playback. It may be configured as follows.

In this case, the constant frequency is preferably a signal that is an integral multiple of the rotational speed of the motor 12.

It goes without saying that the present invention can also be applied to devices that reproduce signals from recording disks with spiral tracks, such as magnetic recording and reproducing devices, magneto-optical recording and reproducing devices, and capacitive reproducing devices. etc. can also be applied.

The present invention has been described in detail above, but if the present invention is applied to a device, it is possible to correct time axis fluctuations with a simple configuration. Conventionally, time axis fluctuations of low frequency components were corrected using motors, etc. Therefore, it took a very long time to pull in the control system, but since the present invention performs the pull-in in the circuit using the second control loop described above, it is possible to pull in the control system extremely quickly and stably. is extremely large.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a time axis correction device in one embodiment of the present invention, Fig. 2 is a block diagram showing one embodiment of a pull-in detection circuit, and Fig. 3 is an electrical connection diagram showing one embodiment of a control circuit. 4 is an electrical wiring diagram showing one embodiment of the phase comparator 26, FIG. 6 is a timing diagram for explaining the operation of the phase comparator shown in this figure, and FIG. 6 is a phase comparison diagram. FIG. 7 is a block diagram showing one embodiment of the phase comparator, and FIG. 7 is a timing diagram for explaining the operation of the phase comparator shown in FIG. 6. 6... Converging lens, 7... Recording disk,
9...Photodetector, 1o...Drive element,
12... Motor, 14... Composite signal generation circuit, 15... Vertical synchronization signal separation circuit, 16, 21° 26... Phase comparator, 17・
...Drive circuit, 19.27...Horizontal synchronization signal separation circuit, 20, 26...Broadcast circuit, 2
2... Synthesis circuit, 23.32... Phase compensation circuit, 24... Voltage controlled oscillator, 29...
. . . Switch circuit, 30 . . . Pull-in detection circuit, 31 . . . Control circuit, 33 .......... Drive circuit. Name of agent: Patent attorney Toshi Nakao Haga 1 person 11
Figure 1 * z @ s. Figure 3 1 Chicken Figure 4? b Fig. 5 ((/U) to WA6 Fig. 7 no't-i,)-X

Claims (1)

Scope of Claims: (1) A record carrier having a track on which a signal is recorded, a converting means for reproducing the signal from the record carrier, and a trunk whose scanning positions are relative to the record carrier and the converting means. a first moving means for moving the record carrier and the converting means in a relatively narrow range in the track direction; a first control means for controlling the drive so that it is driven in synchronization with a reference synchronization signal; and a synchronization device that indicates the relative position between the scanning position of the conversion means and the record carrier based on a reproduction signal from the conversion means. reproduction synchronization signal detection means for detecting the signal; signal generation means for generating a signal with a frequency corresponding to the input signal; and control so that the signal of the signal generation means is synchronized with the reference synchronization signal. a second control means for controlling the signal of the phase comparison means, a phase comparison means for comparing the phases of the signal of the reproduction synchronization signal detection means and the signal of the signal generation means, and control of the signal of the phase comparison means of the second control means. In addition to the system, a third control means for controlling the phase of the signal of the signal generation means according to the signal of the phase comparison means;
and fourth control means for controlling the second moving means in accordance with a signal from the phase comparison means. (2) When starting correction of time axis fluctuations, the fourth control means is operated after the third control means is operated. Time axis correction device. (3) When operating the third control means, the response of the control system of the third control means is made high to cause the control system to be drawn in, and then the response of the control system is reduced, and the response of the control system of the third control means is reduced. 2. The time axis correction device according to claim 1, wherein the time axis correction device is configured to control the phase of the signal of the signal generating means in accordance with the low wave number component of the signal. (4) In the low frequency region, the loop gain of the control system of the third control means is made larger than the loop gain of the control system of the second control means. Axis correction device. (6) In the low wavenumber region, the loop gain of the control system of the third control means is made larger than the loop gain of the control system of the fourth control means. Time axis correction device. (6) The control system of the third control means is configured to include an integrating circuit, and the lower the frequency, the higher the loop gain of the control system. (7) The time base correction device according to claim 6, characterized in that the time base correction device is configured to operate as an integrating circuit after operating the third control means. (8) Second control to compare the phases of the reference synchronization signal and a signal obtained by frequency-dividing the signal of the signal generating means, and control the signal of the signal generating means according to the compared signal. The time axis correction device according to claim 1, characterized in that the device comprises means.