JPS58165446A - Error notice circuit - Google Patents

Abstract

PURPOSE:To inform the generation of an error to a remote station of communication without provision of special communication control steps, by inverting forcedly a frame check sequence at the transmission side if the error takes place in a reception data in an adaptor which relays and edits data. CONSTITUTION:The frame check sequence extracted from an input data buffer 1 is checked at an FSC reception circuit 6, and logical ''1'' input is inputted to an AND gate 10 through an OR gate 8 at the generation of error. Similarly, when error report 7 in a communication adaptor is received, the logical ''1'' input is inputted to an AND gate 10a. In the frame check sequence added to a transmission data, a denying input of an FSC generating circuit 9 is outputted via an insertor 12 in the inserting timing of the frame check sequence through the gate 10a and an OR gate 11, and the frame check sequence at an output data train 5 is a sequence forcedly inverted, which indicates the generation of a failure at the communication adaptor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error notification circuit for detecting an error in received data in an adapter that relays and edits data.

An example of a communication adapter according to the prior art will be described with reference to FIG.

Figure 1 shows an example of a communication adapter that converts an M-Unzaka, where 1 is an input data buffer;
2 is a conversion unit, 3 is a timing generation circuit, 4 is an input data string, and 5 is an output data string. The 0%/-ht data string 4 is generated in the timing generation circuit 5 and is input to the input buffer with a 9-tight signal. 1, is quickly converted into a converter, and is output as an output data string 1. At this time,
The round frame check etance added to the input data string 4 is not modified in any way in the converter 2, and is combined and added to the transmission data to become an output data string.

In the above-mentioned communication adapter configuration, errors that occur in the communication adapter, overrun errors, underrun errors, etc. are processed within the communication adapter, so the data that is red and white in the communication adapter is considered to be prepared by the sending side. Despite the difference, the receiver has the disadvantage that the receiver is treated as normal data with no errors.The purpose of the present invention is to eliminate the disadvantages of the communication adapter according to the prior art described above, To achieve the above-mentioned purpose, the present invention provides a communication adapter that relays and outputs data to the other party that performs the communication. The system measures frame check sequence errors in received data and errors that occur in the communication adapter (for example, overrun errors, under 2nd errors, parity errors), and if one error occurs, it checks the 7 frame check sequence of the transmitted data string. By forcibly reversing the error, the communication partner is notified of the occurrence of an error and a one-shot display is made, thereby making it possible to clarify the point of failure and improve the reliability of data communications. It is.

The present invention will be explained in detail below using the drawings.

,: Figure 2 shows an embodiment of the notification circuit 10 according to the present invention. 7 is an error report (underrun,
8 is an OR gate, 9 is a frame check sequence generation circuit 10a%b for transmission data, is an AND gate, 11 is an OR gate, and 12 is an inserter.

Note that the 1ici number, which is the same as in Figure #&1, indicates the same thing as in Figure I@1. In this XS, the frame check sequence extracted from input data buffer 1 is checked by FO8 receiving circuit 6, and when an error occurs, The logic 111'' input is input to the AND gate 10a through the OR gate 8.Similarly, if there is an error report 7 in the communication adapter, the logic 111'' is also input to the AND gate 10a.

In this case, the frame check sequence added to the transmission date and time is FC8 generation U path, -.

9's negative input □ is goo) 10as Through the OR gate 11, it is outputted through the inserter 2 at the insert timing of the frame check sequence, and the frame check and tsuku sequence in the 9 card data string 5 is forced to indicate that some abnormality has occurred in the communication adapter. It will be reversed.

In a normal state, a normal frame check sequence from the FO8 generation circuit 9 is output to the output data string 5 via the eyedog 10b, the OR gate 11, and the inserter 121.

As described above, the present invention is a general-purpose communication adapter (one that can notify the other party of communication of the occurrence of an error without providing a special retroactive value allocation procedure), which has a circuit configuration of four circuits with high efficiency. It is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a conventional communication adapter';
Figure 2 is a diagram showing the configuration of a communication adapter including a entertainment notification circuit according to a Kazumi embodiment of the present invention. t... Input data buffer 2... Variation section 5,... Timing generation circuit 4,... Reception data string &... Transmission Data string 4...FO8 receiving circuit l...Communication adapter occurrence error 8,...
・OR gate 9...FC8 generation-path 10a%b...AND gate 11...OR gate 12...Inserter

Claims (1)

[Claims] In the communication adapter that relays and edits the data to the other party, the 7-frame check sequence of the received data is damaged, the damaged data is relayed to the circuit that checks the received data, and a new 7-frame check sequence is added to the transmitted data. It has a circuit that adds a frame check sequence, and when an error occurs in the received data, the frame check sequence on the transmitting side is forcibly reversed. A prefecture notification circuit characterized by a t-a information.