JPS58164348U - low noise receiver - Google Patents

low noise receiver

Info

Publication number
JPS58164348U
JPS58164348U JP5926582U JP5926582U JPS58164348U JP S58164348 U JPS58164348 U JP S58164348U JP 5926582 U JP5926582 U JP 5926582U JP 5926582 U JP5926582 U JP 5926582U JP S58164348 U JPS58164348 U JP S58164348U
Authority
JP
Japan
Prior art keywords
low noise
noise receiver
antenna
impedance
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5926582U
Other languages
Japanese (ja)
Inventor
和彦 本城
杉浦 禎彦
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP5926582U priority Critical patent/JPS58164348U/en
Publication of JPS58164348U publication Critical patent/JPS58164348U/en
Pending legal-status Critical Current

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  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はGaAs−FETの雑音特性を説明するた゛め
の図で、第2図は本考案の実施例を説明するための図で
ある。図において4は信号源コンダクタンス、1,13
はゲート電極、3.15はソース電極、2.14はトレ
イン電極、11,21゜31はアンテナ、12,22.
32は伝送線路、27はインピーダンス変換器、16は
モノリシック構成受信増幅器。
FIG. 1 is a diagram for explaining the noise characteristics of a GaAs-FET, and FIG. 2 is a diagram for explaining an embodiment of the present invention. In the figure, 4 is the signal source conductance, 1, 13
is a gate electrode, 3.15 is a source electrode, 2.14 is a train electrode, 11, 21° 31 is an antenna, 12, 22.
32 is a transmission line, 27 is an impedance converter, and 16 is a monolithic receiving amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力雑音整合回路を持たない初段増幅トランジスタの入
力端子からアンテナ側を見込んだインピーダンスが通常
用いられる伝送系特性インピーダンス50Ω(または7
5Ω)より高いことを特徴と゛する低雑音受信装置。
The impedance looking toward the antenna from the input terminal of the first-stage amplification transistor, which does not have an input noise matching circuit, is the transmission system characteristic impedance of 50Ω (or 7Ω), which is normally used.
A low noise receiving device characterized by higher than 5Ω).
JP5926582U 1982-04-23 1982-04-23 low noise receiver Pending JPS58164348U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5926582U JPS58164348U (en) 1982-04-23 1982-04-23 low noise receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5926582U JPS58164348U (en) 1982-04-23 1982-04-23 low noise receiver

Publications (1)

Publication Number Publication Date
JPS58164348U true JPS58164348U (en) 1983-11-01

Family

ID=30069583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5926582U Pending JPS58164348U (en) 1982-04-23 1982-04-23 low noise receiver

Country Status (1)

Country Link
JP (1) JPS58164348U (en)

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