JPS58164313A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To perform high-speed operation with high precision and to realize packaging on a single semiconductor substrate by constituting a DAC wherein a weighting current source is composed of transistors (TR) in the same shape. CONSTITUTION:Current mirror circuits 23 and 24, 25 and 26, 27 and 28, and 29 and 30 are stacked successively in plural stages to divide a prescribed current successively, and current mirror circuits 31 and 32, 33 and 34, 35 and 36, 37 and 38, and 39 and 40 constitute the binary weighting current source; input digital data D1-D4 are inputted to an input terminal group 41 to turn on/off current changeover switches 42-45 and then outputted from a terminal 47 through a current sum line 46. The TRs may be in the same shape and easy to obtain precision; and no glitch is generated, high-speed operation is realized, and a wide dynamic range is obtained.

Description

[Detailed description of the invention] [Technical field of invention]-1 The present invention relates to a digital-to-analog converter.

The present invention also relates to a digital-to-analog converter that can be formed on a single semiconductor substrate and is capable of high performance and high speed operation.

[Technical background of the invention and its problems]

As an example of a conventional digital-to-analog converter (hereinafter referred to as F DAC), a current output type 4-pin DCA is used
11. Its operation consists of input digital data DI,
Dl, 03. D4 is input to the input terminal group 1 and switches the 1 contracting current changeover switches 2, 3, 4.5. On the other hand, the weighting current is determined by the resistance value 0 and the resistance value 2R, which is twice that value. 9 weights are applied to the R-2R Prada resistor circuit 6, and this current is selected from the current switches 2, 3, and 4.5, added by the current adder 11, and outputted from the terminal 12. .ζHere, ``What is the current d amount of the npn bipolar transistors 7.8, 9.10 that constitute the current source of each bit? If the ivy current value is I, then the key serial numbers 8, 9, and 10's 2 ivy current values are 8!, 4, and 21.1, respectively.In other words, due to the difference in current values, the A difference of 4 voltages is generated in the base-emitter voltage VBft between each transistor, and the electric bow causes an error in the current ratio.As is generally said, the transistor base-emitter voltage Vag d, collector 4 There is a relationship between the current IC and the following equation.

VBn = VT In (Ic/Is) −
...However, vT: Thermal voltage is: Difference in reverse saturation current of transistor ΔVB]
il is a turtle ・ΔVB1=V71n(2IC/l6)−VTln(Ic
/Is) ...-+・121=VTln2°=18 (ml/). That is, the npn bipolar transistor shown in Fig. 1? , 8, 9, and 10 are formed with transistors of the same shape, the solder level of the connecting terminals 13, 14, 15, and 16 is ts (mv) higher than the terminal 15, and the terminal 15 is 18 mv higher than the terminal 14. (mV) becomes higher 0
In this way, a difference in position of 18 (mVJ) is generated, which results in a difference in the weighted Wttllt value K11l.
? :, In order to remove the difference, weighting is applied to the backward saturated IE flow Ill which is expressed by the equation K(1). Actually, LaI3
)If the area of the transistor 10 is a person, what is the transistor of each bit? , 8, 9.10, and the area of the correction transistor F is 8mm, 4A, 2mm, respectively.
From A, M and K, the reverse saturation current ■8 is calculated by each *
8I@, 4I@, 2Bg, Ig, Is (However, L8
B) Corrected by setting the reverse saturation current of the transistor to O2). At this time, equation (2) is.

ΔVan = Vy In (2IC/2Ia) - Vyt
If a (IC/IB) = 0, the error voltage ΔV1m will not occur.However, if the area ratio of the two people is 0, then the error voltage ΔV1m will not occur.

... Setting zn-3 people (n is the number of bits) means taking the area ratio 411L<, and the maximum quantization bit (hereinafter referred to as M8B) for the large emitter area of KI, 8B. ), the larger the ratio of the M2R transistor area to the M2R transistor area (2fi-1), the larger the M2R transistor area, and the difficulty of matching the frequency characteristics, current amplification factors, etc. of transistors with different shapes. 〇 [Purpose of the invention] So, the purpose of the present invention is high -accurate and high -speed operation by configuring a DAC that is weighted with a transistor of the same shape without changing the shape of the transistor in this way. It is an object of the present invention to provide an AC that is easy to form on a fist-to-cow conductor board.

[Summary of inventions]

The present invention generates a weighted current corresponding to an input digital signal by stacking multiple stages of circuits that divide and equalize current by connecting transistors in parallel and sequentially dividing a predetermined current.This weighted current is used as the base of the transistor. The weighted current is generated in the second transistor by the base (or gate) of the transistor of pill 1 whose collector (or gate and drain) are connected, and the second transistor whose base (or gate) is connected, and the weighted current is generated in the second transistor. Digital-to-analog conversion is performed by configuring a current source, configuring a plurality of parallel IL current sources connected in series with an input current switch, and summing the weighted current corresponding to the human input digital signal. [Embroidery Example of the Invention] The present invention will be described in detail below with reference to the drawings.

As an embodiment of the DAC according to the present invention, a 4-bit DA
C is shown in FIG. The collector line of the NPN bipolar transistor is connected to the power supply voltage application terminal 21, and the base terminal 22 is connected to a predetermined voltage V to obtain a predetermined output current of the DAC.
, is applied, and % 9 is applied to the two vines of the plating transistor processing.
Connect the n9 bipolar transistor field, 24 E2 pins, connect the base of 24 transistors, and
By connecting the base and collector of one of the transistors and connecting them as a diode, a current doubler circuit is formed. From this, the 11pfi bipolar transistor 20+2) transistor current I is divided into two equal parts, and the pnp bipolar transistor 22. ! : The same current value I/2 flows through the 2B power plant. Similarly, by connecting the current transistor 1IllI, which is composed of 9nD) transistors 25 and 28, to the collector for transistor F, the same current value V4 flows through both transistors δ and 26, and therefore the current Ha to the transistor 4 degree device with 2 la one circuit! /8% IA6 for transistor 4 and 30
A current flows. Furthermore, by connecting the collector of the transistor 31 (1)01)) to the collector of the diode-connected npn) transistor 31, and configuring the transistor 31.32
◇Similarly; npn) transistors (, 34 are current mirror circuits, so a current of ``/4'' flows through transistors 34, transistors 35, 36 KaI, transistors 37... To Hu”
A6, transistor, 4DIK%IA6 flows.

That is, this results in a binary weighted current source K, and transistors 32, 34, 36 . Each on the side! , now, '/4, l/8, '/16
A current flows.

On the other hand, when the input digital data Ds, Da, Ds, and Ds are input to the input terminal group 41, the current changeover switches 42, 43, 44, and 45 become conductive or nonconductive, and the current of the weighted current source , current addition 46K
.

It is selected whether or not to flow, and the DAC output current corresponding to the digital data is output from the terminal 47.

As explained above, in the DAC according to the present invention, the pnp
Bipolar transistors and NPN bipolar transistors can all have the same shape, so they can be placed on the same semiconductor substrate.
When the transistor is constructed, there is little variation in the characteristics of the transistor, making it easy to improve accuracy. Moreover, since it is a current output, glitches do not occur, high-speed operation is possible, and a wide output voltage range (dynaelectric power range) can be obtained. Since the switch is composed of differential transistors, the I & large output voltage is % (
vcc-2VBL) book. Generally, when a %npn bipolar transistor and a PfiP bipolar transistor are formed on the same semiconductor substrate, the characteristics of the 5pnp) transistor are inferior to the Ilplm) transistor (in particular, the frequency characteristics are inferior). However, in the present invention, pop)
The transistors whine because they are all DC-powered.

9fiP) What does it mean that the speed deteriorates due to the use of transistors?

With the above explanation, 9119) Langista staff spa)
Although the base current of the transistor was ignored (that is, the current amplification factor of the transistor was set to infinity), in reality, the accuracy deteriorates due to the base current. For example, in figure 82, 5
A current mirror circuit composed of pnp transistors 24, with emitters 4 of both transistors 24
flL has the same value but on the collector side, i.e. line 4
The currents of 9 and the mallet do not have the same value ◎Specifically, the added base current of the transistor 24 is added to the collector current of the transistor and flows through the wire. Here, the current amplification factor of pnp) is βp, and a
If the machining current of the pn bipolar transistor is 1, the current 1' of S49 and the electric current ah' of the wire mallet are as follows.

II" = l/2・(1-1//,)...
...(3) Ir' = l/2・(141//p)
', and similarly, the current Is' for lines 50, 51, and 52
, 'Is', I4'.

I'=!・(1+'//)・(1-'//, )・
(4) Then, if the current amplification factor of the FIPFI bipolar transistor is 7N, it is a weighted current source transistor.

3A, :m, 3RO covl fi current, Il, Is
, I4c.

I 1 = ”/2・(1-'//,)・(to l-re)
・・・・・・(7) I snow=y/zH-(-4L
)・(1-'//p)・(1-2//N) ・・・(
8) Is-I now・(t+1/)p)! -(t-1θ,)
・(1-2θ,) ...(9)I4xl/24・(1
41//,)S・(1-1θ,)・(l-2θ,)・
...Since α・current O1 & large output amplitude is I (=2ft), the accuracy of the current of each bit is based on the current of M2R.

Mr.■ is ”/21. = 1/2...
α■2nd bit is XV2*, = 1/4・(1+
"//p)...Work 3"1 is... "VHt="
/B・(1+'/r,＞” ”Jl) In terms of Rui, it is (Re1/2・1/4, l/8, l/16
Therefore, the current amplification factor βpK of the p11p transistor
.

However, the current amplification factor 1wK of the npn transistor does not depend on the current amplification factor 1wK. If the current amplification factor βp of the transistor is assumed to be 9fil)), then the non-linearity distribution and the non-linearity of the current ratio are shown in Table 1.

Below is #'White Table 1, which satisfies the 4-bit accuracy of ±3.12m.
The accuracy will further improve if the current amplification factor βp of the np bipolar transistor is large. In addition, in the 0 type QLI-Q4) where the transistor input may be a current source, the accuracy is npn
) does not depend on the current amplification factor βN of the transistor.

This is the case when βN does not change due to the collector current of the transistor (for example, Nikkei Electronics %
1981, No. 8-17, p55, Figure 3
In the N8A process shown in Figure 1, the current amplification factor is almost constant for changes in collector current of 104 or more. In other words, the current amplification factor changes depending on the current level, so in this case, the npn transistors 48 and 4 shown in Fig. 3 are used.
9, 50, and 51, the current mirror circuit transistor pair 52 and 53.54 and 555
By supplying base currents of 6, 57, 58 and 59 from IE#l, the collector current error is 2y/lt,
2, which is a sufficiently small value even if βN changes slightly.

Similar K Pl'll) ) Rangistaro 0,61.62
Figure Jl14 shows an example in which the accuracy of current division is improved slightly by connecting . In the example of Figure 2, *pnp transistor vs.
24 Eituta Dentaki has the same value, but the collector is 0 @ 4
9 and Hammer Den 1! An error of twice the base current occurred.

FIG. 4 shows an example in which this is corrected. 911? ) I) Ilg) ) I
．． Connect with 83 collector. From the so-called Darlington connection, L can be obtained by making the currents of the transistors 82 and 83 and the currents of the wires 86 and 87 almost equal.
&, it is possible to obtain a more accurate current division ratio6.
In the case of e, the current ratio is 1: (1+2//:), and the error is 1//p times that in Fig. The possibility of a mismatch between the base-emitter canal pressures of transistors 84 and 83 and 83' is greater than in the embodiment of FIG.

Therefore, another embodiment is shown in FIG. This is a four-flow split circuit with a multi-collector structure with a collector area ratio of l:1.
NP transistors 98, 99, and 100 are connected together. npn) If the current of the transistor 101 is I, then the current of the pnp transistor 102 is V.
Current It and Hill 103 O Current 11'a,
It = l/2・(1-l/β2) ・・・・・・
α9■1'2/2・(1+2// Similarly, the collector currents of transistors 104, 105, 106 ``I2.I3.I4'' are
-Iz=I/2"-(t+2/z,")・(t-1//
,)'-・aeIs=I/23・(l+2//,2
)2・(l-1θ,)...aηI 4 = l
/24・(1+2//,! )"・<1-1/'/p)
...08 and the maximum output current I (=21
1) The accuracy for K is a9.6・ , aη , (1 fathom).

M @ B It/2M纺l;/! 2nd bit
I'211 m l/4・(l+2/p, goose) 3rd bit IP'2g = "/s・(1+2//, ri")
“′ L 8 B I4/2I, =lAs
・(1+2//, 2) becomes 1. These expected values are 1/2, '/4, and '/s, respectively.

Table 2 shows the accuracy when the current amplification factor βp of the transistor is set to 50.

Table 2 ゛From Table 2, β = father's case, 9 bits of practice, or ±0
．． 0981 or less. Furthermore, when βp is larger, n-value is improved. In addition, when β is even larger, the degree of *S is improved.
Although the collectors of 0, ie, lines 107, 108, and 109, are grounded, they may be connected to lines 110, 111, and 112, respectively. The seed degree S in this case is as shown in Table 2.

Another implementation-1 is shown in FIG. When a DAC according to the present invention is formed on the same semiconductor 4fh, as described above, the transistors have the same shape due to the manufacturing process, and this embodiment reduces the sensitivity difference caused by variations in the voltage between the base and emitter of the transistor. is shown in Figure 6. Resistor 119°120 with the same resistance value R1, 9np) transistor 1
By connecting between the emitters of the transistors 21 and 122 and the connection terminal 123, the angle of variation in the base-emitter voltage VBI between the transistors 121 and 122 can be reduced.

In this case, the current division ratio of transistors 121 and 122 is determined by the ratio of 119 and 120 of resistor R1, so
Accuracy improves.

Similarly, it is used for the current divider circuits 124, 125, 126, and for the DAC current 11[K, R-2B
The lug resistor 111111111127.128 may be used.

Another difference factor in the current dividing circuit is that a collector current ICK 14 @ is generated due to the difference in voltage vcl between the emitter and collector of the transistor. That is, IC=I
5 (exp vllll/V'r) ・(1+V(H
B/VA) Engineering 82 Reverse saturation current VBI: Solder pressure between base and Niotsuta v! :Early voltage Vmu: Known as early voltage. To correct this, it is enough to make the transistor construction and collector voltage vc equal.
Figure 117 shows the example of Figure 12 in which this correction is easily performed by Ksp, and the transistor of Figure 2, 2! %,
Rounding to make the VCIs of 27 and 29 almost equivalent.

I) II) ) In Figure 117, connect the terminal to diode J1
! The connected diodes 135, 136, 137.138.
If 139 and 140 are connected, it can be corrected considerably, but as mentioned above, a slight difference occurs due to the difference in the current flowing through each diode. The illusion of each transistor in Figure 2.

5. Difference between vcIA of 27 and 29, vB11 Tutu Alcala, in Figure 8, resistance 152.153.154.155
Therefore, if this differential brazing pressure is generated and each VCB is made the same correction, even more sufficient correction will occur, and if necessary, only the first bit can be corrected. It is obvious that the same can be applied to the embodiments shown in FIGS. 3 to 6.
It can be done regardless of the number of bits. Also, the current was divided by a pnp) transistor and the DACg current source was constructed by an npn transistor, but conversely, the current dividing circuit is made by an npn) transistor, and the current is divided by a ρnp transistor? ,
The DAC current source may be constructed using a junction field effect transistor (J-FI) rather than a bipolar transistor.
T) or isolated field effect transistor (MO8-
FIST) can also be implemented in the same way.

〔Effect of the invention〕

As explained above, by operating the 1-weighted current generating circuit in DC operation, a more sufficient correction circuit can be connected, and the necessary accuracy can be obtained.

11 Nine weighted currents are calculated using a current zler circuit.
In order to configure an AC weighted current source, a correction circuit is inserted and the output 'dynamic range S (dynamic range) is
never becomes smaller. Moreover, since it can be used as a current output, high-speed operation is possible and glitches do not occur.Also, since the current source transistors can all be configured in the same shape, they can be easily formed on a single semiconductor substrate. and,
Since less voltage is used in the power supply voltage range than the power supply 1[K, the DAC output voltage range can be widened.

As described above, the present invention provides a digital-to-analog converter that is high-speed, highly accurate, has a wide output voltage range, and can be easily fabricated on a single semiconductor substrate.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional DAC, FIG. 2 is a diagram showing an embodiment of the DAC according to the present invention, and FIGS. 3 to 8 are diagrams showing other embodiments of the present invention. It is. 1.41, 74, 88, 113, 129, 141, 15
6...Digital data input terminal, 2~5.42~45.75~78,97,115,13
3,142,157...Switch, 6, 127
,128...R-2R ladder resistance network, 7~10.17,2
o, 31-tO, 48-59. 71-73, 96. '1
01,148°163...NPN bipolar transistor. 11.46...# fed-batch thin wire, 12, 47, 79.93.116.130.149
．． 164 Output electron, 13-16, 86, 87.
IL) 3.107~112,123...Connection line, 1g
, 21 , 81, 94, 117, 131, 150, 16
5...Power supply voltage application terminal, 19.22, 80, 95
, 118, 132, 151, 166...Reference brazing pressure application terminal, 23-30, 60-70.82-85.98-
100,102.104~106°1214122...
・PNP bipolar transistor, 89, 114.13
4.143.158...DAC current source, 90-92-
．． 124-126, 144-147, 159-162・
...Current dividing circuit, 119, 120, 152~
155...Resistance. 135→140...Diode. Agent: Patent Attorney Noriyuki Tora (and 1 other person). 1 Figure 2 Figure 3 Figure 1

Claims (1)

[Claims] A circuit that generates a predetermined IT flow t-S, a transformer, a transistor/) is connected in parallel to divide the dL flow in multiple stages. Drill flow S that was made to occur
Times and additions! A first transistor whose base and collector (or gate and drain) of the transistor are connected, and a second transistor whose base (or gate) is connected to the base (or gate) of this transistor, A weighted current source that generates the weighted 4 currents in the second transistor, and the weighted 1 current source connected in series with the input current switch are connected in parallel to Kl[
A weight t corresponding to the human-powered digital signal composed of fi pieces.
A digital-to-analog converter comprising: means for measuring K.・ .