JPS5816243B2 - Kirokusai Seisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a recording and reproducing apparatus for digital signals such as PCM recording, particularly a tape-type multi-channel digital signal recording apparatus, in which recording and reproducing are performed simultaneously for each channel. The purpose is to make the data transfer rate of each channel equal.

As used herein, one channel on a tape does not necessarily correspond to one track, but may include multiple tracks.

Furthermore, it is not limited to one channel on the tape or one channel of the signal source.

That is, when using a time division method, one channel on the tape is constructed from multi-channel signal sources.

In particular, the present application aims to eliminate the difference in transfer rate caused by a slight slip between the tape and the capstan.

Embodiments of the present invention will be described below with reference to the drawings.

The figure is a 2-channel recording and reproducing circuit diagram shown as a block diagram, Hl and H2 are each 2-channel reproducing head, and the encoded reproduction signal from each reproducing head is processed by a signal processing circuit, as is well known. The clock is amplified and waveform shaped by DM, DM, and then the clock is extracted and connected to a phase-locked loop (PHASE LOCK L).
OOP) circuit PLL1. The signals are supplied to AND circuits A, , A2 (logical product circuits) through PLL2, that is, a first recovered clock stabilizing circuit having a short-time flywheel effect.

On the other hand, the AND circuit A1 includes the signal processing circuit DM.
1, the reproduction command signal, and the output signal of the retrigger type mono multi-vibration brake MM1 which is driven thereby.

Here, the presence or absence of a reproduced clock for each channel is determined.

Further, the output pulse width of this retrigger type mono-multivibrator MM1 is selected to be longer than the clock cycle.

When both signals are all "L", an output of "L" is obtained from the AND circuit A1, and is supplied to the input of the concatenated OR circuit 01 (logical sum circuit).

Further, the other AND circuit A2 is supplied with each signal of the circuit similar to the above and the output signal of the mono multi-bi break MM1 via the inverter 1, and when the signal is rlJ, the OR circuit 01 input, [-1”
A signal is supplied.

In addition, when outputting a signal of "1" from either of these two AND circuits, the signal of "1" or the reproduced clock is output from the OR circuit 01, and if necessary, it is divided into an integer. A frequency dividing circuit FD1 that divides the frequency. FD2 phase detection circuit PD1 has a longer time constant than the first recovered clock stabilization circuit consisting of a loop filter LF, a voltage controlled oscillator VCO, etc., and a longer time than the flywheel effect of the first recovered clock stabilization circuit. The second recovered clock stabilizing circuit PLL3 has a flywheel effect.

The output of the voltage controlled oscillator is supplied to another AND circuit A30.

Both re-trigger type mono multi-vibration break MM mentioned above.

The output of MM2 is supplied to another OR circuit 02, where it is determined whether or not there is a reproduced clock in all channels, and when there is a reproduced clock in any channel, that information is transmitted to the AND circuit A3, and the output is determined as described above. A stabilized regenerated clock is supplied to the other OR circuit 03.

If the reproduced clock cannot be obtained from any of the above channels, the output of the OR circuit 02 or the other input signal 2 is inverted and supplied to the other AND circuit A4.

Therefore, the AND circuit A4 converts the station clock to the above O.
Supplied to R circuit 03.

Furthermore, the output of the OR circuit 03 is used as a clock for channels in other recording modes.

When the reproduced clock is supplied to the pen pal from both channels, the mono multi-vib break MM is connected via the inverter 1 as shown in the figure.

The priority order can be determined by inputting the output from the AND circuit A2 and using the recovered clock from the node H1.

In addition, in the above device, when the channels corresponding to all tracks are in recording mode or playback mode, normal recording and playback can be performed, and the phase-locked loop for stabilizing the playback clock can be used. P.L.
Make the response frequency band of L3 lower than the lowest frequency of the spectrum with a high level of wow and flutter (lowest frequency component with large power supply voltage) when in driving system or recording mode.For example, when in driving system or recording mode. In order to achieve the object of the present invention, it is preferable to select a frequency band lower than the frequency band of the servo system.

Furthermore, considering the possibility that there is dropout in the case of recording media or magnetic tape, we can detect it using a fast attack method.
This can be solved by increasing the flywheel effect as a slow release.

As described above, the present invention reproduces a signal recorded on at least one track, adjusts the phase of the reproduced clock obtained by the reproduced signal in a stabilizing device, and adjusts the phase of the reproduced clock obtained by the reproduced signal. Depending on the presence or absence of the playback clock, switching to another standard signal, such as a station clock, equalizes the data transfer rate of channels in playback mode and channels in other recording modes, allowing for after-recording and other sounds for each channel.・It enables on-sound operation, and has a remarkable effect on recording and playback using digital methods.

Note that the reproduced clock stabilizing circuit PLL1 is, for example, i.

The other recovered clock stabilizing circuit PLL3 has a flywheel effect of, for example, 1 sec or more.

[Brief explanation of drawings]

The figure is a circuit block diagram specifically showing the apparatus of the present invention. Hl, H2...Playback head, PLL3...
...Regenerated clock stabilization circuit.

Claims (1)

[Scope of Claims] 1. A signal recorded on at least one channel on a tape is reproduced, a first reproduced clock stabilizing device reproduces a reproduced clock from the reproduced signal, and the obtained reproduced clock is used as described above. The phase is adjusted in a second recovered clock stabilizing device having a longer time constant than the first recovered clock stabilizing device, and the phase-adjusted recovered clock is transferred to another standard according to the presence or absence of the recovered clock. A recording/reproducing device which switches the signal and uses it as a clock for other channels in recording mode on the tape. 2. Claim 1 wherein the second recovered clock stabilizing device comprises a phase detection circuit, a filter, a voltage controlled oscillator, and further a frequency dividing circuit as required, connected in a loop.
Recording and playback packaging described in