JPS58159682A - Speed control circuit for motor - Google Patents

Abstract

PURPOSE:To simply control a motor by utilizing a demodulated clock signal synchronized with a data signal and comparing it with a reference signal. CONSTITUTION:A data signal detected by a pickup 1 is supplied through an amplifier 3, a waveform shaper 4 to a demodulator 5 and a demodulating clock signal generator 6. The output of the generator 6 is inputted to a phase comparator 8, the output from the reference oscillator 9 is compared in phase, the error voltage is supplied through a low pass filter 10 to a motor drive circuit 11, thereby controlling the rotating speed of the motor 10. The demodulator 5 detects the length of the data signal on the basis of the demodulation clock, and binary data is outputted in response to the length of the data signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control circuit for a motor, and more particularly to a speed control circuit for a constant linear velocity motor such as a digital audio disc (D&D).

Recently, digital audio discs have been developed and are attracting attention, in which 7" information is recorded digitally on a disc, and the recorded information is read and played back using radiation such as a laser beam. The linear velocity is regulated to be constant, and the rotational speed of the motor that drives the disk to complete rotation is sequentially varied as the pickup moves.

Then, the control signal that controls the motor is recorded on the disk (based on the f'L7t data signal recorded), so the pickup detects the longest synchronization signal from the data signal and detects the longest synchronization signal from the data signal. There is a method of controlling the rotation speed of the motor so that the intervals are constant, but there is a problem that it is difficult to extract the synchronization signal and the configuration becomes complicated.

Therefore, the present invention does not take this point into account when considering the VC f''Lt, and by using the demodulated clock signal synchronized with the data signal and comparing it with the reference signal, the motor tsqi+i
The present invention provides a motor speed control circuit that can control the motor speed. Embodiments of the present invention will be described below with reference to the drawings.

A laser beam is emitted onto the tilt disk (2) and the disk 121K is recorded fL! A pickup that reproduces information detects the data signal (
EIO) Well, the demodulation circuit (51 and demodulation clock signal generation circuit 16
1 is supplied. Demodulated clock signal generation circuit (6)
Then, the data signal (So) K synchronized with the demodulated clock frequency (4,3218M1lz) signal (81) is generated.
The generated pulse output is divided into 11 circuits (5).
The demodulation circuit (51) detects the entire length of the data signal (80) based on the demodulated clock signal (S+) iC and outputs t2 over-data according to the length of the data signal. 1) The data signal g(
60), the reference frequency h (4,3218
The demodulation circuit (5) outputs binary data corresponding to the length of the data signal (SO), that is, the signal level. ) is a digital/analog f which sends two lines of digital data from the demodulation circuit (5) to an analog signal.
At the converter, the analog signal is amplified by an amplifier (not shown) and then played back by a speaker. (8) to 4. ! +218MH
A phase comparator circuit is configured with a crystal oscillator that oscillates a reference frequency of z, and inputs the output of the na reference oscillator (9) and the output of the demodulated clock signal generation circuit 161. The circuit is configured to generate a differential voltage. α8 is a low-pass filter that generates a DC voltage according to the error voltage of the phase comparison circuit (8), and its output is supplied to the motor drive circuit 111)V, and is configured to restrict the rotation speed of the motor u3. ing.

Figure 2 shows the main part of the demodulated clock signal generation circuit (6) in Figure 1.
This is a diagram showing the configuration of f detected by pickup txt.
'1. It consists of a one-shot multivibrator-03 that operates on the rising edge of the data signal (80), one-shot multivibrator-041 that operates on the falling edge, and an OR gate U51 in which the outputs of both q-shot multivibrator DC+41 are manually input. Sand pulse generation port wr
αG, the output (S2) of the pulse generation circuit u6, and the reference m
Voltage lI41II that is free-running oscillating at a frequency close to the wave number
The output (Sl) of the J oscillation inη is composed of an input phase comparator and a low-pass filter t19, and the phase ratio I
The outputs (S2) of the pulse generation circuit group are sent to the IR device Ql, respectively.
10,000 inputs and a voltage-constrained oscillator [1
The output (sl) of 7+ is directly supplied through the 1 N A N D gate and f'L! is supplied via an inverter.
The AND gate (support) and the output of the NmND gate α) are supplied to the gate voltage tIIL fL7'j charge pump @
The output of all the P-channel FK TIE and AND gates is supplied to the gate electrode of the N-channel FE.
Due to the light radiation constraints of the capacitor (A), which is composed of T It consists of two. The voltage of the capacitor (7) is fed back to the power control system through the low-pass filter 19, and the number of silkworm cycles of the voltage-constrained oscillator 0L is controlled by the output direct voltage of the low-pass filter 09. It is structured so that it can be saved.

Next, the operation of the present invention having the configuration to be analyzed will be explained.

First, the data signal (SO) is detected from the pink knob 6, and the clock signal generator circuit (6) to which the data signal (EIO) is input operates at the rising edge of the data signal (S). One-shot multi-vibrator-α
J output (s2) and free-running oscillating voltage-controlled hook oscillation a
The output (81) of αη is compared in phase with a phase ratio of 18.

If the phases of this poetry output match perfectly -ζ, as shown in Fig. 3, the phase ratio vaamK will be the same as that of the one-shot multivibrator 1l) output (B 2 )
IIJm ffi! The coincidence of 171 outputs (Sl) is WA
Detected by ND gate (support), while P channel FE
The capacitor (4) is charged by the conduction of To4, and then the one-shot multivibrator-d
When the match between the output (S2) of the inverter (S2) and the inverter output (S-1) of the voltage mt + Iη is detected by the MD gate 4, the conduction of the N channel 11 (2) causes the capacitor (
Since the charges in e) are discharged and reduced, if the phases match and the discharge and charge periods are the same, the potential of the capacitor will not change. Due to the difference in ↓, the potential of the capacitor changes, and the voltage is supplied to the voltage constrained oscillator aη via the low-pass filter aIt, so that the phase difference becomes zero. The mfgl number of the electric IE control oscillator αη is controlled. Also, data signal-55 (8.

), phase comparison is performed as described above between the output of the one-shot multivibrator Q (s2) and the oscillation frequency (Sl) of the electric and pressure am oscillator αn. Phase matching between the it1 target frequency and the data signal (SO) is completed. In this way, a demodulated clock signal synchronized with the data signal (SO) is obtained from the voltage constrained oscillator 171.

In this way, the demodulation circuit]5) The data signal is transmitted.
1WIJIA demodulated clock signal is supplied to
If the rotation speed of the motor I!z that drives the disk (21) is not normal, it will be detected by the pickup (1) and the length of the data signal (SO) will change, so the frequency of the demodulated clock signal will not be normal. .3218MHi.Therefore, in the present invention, a voltage controlled sail generator (1
Reference oscillator (9) consisting of a crystal oscillator with the output of 71
The phase comparator circuit (8) compares the output of
The rotation speed of the motor (130 rotations) is controlled so that the length of o) becomes the normal length, and conversely, the rotation speed of the motor is controlled so that the linear velocity is constant.

Thus, a demodulated clock signal (81) of 4,3218 MHz is sent to the demodulating circuit (5) and synchronized with the data signal (So).
The length of the data signal (So) detected by the pickup (1) r is detected and demodulated into a binary data signal.

As mentioned above, the motor speed of the present invention 1. ! ! 'Control times &! 8
At the same time, the oscillation frequency detected from the oscillation 6-karat pickup that supplies the demodulation clock frequency to the demodulation circuit is 518, and the oscillation frequency is compared with the output of the base 4 oscillator, and the rotation speed of the motor is determined by the error output. By setting 1d to 1d, the rotation of one disk can be constrained to a constant linear velocity i, and is suitable for a 1:1 g degree-hoto type four-deg system such as a digital audio disk system.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the control circuit of the motor speed control circuit of the present invention, Fig. 2 is a diagram showing the demodulated clock signal generation of Fig. 1, and Fig. Output waveform of main part in Figure 2 A'
r''1, ■...Pickup, (2)...Disc, 151
... Demodulation circuit, 6) ... Demodulation clock < K source!
o! path, (7)...Digital Φ analog, (laugh device 1
．． 8)...Phase ratio-, 4 jo, Ryu 9)...Reference oscillator,
111...Motor drive circuit, 16...Pulse generator circuit, 17)...Kurao, ffIj rabbit oscillator,...1
Le...Phase comparator. =387

Claims (1)

[Claims] (1) In the speed f control circuit of the motor that drives the disc using the constant linear velocity method, a demodulation clock synchronized with the data signal is sent to the demodulation circuit that demodulates the 't'L constant data signal detected from the disc. It consists of demodulated clock signal generation means for supplying a signal sound, means for comparing the output of the generation means with the output of the reference oscillator, and means for controlling the drive of the motor according to the error output from the skeleton means. motor speed control circuit.