JPS58159625U - Noise reduction circuit - Google Patents
Noise reduction circuitInfo
- Publication number
- JPS58159625U JPS58159625U JP5638682U JP5638682U JPS58159625U JP S58159625 U JPS58159625 U JP S58159625U JP 5638682 U JP5638682 U JP 5638682U JP 5638682 U JP5638682 U JP 5638682U JP S58159625 U JPS58159625 U JP S58159625U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- noise reduction
- reduction circuit
- previous value
- audio signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は磁気記録再生媒体のオーディオトラック並びに
ビデオトラックの説明図、第２図は従来の雑音軽減回路
のブロック図、第３図は本考案になる雑音軽減回路の一
実施例のブロック図である。
図中符号５は前値ホールド回路、６は第１ディエンファ
シス回路、１８はディエンファシス特性制御回路、１９
はコンパレータ、２０はアナログスイッチ、２１は第２
ディエンファシス回路、Ｑｌはトランジスタ、Ｒ１，Ｒ
２は抵抗、Ｃ１はコンデンサである。Fig. 1 is an explanatory diagram of an audio track and a video track of a magnetic recording/reproducing medium, Fig. 2 is a block diagram of a conventional noise reduction circuit, and Fig. 3 is a block diagram of an embodiment of the noise reduction circuit according to the present invention. be. In the figure, 5 is a previous value hold circuit, 6 is a first de-emphasis circuit, 18 is a de-emphasis characteristic control circuit, 19
is a comparator, 20 is an analog switch, and 21 is a second
De-emphasis circuit, Ql is a transistor, R1, R
2 is a resistor, and C1 is a capacitor.
Claims (1)
しビデオトラックから再生される音声信号を補完する雑
音軽減回路において、前記音声信号をディエンファシス
する第１のディエンファシス回路を時定数の大きな第２
のディエンファシス回路に切換える切換手段と、前記ド
ロップアウト検出信号の多発を検知して前記切換手段を
制御する制御手段とを具備し、前記前値ホールド回路の
駆動に係わる雑音を軽減するよう構成しすこことを特徴
とする雑音軽減回路。In a noise reduction circuit that drives a previous value hold circuit using a dropout detection signal to complement an audio signal reproduced from a video track, a first de-emphasis circuit that de-emphasizes the audio signal is replaced by a second de-emphasis circuit with a large time constant.
and a control means for detecting frequent occurrence of the dropout detection signal and controlling the switching means, and configured to reduce noise associated with driving the previous value hold circuit. A noise reduction circuit with a unique feature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5638682U JPS58159625U (en) | 1982-04-20 | 1982-04-20 | Noise reduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5638682U JPS58159625U (en) | 1982-04-20 | 1982-04-20 | Noise reduction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58159625U true JPS58159625U (en) | 1983-10-24 |
Family
ID=30066916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5638682U Pending JPS58159625U (en) | 1982-04-20 | 1982-04-20 | Noise reduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159625U (en) |
-
1982
- 1982-04-20 JP JP5638682U patent/JPS58159625U/en active Pending
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