JPS58159621U - Muting circuit - Google Patents
Muting circuitInfo
- Publication number
- JPS58159621U JPS58159621U JP5700782U JP5700782U JPS58159621U JP S58159621 U JPS58159621 U JP S58159621U JP 5700782 U JP5700782 U JP 5700782U JP 5700782 U JP5700782 U JP 5700782U JP S58159621 U JPS58159621 U JP S58159621U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- amplifying transistor
- collector
- circuit
- muting circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図示した回路は、本考案のミューティング回路の一実施
例である。
主な図番の説明、2・・・・・・前置増幅回路、3・・
・・・・増幅用トランジスター、8・・・・・・主増幅
回路、10・・・・・・ミューティング用スイッチ、1
1・・・・・・積分回路、14・・・・・・ダイオード
。The illustrated circuit is one embodiment of the muting circuit of the present invention. Explanation of main drawing numbers, 2... Preamplifier circuit, 3...
...Amplification transistor, 8...Main amplification circuit, 10...Muting switch, 1
1...Integrator circuit, 14...Diode.
Claims (1)
出力信号が導出される増幅用トランジスターと、ミュー
ティング動作時閉酸されるミューティング用スイッチと
、該ミューティング用スイッチを通して得られる直流を
積分する積分回路と、該積分回路により積分された信号
を前記増幅用トランジスターのコレクタに印加せしめる
ダイオードとより成り、ミューティング動作時前記積分
回路の出力により前記増幅用トランジスターの増幅度を
低下せしめるようにしたことを特徴とするミューティン
グ回路。An amplifying transistor to which an input signal is applied to the base and an output signal is derived from the collector, a muting switch that is closed during muting operation, and an integral that integrates the direct current obtained through the muting switch. and a diode for applying the signal integrated by the integrating circuit to the collector of the amplifying transistor, and the amplification degree of the amplifying transistor is reduced by the output of the integrating circuit during muting operation. A muting circuit featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5700782U JPS58159621U (en) | 1982-04-19 | 1982-04-19 | Muting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5700782U JPS58159621U (en) | 1982-04-19 | 1982-04-19 | Muting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58159621U true JPS58159621U (en) | 1983-10-24 |
JPS647494Y2 JPS647494Y2 (en) | 1989-02-28 |
Family
ID=30067494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5700782U Granted JPS58159621U (en) | 1982-04-19 | 1982-04-19 | Muting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58159621U (en) |
-
1982
- 1982-04-19 JP JP5700782U patent/JPS58159621U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS647494Y2 (en) | 1989-02-28 |
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