JPS58159119A - Reference voltage circuit for cmos integrated circuit - Google Patents
Reference voltage circuit for cmos integrated circuitInfo
- Publication number
- JPS58159119A JPS58159119A JP4322382A JP4322382A JPS58159119A JP S58159119 A JPS58159119 A JP S58159119A JP 4322382 A JP4322382 A JP 4322382A JP 4322382 A JP4322382 A JP 4322382A JP S58159119 A JPS58159119 A JP S58159119A
- Authority
- JP
- Japan
- Prior art keywords
- type
- reference voltage
- voltage
- vdd
- threshold voltages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
Abstract
Description
【発明の詳細な説明】
本発明けCMO8集積回路用基準電圧回路における基準
電圧の発生方fKI11するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention describes how to generate a reference voltage in a reference voltage circuit for a CMO8 integrated circuit.
従来の方式は第1図に示すように、P型MQ8FIT
1のスレッシ冒−ルド電圧を基準電圧とするものである
。その構成は基準電圧発生回路ブロックΔと定′11t
IIt回路ブロックBとかち成る。The conventional method is P-type MQ8FIT, as shown in Figure 1.
The threshold voltage of 1 is used as the reference voltage. Its configuration is a reference voltage generation circuit block Δ and a constant '11t.
It consists of IIt circuit block B.
基準電圧発生のメカニズムは下式のよらか定丈什によっ
て理解することがで芦る。The mechanism of reference voltage generation can be understood by using the fixed length of the equation below.
基準電圧発生回路ブロックAにおいて、VDD 11位
から1■流れる電流をiαとすると、ia=”β+m
(VDKI −Va −Vtht )” −・”■0丈
において電fliiaf定市沖〕αと仮定すると、設計
すれば、
voo −va = vth+ −”■となる。■式
N VDT)電位を基準としたa点の電圧VαがP型M
O8FI!iT 1のスレッシl−ルビ電圧で慶わζね
ることを示している。In the reference voltage generation circuit block A, if the current flowing from the 11th position of VDD is iα, then ia=”β+m
(VDKI −Va −Vtht )” −・”■ Assuming that the electric potential at 0 length is α, if you design it, voo −va = vth+ −”■.■Formula N VDT) The voltage Vα at point a is P type M
O8FI! It is shown that the threshold of iT1 is satisfied by the l-ruby voltage.
汗)β1はP型M ORF F丁の電圧電流葡換率、V
Dnは11曽電圧、■αけVDT)電位を基準とし六a
やの重臣、VthtけP型M OB FAT 117
”スV 9 ’/ @−1’vト1−1圧
この基準電圧回路の精慶け、0式かられかるように定電
流工αの項をいかに微少に押さえるかKよっτいる。) β1 is the voltage-current conversion rate of P-type M ORF F, V
Dn is 11 voltage, 6a with reference to α VDT) potential.
Yano's senior minister, Vthtke P type M OB FAT 117
``SV9'/@-1'vt1-1voltageThe precision of this reference voltage circuit depends on how to keep the term of the constant current factor α as small as possible from equation 0.
定電法回路ブロックBより、haの電圧vhを求める。From the constant voltage method circuit block B, find the voltage vh of ha.
各MO日FKTの動作を飽和領域に限定してVDD電位
からbaK流れる電流をibとすると、ここでP型MO
EIFKT 2のゲート電圧は抵抗5を通してVDDの
マイナス@に落ときれている。また、vbけN型MO8
IFET a tvケー ト電圧テhルカら、
N 型MO8FETのスレッシ菖−ルド電圧は斡[いと
するとVths = Vt1aとなりの丈は下式のよう
に替形で舞る。If the operation of each MO day FKT is limited to the saturation region and the current flowing baK from the VDD potential is ib, then the P-type MO
The gate voltage of EIFKT 2 is dropped to minus @ of VDD through resistor 5. Also, vbke N type MO8
If the threshold voltage of an N-type MO8FET is □, then Vths = Vt1a, and the length varies as shown in the following formula.
■式#′1Van −VaのVth、tからのバラツキ
が電#1とによって、VDD ICよる電圧依存性を実
用上無視することかで舞る。すなわち0丈は
VDD −Vσ=vtん ・・・・・・■のよ電]形す
ることかで諷、0式け■ぎと一致する。(2) The variation in equation #'1 Van -Va from Vth and t varies depending on voltage #1, even if the voltage dependence due to the VDD IC is ignored in practice. In other words, 0 length is VDD -Vσ=vtn...■noyoden], which matches the idiom, 0-shiki kegi.
注)β!けP型MO8FEIT 2の電圧電流変換率β
3/4はそれぞれN型MOEIFET 5.4の電圧電
流t′換率、VthxけP型MO8FICT2のスレッ
ショールド電圧、Vths 、 VthaけそれぞれN
型MO8FFT 3.4のスレッショールドt 圧。Note) β! Voltage-current conversion ratio β of P-type MO8FEIT 2
3/4 is the voltage-current t' conversion ratio of N-type MOEIFET 5.4, Vthx is the threshold voltage of P-type MO8FICT2, and Vths and Vtha are N, respectively.
Type MO8FFT 3.4 threshold t pressure.
以上の方法をもってすれば、端子αのvDD電位からの
電圧を基準電圧として堰り出すことがでとろt・、この
方式の場合、基板濃度によって決まるP型1%087)
T 1のスレッシ曹−ルド電圧以下の基準電圧しか利用
で着ない。それより高い電圧を必要とする場合はオペア
ンプなどC手段によ抄増幅りなくてはならず、この際に
バラツキ41)!増幅櫨わてiまへ。この従来の方丈で
は、基準電圧が低いのでバラツキも相対的に大舞〈なり
精庸−F不利であった。Using the above method, it is possible to extract the voltage from the vDD potential of terminal α as a reference voltage.In the case of this method, P type 1%087, which is determined by the substrate concentration, is used.
Only the reference voltage below the threshold voltage of T1 can be used. If a higher voltage is required, it must be amplified using C means such as an operational amplifier, and there may be variations in this process41)! Amplify Kashi Watei Mahe. In this conventional hojo, since the reference voltage was low, the variation was relatively large, and the precision was disadvantageous.
本発明はかかる欠点を除去したもCで、その目的は、基
準電圧を高くとることKよりノくラツキ分を相対的に舖
少ζせよらとすることにある。DI T第2図に示す実
施例に基づいて本9苧を峠明する。The present invention eliminates such drawbacks, and its purpose is to relatively reduce the deviation by setting a high reference voltage. DIT Based on the example shown in FIG.
本発明による基準電圧回路もその構成は、基準電圧発生
回路ブロック0と定電流回路ブロックDとから戚る。The configuration of the reference voltage circuit according to the present invention is similar to that of a reference voltage generation circuit block 0 and a constant current circuit block D.
vrIo 11位かち0点に流れる電流をicとすると
、注) β・、1丁けそれ−PわP沙1h40SFRT
6、N型MO8FFT 7の電圧電流変換率、Vt
ha 、 Vth、、tはそねぞれ6,7のスレッショ
ールド電圧、■CFiVoo電位を基準としたc、4の
電圧
分小さく設計すれば
yon−vC−vtm=vtha+vtht =++
+#0)となる。06)式はVDD電位を基準としたC
、6の電圧VCがP型MO8FICT 6とN型MO8
FhT 7とのス5−
レッジ璽−Aド電圧の和でh i G−れることを示し
ている。vrIo If the current flowing to the 11th point and the 0 point is ic, then Note) β・, 1 piece - PwaPsha 1h40SFRT
6. Voltage-current conversion rate of N-type MO8FFT 7, Vt
ha, Vth, and t are threshold voltages of 6 and 7 respectively, and if designed to be smaller by voltages of c and 4 based on CFiVoo potential, then yon-vC-vtm=vtha+vtht=++
+#0). 06) Formula is C based on VDD potential.
, the voltage VC of 6 is P type MO8FICT 6 and N type MO8
It is shown that the sum of the voltages of FhT7 and S5-Ledge-A leads to h i G-.
この方丈においても、回路の精変け0式かられかるよら
K、定電流XcO項をいかに微少に押さえるかによって
いる。定電諸回路ブロックDけ第1図におけるBと同一
であり、P型MOflFKT 9のゲート電圧は抵抗1
1を通して電源電圧VDDのマイナス儒に落とされてい
る。また、d点の電圧vdijN型MO81FKT 8
のゲート電圧である。よってVDD −v6のvTil
からのバラツキを表わす式は第1図の駿明と同様に
して、
となる。ij) fけVDD −VCの77M から
のバラツキかよる電圧依存性を実用上無視することがで
縁る。In this case as well, it depends on how small the constant current XcO term can be kept from the circuit's precision equation. The constant voltage circuit block D is the same as B in FIG. 1, and the gate voltage of the P-type MOflFKT 9 is
1, it is dropped to the minus voltage of the power supply voltage VDD. In addition, the voltage at point d vdij N-type MO81FKT 8
is the gate voltage of Therefore, vTil of VDD-v6
The formula representing the variation from , as in Shunmei in Figure 1, is ij) The voltage dependence due to the variation of f from 77M of VDD -VC can be practically ignored.
すなわち0式は、
+IDD−VC=Vtw…・=@
のように管形することかで舞、0式は(b式と一致する
。In other words, the 0 formula can be changed into a tube shape as follows: +IDD-VC=Vtw...=@, and the 0 formula matches the (b formula).
−6=
注)A#′iP′IJJJMO8FET 9の電圧久流
豐換率、β黍、β+oFiそれぞれN型MO8F11C
T8,10の電圧w汗変換率、VthsけP型MO8F
K79(r+スvッシ璽−ルド電圧。-6= Note) A#'iP'IJJJMO8FET 9's voltage-current conversion rate, β-mill, β+oFi, respectively N-type MO8F11C
Voltage conversion rate of T8, 10, Vths ke P type MO8F
K79 (r+sv shield voltage.
以上の方法をもってすれば、P!!l!MO8FFTと
N MI MO81FETのスレッシ璽−ルド電圧の和
fM準電圧として取9出すことがで−るが、本発明は第
1図の従来の方式にはない。もう一つの特會を有してい
る。それはすなわち、$2図の応用としテ931fK示
すよ’5に、PMMO8FET 1 個とN型MOP
FBTを2個以上蓼列1#続することにより第2図にお
ける方式よりさらに高い電圧を取抄出すことが可能であ
るといら点である。第3図の方式においても、基準電圧
は、12.13.14・・・・・・・・・・15の各M
O81FBTのスレッシ璽−ルド電圧の和となる。この
ように基準電圧をさらに高くとることKよって、相対的
なバラツキ分をよね減少させることが可能になる。If you use the above method, P! ! l! The sum of the threshold voltages of the MO8FFT and the NMI MO81FET can be taken as the quasi-voltage fM, but the present invention does not exist in the conventional system shown in FIG. It has another special feature. In other words, as an application of the $2 diagram, as shown in Te931fK '5, one PMMO8FET and an N-type MOP
The problem is that by connecting two or more FBTs in one row, it is possible to extract a higher voltage than the method shown in FIG. 2. Also in the method shown in Fig. 3, the reference voltage is
This is the sum of the threshold voltages of O81FBT. By setting the reference voltage higher in this manner, it becomes possible to further reduce the relative variation.
本発明の適用例としては、3v系リチウム電池を用い九
時針・電卓・その仲の高電圧回路がある。Examples of the application of the present invention include high voltage circuits such as nine-hour hands, calculators, and the like using 3V lithium batteries.
図中の番号
1、2.6.9.12けP型MO[1iFF:T5、4
.7.8.10. j3.14.15 tiNWM。
PET
VDDけ電源電圧
5.11ti抵抗
以 上
出廖人 株式会社 諏訪精工舎
什理人 弁理士 最上 務
才 1 図
才2図
第3国Numbers 1, 2, 6, 9, and 12 P-type MO in the figure [1iFF: T5, 4
.. 7.8.10. j3.14.15 tiNWM. PET VDD power supply voltage 5.11ti resistance or more Extractor Suwa Seikosha Co., Ltd. Patent attorney Tomisai Mogami 1 Illustration 2 Figure 3
Claims (1)
電界効果トランジスタ、1゛l下MO8FETと称する
)と15MO8FETを各1僻またFip型MO8FE
T 1個とN MI MO8?ETを2@1以上直列接
続して、そのスレッシ1−ルド電圧の和を基準電圧とす
ることを特徴とするCMO8集積回路用基準電圧回路。In CMO8 integrated circuit, P-type MO8FET (M08
Field effect transistors, one each of 1゛1 MO8FET) and 15 MO8FET, and Fip type MO8FE.
1 T and NMI MO8? A reference voltage circuit for a CMO8 integrated circuit, characterized in that two or more ETs are connected in series and the sum of their threshold voltages is used as a reference voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4322382A JPS58159119A (en) | 1982-03-18 | 1982-03-18 | Reference voltage circuit for cmos integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4322382A JPS58159119A (en) | 1982-03-18 | 1982-03-18 | Reference voltage circuit for cmos integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58159119A true JPS58159119A (en) | 1983-09-21 |
Family
ID=12657909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4322382A Pending JPS58159119A (en) | 1982-03-18 | 1982-03-18 | Reference voltage circuit for cmos integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58159119A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62188255A (en) * | 1986-02-13 | 1987-08-17 | Toshiba Corp | Reference voltage generating circuit |
JPH07262864A (en) * | 1991-01-19 | 1995-10-13 | Georg Schlegel Gmbh & Co | Electric switch with press rod |
KR100310858B1 (en) * | 1993-04-30 | 2001-12-15 | 이데이 노부유끼 | Communication circuit system |
JP2008293206A (en) * | 2007-05-23 | 2008-12-04 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
CN104808731A (en) * | 2014-01-27 | 2015-07-29 | 精工电子有限公司 | Reference voltage circuit |
-
1982
- 1982-03-18 JP JP4322382A patent/JPS58159119A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62188255A (en) * | 1986-02-13 | 1987-08-17 | Toshiba Corp | Reference voltage generating circuit |
JPH07262864A (en) * | 1991-01-19 | 1995-10-13 | Georg Schlegel Gmbh & Co | Electric switch with press rod |
KR100310858B1 (en) * | 1993-04-30 | 2001-12-15 | 이데이 노부유끼 | Communication circuit system |
JP2008293206A (en) * | 2007-05-23 | 2008-12-04 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
CN104808731A (en) * | 2014-01-27 | 2015-07-29 | 精工电子有限公司 | Reference voltage circuit |
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