JPS58158912A - High mobility semiconductor material - Google Patents

High mobility semiconductor material

Info

Publication number
JPS58158912A
JPS58158912A JP4135482A JP4135482A JPS58158912A JP S58158912 A JPS58158912 A JP S58158912A JP 4135482 A JP4135482 A JP 4135482A JP 4135482 A JP4135482 A JP 4135482A JP S58158912 A JPS58158912 A JP S58158912A
Authority
JP
Japan
Prior art keywords
layer
mobility
semiconductor material
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4135482A
Other languages
Japanese (ja)
Inventor
Takafumi Yao
隆文 八百
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP4135482A priority Critical patent/JPS58158912A/en
Publication of JPS58158912A publication Critical patent/JPS58158912A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • H01L21/02507Alternating layers, e.g. superlattice

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain a mixed crystal semiconductor material of which mobility is high by such an arrangement wherein a buffer layer is deposited on a substrate, and layers of semiconductors, each differs in constitution from other, are alternately and regularly laid over another by the unit of 1mol layer or 2mol layer on the buffer player. CONSTITUTION:On a substrate 7 made of semiconductor or insulation material, a buffer layer 8 of semiconductor or insulation material is caused to grow, and on the layer, a layer 9 of AX single molecule and a layer 10 of AqB1-qX (0<=q<1) single molecule are alternately deposited by 1mol layer up to a desired thickness. Since carriers in the direction parallel with the substrate 7 detect regular lattice potential such as A-X-A-X... in the layer 9, they can realize mobility of high speed without being affected by the influence of alloy dispersion. On the one hand, in the layer 10, alloy dispersion and space charge dispersion exist, except q=0. However, at the time of q=0, the layer 10 becomes BX, and there exists no alloy dispersion nor space charge dispersion. In any case, the average mobility of the layer 9 and layer 10 in the direction parallel with the substrate 7 becomes larger. On the one hand, the mobility of carriers running in the direction perpendicular to the substrate also becomes larger, as the irregularity of potential is lessened.

Description

【発明の詳細な説明】 本発明は、所望の混晶半導体と等しい平均的組成をもつ
高移動度の積層半導体材料に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high mobility layered semiconductor materials having an average composition equal to the desired mixed crystal semiconductor.

従来の半導体材料の一つに混晶半導体がある。One of the conventional semiconductor materials is a mixed crystal semiconductor.

一般に、混晶半導体材料は次のような利点を有している
Generally, mixed crystal semiconductor materials have the following advantages.

(1)混晶の組成比を適当に選ぶことによって1エピタ
キシヤル成長用基板との格子定数の整合をとることがで
きる。
(1) By appropriately selecting the composition ratio of the mixed crystal, it is possible to match the lattice constant with the substrate for epitaxial growth.

(2)混晶の組成比を変えることによって、エネルギー
・バンド・ギャップ、電子親和力、屈折率を変えること
ができる。
(2) By changing the composition ratio of the mixed crystal, the energy band gap, electron affinity, and refractive index can be changed.

(S)  特にダ元半導体混晶では、格子定数とエネル
ギー・バンド・ギャップを独立に変化させることができ
る。
(S) In particular, the lattice constant and energy band gap can be changed independently in a semiconductor mixed crystal.

等である。etc.

しかし、混晶のキャリア移動度は、混晶を構成する半導
体の移動度を用いて、ベガードの法則により求められる
移動度より、はるかに低い値を示す。これは、混晶中の
キャリアは、通常のフォノンやイオン化不純物による散
乱機構以外に、余分な合金散乱や空間電荷散乱を受ける
ためである。合金散乱は、混晶の構成原子の分布の不規
則性によるものであり、空間電荷散乱は、空間的な組成
の不均一性によって誘起される空間′d!荷による散乱
である。これらの効果のため、混晶半導体材料を用いた
トランジスタや光検知器等の素子の高速動作は困鎧とな
っている。このことをInxGa1−xムSを例にとっ
て以下に説明する。第7図はイオン化不純物密度が77
にで−7,39×10”cs−”のIno、40ao、
@Asの電子移動度の一度依存性を示す(〒’、 Ka
toda、 F。0saka、 and T。
However, the carrier mobility of the mixed crystal exhibits a much lower value than the mobility determined by Vegard's law using the mobility of the semiconductor constituting the mixed crystal. This is because carriers in the mixed crystal undergo extra alloy scattering and space charge scattering in addition to the normal scattering mechanism caused by phonons and ionized impurities. Alloy scattering is due to the irregularity in the distribution of the constituent atoms of the mixed crystal, and space charge scattering is caused by the spatial ′d! This is due to scattering due to the load. These effects make it difficult to operate devices such as transistors and photodetectors using mixed crystal semiconductor materials at high speed. This will be explained below using InxGa1-x system S as an example. Figure 7 shows that the ionized impurity density is 77.
Nide-7,39×10"cs-" Ino, 40ao,
Shows the once dependence of the electron mobility of @As (〒', Ka
toda, F. 0saka, and T.

sugano、 Japan、 J、ムpP1. Ph
Vg、 vol /、3. P、 54/−p−56コ
C/97→)。図中で実1d 1.2.8.4は各々光
学7オノン散乱、イオン化不純物散乱、空間電荷散乱、
合金散乱の移動度の計算値を示し、破線5は以上の散乱
を考慮して得られた移動度の計算値を示すものである0
黒点とそれを結ぶ実@6は実験で得られた移動度を示す
。この材料では、70に〜3COKの温度範囲で、空間
vjt荷散乱が主要な敗、!1L19?素となっている
。一方、例えば、ND −JNAI NKl十NA −
/X 1011 cm−aのムl@uGIL*、 ad
sのような半4体材料では、100K附近で合金散乱が
皺も強い散乱要素となっている( A、 0handr
aand  L F、Eastman、J、ムpI)1
.Phy!1.vol  &/、I)、コロ6デ〜p、
21,7り(/910))。即ち、合金散乱及び空間電
荷散乱は、混晶半導体材料の移動度を制限する主要な原
因の一つである。
Sugano, Japan, J, pP1. Ph
Vg, vol/, 3. P, 54/-p-56koC/97→). In the figure, real 1d 1.2.8.4 is optical 7-onone scattering, ionized impurity scattering, space charge scattering,
The calculated value of the mobility of alloy scattering is shown, and the broken line 5 shows the calculated value of the mobility obtained by considering the above scattering.
The black dot and the fruit @6 connecting it indicate the mobility obtained in the experiment. In this material, spatial load scattering is a major failure, in the temperature range from 70 to 3 COK! 1L19? It is basic. On the other hand, for example, ND -JNAI NKl0NA -
/X 1011 cm-a mul@uGIL*, ad
In a semi-4 body material like s, alloy scattering becomes a strong scattering element near 100K (A, 0handr
aand L F, Eastman, J, pI)1
.. Phy! 1. vol &/, I), Colo 6 de~p,
21,7ri (/910)). That is, alloy scattering and space charge scattering are one of the main causes that limit the mobility of mixed crystal semiconductor materials.

本発明は、以上に記したような混晶半導体材料の欠点を
除き、技術的に容易な方法で、この混晶半導体材料と実
効的な組成比が等しく、かつキャリア移動度のより大き
な半導体材料を提供することを目的としてなされたもの
である。
The present invention eliminates the drawbacks of mixed crystal semiconductor materials as described above and uses a technically easy method to create a semiconductor material that has the same effective composition ratio as this mixed crystal semiconductor material and has higher carrier mobility. It was made with the purpose of providing.

以下本発明について、初めにムpn、−pX (Qmp
〈/)型の三元混晶半導体を例にとって説明する。
Hereinafter, regarding the present invention, firstly, Mpn, -pX (Qmp
This will be explained by taking a 〈/) type ternary mixed crystal semiconductor as an example.

ここで、この混晶の構成半導体は、■及びBXである。Here, the constituent semiconductors of this mixed crystal are ■ and BX.

また、ム、1%0はそれぞれ金属元素を、X、Y%2は
それぞれ非金属元素を表す記号である。
Moreover, M, 1%0 are symbols each representing a metal element, and X and Y%2 are symbols each representing a nonmetallic element.

1112図は本発明のムpBl−pX型三元混晶半導体
の代表例の原理説明のための1で、清浄な基板7の表向
上にバッファ層8を成長させ、さらにその上に、■単分
子層9とAqBt−IX(p≦q〈/)−単分子層10
tt1 分子層ずつ交互に所望の厚さまで積層した噸ユである。
Figure 1112 is a diagram 1 for explaining the principle of a typical example of the pBl-pX type ternary mixed crystal semiconductor of the present invention, in which a buffer layer 8 is grown on the surface of a clean substrate 7, and on top of that, Molecular layer 9 and AqBt-IX (p≦q〈/)-monolayer 10
tt1 This is a fabric in which molecular layers are alternately laminated to a desired thickness.

ここで、積層の順序をムqIBl−(X −AXとする
ことも可能である。但し、pとqg)間係組成は、当該
混晶と等しい。このように単分子層単位で積層した材料
を作成することは、現在のエピタキシャル成長技1#な
用いれば容易に可能である。基板テと平行方向のキャリ
ヤは1.■単分子層9中ではムーX−ム−X10.とい
う規則正しい格子ポテンシャルを感じるため、合金散乱
及び空間電荷散乱の影響を受けることなく高速の移動度
が実現できる。他方、ムQBI−qX(θ≦pく/)単
分子層10中では、q−Oを除き通常の混晶と同様に合
金散乱及び空間電荷散乱が存在する。しかし、q−θで
はム、Bl−、X単分子層lOはBXとなり、合金散乱
及び空間電荷散乱はない。いずれにせよりα単分子一層
9とム、B、1X単分子*20の基板に平行方向の平均
的移動度は当該ムpBl−pXljj混晶半導体の移動
度より大きくなる。一方、基板に垂直な方向に走行する
キャリヤは、ん二近接層までを考えるとム−X−B−X
−A−X−、、、というポテンシャルか、A −X−ム
−X−X −A−X +、、。というポテンシャルのど
ちらかを感じることになり、ポテンシャルの不規則性は
減るため、合金散乱及び空間電荷散乱は減少する。従っ
て、基板に垂直方向のキャリヤの移動度は、当該ムpB
i −pX M l!i晶半導体の移動度より大きくな
る。
Here, it is also possible to set the stacking order to be MqIBl-(X-AX. However, the relational composition between p and qg is the same as that of the mixed crystal. It is easily possible to create materials laminated in monolayer units in this manner using the current epitaxial growth technique 1#. The carrier parallel to the substrate is 1. ■In the monomolecular layer 9, MuX-Mu-X10. Because of the sense of a regular lattice potential, high-speed mobility can be achieved without being affected by alloy scattering and space charge scattering. On the other hand, in the monomolecular layer 10 of QBI-qX (θ≦p/), alloy scattering and space charge scattering exist as in normal mixed crystals except for q-O. However, at q-θ, the monomolecular layer 10 of Mu, Bl-, and X becomes BX, and there is no alloy scattering or space charge scattering. In any case, the average mobility of the α single molecule single layer 9 and Mu, B, 1X monolayer *20 in the direction parallel to the substrate is greater than the mobility of the pBl-pXljj mixed crystal semiconductor. On the other hand, carriers traveling in the direction perpendicular to the substrate are
The potential is -A-X-,..., A-X-mu-X-X -A-X +,.... Since the irregularity of the potential is reduced, alloy scattering and space charge scattering are reduced. Therefore, the carrier mobility in the direction perpendicular to the substrate is
i-pX M l! The mobility is greater than that of i-crystalline semiconductors.

以上はムpBi−pX ((15≦X〈/)型の混晶半
導体についての説明であるが、ムt−pBpX ((1
3≦X〈/)−ムqB1− q X  AqB 1− 
q X −、、、の如く、2分子層ずつ規則的に積層し
ても同様な効果が得られるし、また1、■−ムX −A
、Bl−、X−、、、の如く、2分子層と1分子層を規
則正しく混合して積層しても同様な効果が得られる。要
するに、規則的に積層することによって合金散乱及び空
間電荷散乱が減少し、キャリヤ移動度の大巾な増加が得
られる。
The above is an explanation of the mixed crystal semiconductor of the type pBi-pX ((15≦X〈/), but the explanation is for the mixed crystal semiconductor of the type pBi-pX ((1
3≦X〈/)-MuqB1- q X AqB 1-
A similar effect can be obtained by stacking two molecular layers regularly, such as q
, Bl-, X-, . . , a similar effect can be obtained by stacking bimolecular layers and monomolecular layers in an orderly mixture. In short, ordered stacking reduces alloy scattering and space charge scattering and provides a significant increase in carrier mobility.

次ニ、ApBqOi−p−qX (+≦p</、+≦q
〈/。
Next, ApBqOi-p-qX (+≦p</, +≦q
〈/.

1≦p+q</)型の四元混晶半導体について説明する
。ここで当該混晶の構成半導体はムx、 nx及びCx
である。
A quaternary mixed crystal semiconductor of 1≦p+q</) type will be explained. Here, the constituent semiconductors of the mixed crystal are Mx, nx and Cx
It is.

第3図は本発明のムP”tlol−P−11X型四元混
晶半導体の代表例の原理説明のための図である。清浄な
基板7の表向上にパンファ層8を成長させ、さらにその
上に、■単分子層11 s ilX単分子層12AyB
101−r−gX (0≦r</、0≦s</、0≦r
+s</)単分子層1Bを7分子層ずつ交互に所望の厚
さまで積層したものである。但し、plqとr、sの1
+Ii係は、 p−4−<i+r> (1−+(/+a) であり、この半導体材料の平均的組成は当該混晶と等し
い。この場合も上に記したApB l + px型三元
混晶半導体と同様な議論が展開でき、■層11、BX層
12、ムrBao1−r−s層18を1分子層ずつ  
  “交互に多層に積層した半導体材料のキャリヤ移動
度は当該混晶の移動度より大きくなる。当然のことであ
るが、ApBqOl −p−qX型四元混晶半導体でi
≦p</、−4−≦q〈/、−≦p+q</畠 以外のp、qの値をもつ混晶についても上記の結論は変
らない。本例では、1分子層ずつ積層しする方法は数多
くある。どのような積層の方法゛11でも多くとも2分
子層単位以下での規則的な積法に、ムpBi−pXqY
i −q (0,3≦p</、 Q、li’−!q</
) M四元混晶半導体について説明する。ここで当該混
晶の構成半導体はAX BX、 AY、 BYのダ種類
である。
FIG. 3 is a diagram for explaining the principle of a typical example of the P"tlol-P-11X type quaternary mixed crystal semiconductor of the present invention. A breadlayer 8 is grown on the surface of a clean substrate 7, and On top of that, ■ monomolecular layer 11 s ilX monomolecular layer 12AyB
101-r-gX (0≦r</, 0≦s</, 0≦r
+s</) monomolecular layers 1B are alternately laminated in seven molecular layers to a desired thickness. However, 1 of plq, r, and s
The +Ii coefficient is p-4-<i+r> (1-+(/+a)), and the average composition of this semiconductor material is equal to that of the mixed crystal. In this case as well, the ApB l + px type ternary described above The same argument as for mixed crystal semiconductors can be developed, and the layer 11, the BX layer 12, and the layer Bao1-rs layer 18 are made one molecular layer each.
“The carrier mobility of the semiconductor material stacked in multiple layers alternately is greater than the mobility of the mixed crystal.It goes without saying that in the ApBqOl-p-qX type quaternary mixed crystal semiconductor, i
The above conclusion does not change for mixed crystals having p and q values other than Hatake. In this example, there are many methods for laminating one molecular layer at a time. Whatever the layering method ``11'', a regular layering method with at most two molecular layer units or less, pBi-pXqY
i −q (0,3≦p</, Q, li'−!q</
) The M quaternary mixed crystal semiconductor will be explained. Here, the constituent semiconductors of the mixed crystal are of the following types: AX, BX, AY, and BY.

第q図は本発明をApB l−pXqYt −q 型四
元混晶半導体に適用した代表例の原理説明を示す図であ
る。清浄な基板7の表面上にバッファ層8を成長させ1
.欽単分子層14、BX単分子層15、AY単分子層1
6、ArBt−rx# Yl−a単分子層(θ≦r〈/
、O≦tx < / )1テを一分子層ずつ交互に所望
の厚さまで積層したものである。但し、pSqとrsB
の関係は、 p−+(コ+r) q−4−(2+t) であり、この半導体材料の平均的組成は当該混晶と等し
い。この場合も上記のムpB1.−p X 1jJI 
三元混晶半導体と同様な#Al11+が成立し、この型
の半導体材料のキャリヤ移動度は当該混晶の移動度型、
ApBI−pXI−qYq型四型温元混晶半導体いても
同様の結論が得られる。本例では、1分子層ずを維持し
つつ、規則的に積層する方法は数多くある。どのような
積層の方法でも、多くとも2分子層単位以下での規則的
な積層によって、同様な移動度増大の効果が得られる1
、 以上の例は、合金散乱及び空間′鑞付散乱を抑制し、移
動度の高速化を図ろうとするものであった。
FIG. q is a diagram illustrating the principle of a typical example in which the present invention is applied to an ApB l-pXqYt -q type quaternary mixed crystal semiconductor. A buffer layer 8 is grown on the surface of a clean substrate 7 1
.. Kin monomolecular layer 14, BX monomolecular layer 15, AY monomolecular layer 1
6. ArBt-rx# Yl-a monolayer (θ≦r〈/
, O≦tx</) 1 te is alternately laminated one molecular layer at a time to a desired thickness. However, pSq and rsB
The relationship is p-+(co+r) q-4-(2+t), and the average composition of this semiconductor material is equal to that of the mixed crystal. In this case as well, the above pB1. -p X 1jJI
#Al11+ similar to a ternary mixed crystal semiconductor is established, and the carrier mobility of this type of semiconductor material is the mobility type of the mixed crystal,
A similar conclusion can be obtained for the ApBI-pXI-qYq type four-type warm mixed crystal semiconductor. In this example, there are many methods for regularly stacking layers while maintaining no single molecule layer. Regardless of the stacking method, a similar mobility increase effect can be obtained by regular stacking of at most two molecular layers or less1.
The above examples were aimed at suppressing alloy scattering and spatial brazing scattering and increasing the mobility.

次に、さらにイオン化不純物散乱を抑制し、より一層の
移動度の高速化が実現できる当該高速移動度半導体材料
の一例について説明する。
Next, an example of the high-mobility semiconductor material that can further suppress ionized impurity scattering and achieve even higher mobility will be described.

第9図は合金散乱及び空間電荷散乱を抑制し、度の低い
半導体で積層部分85を堆積する。ざら−にこの積層部
分85の実効的なバンドギャップよりも大きいバンドギ
ャップを持ち、かつ前記不さに堆積する。さらに同じ半
導体材料をpi麿又はn型にドープした半導体材料8フ
を堆積する。
FIG. 9 suppresses alloy scattering and space charge scattering, and deposits a stacked portion 85 with a low-strength semiconductor. It has a band gap that is roughly larger than the effective band gap of this laminated portion 85, and is deposited in the above-mentioned void. Further, 8 layers of semiconductor material doped with the same semiconductor material as Pi or n-type are deposited.

このよりな*iによって、p型又はnmにドープして堆
積した半導体材料81中の電子又は正孔はハ・>1゛八
′マツ27′の嫌い積層部分85中に移行し1核種層部
分8bの中のメシドYイツアの7ムいし卆備層部分85
中の不純物濃度が低く、かつ前記p型その濃度をp型又
はn型にドープして堆積した半導体材料87のドープす
る不純物濃度と不純物濃度の低い層8Gの厚さによって
制御でき、しかも、合金散乱及び空間電荷散乱のみなら
ず不純物散乱も受けないので、高速移動度が実現される
Due to this twist *i, the electrons or holes in the p-type or nm-doped semiconductor material 81 are transferred into the laminated part 85 of the pine 27', which is one nuclide layer. Mesido Y Itza 7mm storage layer part 85 in 8b
The p-type impurity concentration is low, and the concentration can be controlled by the impurity concentration of the p-type or n-doped semiconductor material 87 and the thickness of the layer 8G with the low impurity concentration. Fast mobility is achieved because it is not subject to impurity scattering as well as scattering and space charge scattering.

次に、バッファ層の構成について説明する。Next, the structure of the buffer layer will be explained.

バッファ層は当該基板の当該積層部分への影−を取り除
き、良好な特性を持った当禮槓m部分を形成するために
必要である。当該基板の格子定数と当該積層部分の実効
的格子定数が03%の範囲内で一致しているとき、バッ
フ7層としては、 (リ 当該基板と同じ材料 (2)  当該積層部分と同一のもの ・但し、膜厚は
a!fμ魯〜IO声島 (8)  当該基板又は当該積層部分と03%以内で積
層定数の一致している半導体材料、又は積層部分 以上の(1)〜(a)のうちいずれかを選ぶことができ
る。
The buffer layer is necessary to eliminate the shadow of the substrate on the laminated portion and to form the layered portion with good characteristics. When the lattice constant of the substrate and the effective lattice constant of the laminated portion match within a range of 0.3%, the 7th buff layer is made of the same material as the substrate (2) The same material as the laminated portion・However, the film thickness is a!fμRo ~ IO Koejima (8) Semiconductor material whose lamination constant matches the substrate or the laminated part within 0.3%, or (1) to (a) of the laminated part or more You can choose one of them.

当該基板の格子定数と当該積層部分の実効的格子定数が
上記の値以上に異っているとき、バッファ層としては、 当#基板に接する部分はその格子定数とはば等しく、か
つ当該積層部分に接する部分は、その実効的格子定数と
ほぼ等しくなるように、格子定数を第11図の(g)又
はφ)又は(C)に示したように変化させた半導体材料
が適当である◎ ここでJi//#j!J(g)は、格子定数の変化がm
をとなるようにしたものであり、第11図0)は、格子
定数を階段状に変化させたものであり、第1/図(C)
は鋸−状に格子定数を変化させたものである。
When the lattice constant of the substrate differs from the effective lattice constant of the laminated portion by more than the above value, the buffer layer should have a lattice constant equal to that of the portion in contact with the substrate, and For the part in contact with the semiconductor material, it is appropriate to use a semiconductor material whose lattice constant is changed as shown in (g) or φ) or (C) in Figure 11 so that the effective lattice constant is almost equal to the effective lattice constant of the semiconductor material. And Ji//#j! J(g) is the change in lattice constant m
Figure 11 (0) is the one in which the lattice constant is changed stepwise, and Figure 1/(C)
The lattice constant is changed in a sawtooth pattern.

バッファ層を構成する半導体材料は、上記の要件を満足
すれば、通常の半導体材料、化合物半導体材料でも可能
であり、又、本発明の積層部−分でも可能である。
The semiconductor material constituting the buffer layer may be an ordinary semiconductor material, a compound semiconductor material, or the laminated portion of the present invention, as long as it satisfies the above requirements.

1・次に、本発明の実施例について説明する。1. Next, embodiments of the present invention will be described.

、第S図はムpBl−pX型混晶半導体の一実施例と梶
で平均的組成がIn・、 @ GJLOoilBである
半導体材料をInP基板上に作成した例の説明図である
0InP基板18上に、InPバッファ層19を成長さ
せる。さらにその上にInAl2GとGaAs 21 
 を交互に1分子層ずつ積層するとこの積層部分の平均
的1はIno、6Ga4−ムSとなる。混晶In@、5
eGao、isムSとInPとの格子定数のミスマツチ
は02%と非常に小さいのでInAs/GaAs檀層2
0゜2】とInP■9との界面の結晶性の乱れは無視で
きるので、InAs/GaAs層20.21の結晶性は
極めて良い。InAs/ GaAs層の合金散乱及び空
間1!!#散乱の影曽は極めて小さいので、室温での電
子移動度として/×IO’Cd1−程度の値が得られる
ことが期待される。
FIG. Then, an InP buffer layer 19 is grown. Furthermore, InAl2G and GaAs21
When these are alternately laminated one molecular layer at a time, the average 1 of this laminated portion becomes Ino, 6Ga4-muS. Mixed crystal In@, 5
Since the lattice constant mismatch between eGaO, ism S and InP is very small at 0.2%, InAs/GaAs layer 2
The crystallinity of the InAs/GaAs layers 20 and 21 is extremely good because the disturbance in the crystallinity at the interface between the InAs/GaAs layers 20 and 21 can be ignored. Alloy scattering and space of InAs/GaAs layer 1! ! Since the influence of #scattering is extremely small, it is expected that a value of approximately /×IO'Cd1- can be obtained as electron mobility at room temperature.

第S図に挙げた例ではバッフ7層19としてInPを考
えているが、その代りに格子定数の整合をきちんととる
ためにInxGax−xAs (x : Q3J→a5
θ)とすることは可能である。第5図は平均的組成がI
ns、sGa@、−ムSである半導体材料をInP基板
18の上に成長した例であるが、特に格子定数をほぼ整
合させた例として、表1のような基板と積層部分の組合
わせがあり、これら半導体材料金てに対して、本発明に
よる移動度の着しい増大が見込まれる。積層部と等しい
組成を持つ混晶と基板との格子整合がとれない場合゛で
も、上に記した例に倣って積層することによって移動度
の着しい増加が見込まれる。
In the example shown in FIG.
θ) is possible. Figure 5 shows that the average composition is I
This is an example in which semiconductor materials such as ns, sGa@, and -muS are grown on the InP substrate 18. In particular, as an example in which the lattice constants are almost matched, the combination of the substrate and the laminated portion as shown in Table 1 is Therefore, it is expected that the present invention will significantly increase the mobility of these semiconductor materials. Even if lattice matching cannot be achieved between a mixed crystal having the same composition as that of the laminated portion and the substrate, a significant increase in mobility can be expected by laminating the layers in accordance with the example described above.

余   白 表  1 」Ino、52AIo、48ASInP、′■nAS−
■no、o4A1o、96ASi Ino、5Gao、
5P    GaAs   InP −GaP:、 I
 no 、 sA 1 o 、 sP   、 GaA
s   InP −A I P: Alo、5Gao、
5As   GaAs l AlAs −GaAs1A
IXGa1−xSb       ’  GaSb  
 ’  Garb  −、A12xGa1−2xSh 
 (x<0.5)24、 InAs!5、Ale、5s
sGILs、tmsIno、ssAg 26を交互に1
分子層ずつ積層するとこの積層部の平均的組成はAle
、pe +Ga@、s q *Ins、h sAIと等
しい0混晶Ale、a @4Gas、s v aIns
、 h sム8とInP基板22との格子定数のミスマ
ツチはほとんどないので、GaA8/−) jnAs/Al e、a s zGas、 1111 
Ino、s sA8 積層部24.25.26p In
P 22との界面での結晶性の乱れはない。
Margin table 1 ``Ino, 52AIo, 48ASInP,'■nAS-
■no, o4A1o, 96ASi Ino, 5Gao,
5P GaAs InP-GaP:, I
no, sA 1 o, sP, GaA
sInP-AIP: Alo, 5Gao,
5As GaAs l AlAs -GaAs1A
IXGa1-xSb' GaSb
' Garb-, A12xGa1-2xSh
(x<0.5)24, InAs! 5, Ale, 5s
sGILs, tmsIno, ssAg 26 alternately 1
When laminating molecular layers one by one, the average composition of this laminated part is Ale.
, pe +Ga@, s q *Ins, h 0 mixed crystal Ale equal to sAI, a @4Gas, s v aIns
, Since there is almost no mismatch in the lattice constants between h sm 8 and the InP substrate 22, GaA8/-) jnAs/Ale, a s zGas, 1111
Ino, s sA8 Laminated part 24.25.26p In
There is no disturbance of crystallinity at the interface with P22.

■ −GaAs/InAs/Ale、 5ssGa@、 t
msIno、s+sAs層24.25.26の合金散乱
及び空間電荷散乱の影響はム1・。■寓G5L@、11
8InQulム8 N 26を走行する電子のみ受ける
ので平均的な電子移動度は特に低温度で大巾な増加を示
すと期待される。
■ -GaAs/InAs/Ale, 5ssGa@, t
msIno, the influence of alloy scattering and space charge scattering of the s+sAs layer 24,25,26 is mu1. ■Fable G5L@, 11
Since only electrons traveling through the 8InQIlum 8N 26 are received, the average electron mobility is expected to show a large increase, especially at low temperatures.

上記の例ではバッファ層28としてIn・、 5sAl
e、48A8を使ったがIn・、s*Al・、48ムS
の代りにIn・、BGa・、49ABやInPを用いて
も同じような移細度の増加があるのは明らかである。平
〜的組成ム1e−ss*GILe、ats Ins、s
sム8をちょうど格子定数の盛合がとれるInP麺板2
2の上に成長した例について説明したが、基板と格子定
数を整合した例として他のムBB、cl−,−qx #
1の混晶種半導体についても、表2の如き組合わせがあ
り、これらの半導体材料金てに対して、本光明による移
動度の着しい増大が見込まれる。表2では使亘上1分子
層ずつの積層としたが、2分子層までの規\ 表2 jl 1 WJ ハApBt −PXIIYI −(i
li[51& 4”II 体f) 一実施例として平均
的組成がGa・、IIn・、1Ail・、s8b・、I
である半導体材料をGa8b基板37上に作成した例を
説明する図である。Ga8b 基板27の上にGaO,
IIn・、ins、i8b*、sバッファ層28を成長
させる。さらにその上にGaAs Z&InA186 
、 In8b 81 、Ga8b8mを交互に1分子層
ずつ積層すると、この積層部の平均的組成はGa・、I
In・、IA8・、ssb・、Iとなる。
In the above example, the buffer layer 28 is In., 5sAl.
e, I used 48A8, but In・, s*Al・, 48muS
It is clear that a similar increase in mobility can be obtained by using In., BGa., 49AB, or InP instead of . Typical composition 1e-ss*GILe, ats Ins, s
InP noodle plate 2 with just the right lattice constant for SM8
Although we have described an example in which the lattice constant is matched to that of the substrate, we have described an example in which the lattice constant is matched to that of the substrate.
Regarding the mixed crystal seed semiconductor of No. 1, there are combinations as shown in Table 2, and it is expected that the present invention will significantly increase the mobility of these semiconductor materials. In Table 2, for ease of use, the lamination is made with one molecular layer at a time, but the rule is up to two molecular layers.
li [51 & 4” II body f) As an example, the average composition is Ga・, IIn・, 1Ail・, s8b・, I
FIG. 3 is a diagram illustrating an example in which a semiconductor material of is created on a Ga8b substrate 37. GaO on the Ga8b substrate 27,
The IIn., ins, i8b*, s buffer layer 28 is grown. Furthermore, GaAs Z & InA186
, In8b 81 , and Ga8b8m are alternately laminated one molecular layer at a time, the average composition of this laminated portion is Ga., I
In・, IA8・, ssb・, I.

混晶Ga@、1IflsjA11*、s 8be、iと
Ga8b基板2フとは格子定数の整合がほとんどとれて
いる。従って、一層部分29.8G、 81.8fiと
基板との界面での結晶性の乱れはない。GaAg/In
As/In8b/Ga8b層29゜8G、 81.82
のキャリヤは合金散乱及び空間電荷散乱の影響を受けな
いため高速の電子移動度が実現する。
The lattice constants of the mixed crystal Ga@, 1IflsjA11*,s8be,i and the Ga8b substrate 2F are almost matched. Therefore, there is no disturbance of crystallinity at the interface between the first layer portions 29.8G and 81.8fi and the substrate. GaAg/In
As/In8b/Ga8b layer 29°8G, 81.82
Since the carriers are not affected by alloy scattering and space charge scattering, high-speed electron mobility is achieved.

t4g図に示したムpB1−pxCLyl−11溜混晶
半導体の実施例では、バッフ7層としてGa・4In・
、iム8・、18b・、Sを用いたが、Ga5bを用い
ても同様な効果が得られる。他のムPB1−Pxlly
l−Q m混晶牛導体においても積層構造を適切に選ぶ
と、キャリヤ移め、1分子層ずつの積層としたが、2分
子層までの規則的な積層によっても高速移動度をもった
半導体材料が得られるのは明らかである。
In the example of the pB1-pxCLyl-11 mixed crystal semiconductor shown in the t4g diagram, Ga.4In.
, im8., 18b., and S were used, but similar effects can be obtained by using Ga5b. Other modules PB1-Pxlly
Even in l-Q m mixed crystal conductors, if the laminated structure is selected appropriately, carriers can be transferred and laminated one molecular layer at a time, but regular lamination of up to two molecular layers can also produce a semiconductor with high-speed mobility. It is clear that the material is available.

余      白 \、 次に、合金散乱、空間電荷散乱以外に、さらにイオン化
不純物散乱をも抑制し1高速移動度を可能とする半導体
材料の一実施例について説明する。第1θ図は本例の構
成を説明するための図で、InP基板88上にム1@、
41 Ine、i−のバッファ層89を堆積し、積層部
分としてGaAs 1分子層40とInAs  1分子
層41を交互に積層する。但し、G&A8、InABと
もに不純物をドープしない。
Next, an example of a semiconductor material that suppresses not only alloy scattering and space charge scattering but also ionized impurity scattering and enables high-speed mobility will be described. FIG. 1θ is a diagram for explaining the configuration of this example.
A buffer layer 89 of 41 Ine, i- is deposited, and a single-molecular layer of GaAs 40 and a single-molecular layer of InAs 41 are alternately laminated as a laminated portion. However, neither G&A8 nor InAB is doped with impurities.

さらに不純物をドープしないム1負、sIn拳、sA8
4B附近に移行し、二次元電子伝導層が形成される。
Mu1 negative, sIn fist, sA8 without further doping impurities
The phase shifts to around 4B, and a two-dimensional electron conductive layer is formed.

このチャネル中の電子は合金散乱、空間電荷散乱及びイ
オン化不純物散乱に殆ど影響されないため高達移動度が
実現できる。勿論、ム1・、BIn・、5人842.4
8の代りに、ムlAs!Iを1分子層ずつInAgを1
分子層ずつ堆積しても高電子移動度が実現できる。
High mobility can be achieved because electrons in this channel are hardly affected by alloy scattering, space charge scattering, and ionized impurity scattering. Of course, M1・, BIn・, 5 people 842.4
Instead of 8, MlAs! One molecular layer of I and one layer of InAg
High electron mobility can be achieved even by depositing one molecular layer at a time.

本発明の半導体材料により得られる効果を挙げると、 混晶半導体の組成と平均的な組成が等しい半導体材料と
、当該混晶の構成半導体を1分子層ないし2分子層の巣
位で規則的に積層することによって構成“すると、混晶
に特有な合金散乱及び空間電荷散乱が、この半導体材料
中においては効かないため、この半導体材料中のキャリ
ヤ移動度を大巾に増大させることができる。
The effects obtained by the semiconductor material of the present invention are as follows: A semiconductor material whose average composition is the same as that of a mixed crystal semiconductor, and a constituent semiconductor of the mixed crystal are regularly arranged in one or two molecular layers. When configured by stacking layers, alloy scattering and space charge scattering, which are characteristic of mixed crystals, are not effective in this semiconductor material, so carrier mobility in this semiconductor material can be greatly increased.

り及びそれを用いた集積回路やオブトエレクトロラクス
素子及びそれを用いた集積回路等に応用でき、その性能
向上に貢献するところ大なるものがある。
It can be applied to electronic devices and integrated circuits using the same, obtoelectrolux devices and integrated circuits using the same, and greatly contributes to improving their performance.

4I% 図面の簡単な説明 第1 v!J Lt In・、@Qa・、凰Asの電子
移動度の温度依存性を説明する図(T、Katoda、
 7.08JKL and T。
4I% Brief explanation of drawings 1st v! A diagram explaining the temperature dependence of electron mobility of J Lt In・, @Qa・, and As (T, Katoda,
7.08JKL and T.

Yl−qM四元混晶半導体の代表例の一つの構成略図、
第、S−#Aは本発明を平均的組成がIn・、BGa@
 、 hムSである半導体材料に応用した実施例の構成
略図、第6図はIn・、+mGa5.%ム8に対するバ
ッファ層である半導体材料に適用した実施例の構成略図
、イオン化不純物散乱を抑制し、InAa/GaAs檀
層部分中のキャ積層移動度の高速化を実現した半導体材
料の実施例の構成略図である。
A schematic diagram of a typical example of a Yl-qM quaternary mixed crystal semiconductor,
No. S-#A has an average composition of In・, BGa@
, hmS is a schematic diagram of the construction of an embodiment applied to a semiconductor material, and FIG. A schematic diagram of the structure of an example applied to a semiconductor material that is a buffer layer for % M8, and an example of a semiconductor material that suppresses ionized impurity scattering and achieves high-speed carrier layer mobility in the InAa/GaAs layer portion. This is a schematic diagram of the configuration.

図中、1は光学7オノン散乱による電子移動度、2はイ
オン化不純物散乱による電子移動度、8は空間電荷散乱
による電子移動度、4は合金散乱による電子移動度、5
は1〜4の散乱を考慮して得られた移動度の計算値(黒
点と実線6は実験値)、7はエピタキシャル成長用&&
、8はバッファ層、9は、■の1分子層、10はム、B
t−tXの1分子層、llは■の1分子層、13はBX
の1分子層、18はムrnsci−r−aXの1分子層
、14は子層、21はG&A8の1分子層、22はIn
P基板、層、80はInAg 1分子層、81はIn8
b 1分子層182はGa8b 1分子層、88は基板
、84はバッファ層、85は積層部分、86は積層部分
よりバンドギャップが広く、かつ格子定数の等しい不純
物In・0%ムS層である。
In the figure, 1 is the electron mobility due to optical 7-onone scattering, 2 is the electron mobility due to ionized impurity scattering, 8 is the electron mobility due to space charge scattering, 4 is the electron mobility due to alloy scattering, and 5
is the calculated value of mobility obtained considering scattering of 1 to 4 (black dots and solid line 6 are experimental values), 7 is for epitaxial growth &&
, 8 is a buffer layer, 9 is a single molecule layer of ■, 10 is a mu, B
One molecular layer of t-tX, 11 is one molecular layer of ■, 13 is BX
18 is one molecular layer of Murnsci-r-aX, 14 is a child layer, 21 is one molecular layer of G&A8, 22 is In
P substrate, layer 80 is InAg 1 molecule layer, 81 is In8
b 1-molecular layer 182 is a Ga8b 1-molecular layer, 88 is a substrate, 84 is a buffer layer, 85 is a laminated portion, and 86 is an impurity In/0% S layer with a wider band gap than the laminated portion and the same lattice constant. .

71図 第2図 矛3図 7f5  図 76図 78図 才9図 才10図 第11図 籟居 格旅叡山Figure 71 Figure 2 Spear 3 7f5 diagram Figure 76 Figure 78 age 9 age 10 Figure 11 Lazy house Mount Eizan

Claims (6)

【特許請求の範囲】[Claims] (1)  半導体又は絶縁体基板上に、バッファとなる
半導体又は絶縁体を堆積し、前記半導体又は絶縁体の上
に組成の異なる半導体を1分子層単位又は3分子層単位
でIIL!7Ji的に有限個堆積した積層部分を設けた
ことを特徴とする高移動度半導体材料。
(1) A semiconductor or insulator serving as a buffer is deposited on a semiconductor or insulator substrate, and semiconductors having different compositions are deposited on the semiconductor or insulator in units of one molecular layer or three molecular layers! A high mobility semiconductor material characterized by having a laminated portion in which a finite number of 7Ji layers are deposited.
(2)  特許請求の範囲第(り項記載の高移動度半導
体材料において、積層部分が一種類の半導体から成るこ
とを特徴とする高移動度半導体材料。
(2) A high-mobility semiconductor material according to claim 1, wherein the laminated portion is made of one type of semiconductor.
(3)特許請求の範囲第(1)項記載の高移動度半導体
材料において、積層部分が3櫨類の半導体から成ること
を特徴とする高移動度半導体材料。
(3) A high-mobility semiconductor material according to claim (1), characterized in that the laminated portion is made of a three-layer semiconductor.
(4)特許請求の範囲第(1)項記載の高移動度半導体
材料において、積層部分がダ種類の半導体から成ること
を特徴とする高移動度半導体材料。
(4) A high-mobility semiconductor material according to claim (1), wherein the laminated portion is made of several types of semiconductors.
(5)特許請求の範囲第(1)項記載の高移動度半導体
材料において、バッファとして、互いに組成の員なる少
なくとも一種類の半導体を1分子層単位又は2分子層単
位で規則的に有限個積層して構成したことを特徴とする
高移動度半導体材料。
(5) In the high mobility semiconductor material according to claim (1), as a buffer, at least one type of semiconductor having compositional membership with each other is regularly arranged in a finite number in units of one molecular layer or in units of two molecular layers. A high mobility semiconductor material characterized by being constructed by laminating layers.
(6)  特許請求の範囲第(0項記載の半導体材料に
おいて、不純物濃度が低い半導体から成る積層部分の上
に、この積層部分のバンドギャップよりも広いバンドギ
ャップと、前記積層部分の実効的格子定数と等しい格子
定数とを有する不純物濃度の低い半導体材料を堆積し、
さらにこの半導体材料の上−に、前記不純物濃度の低い
半導体材料にp又はn[にドープした半導体材料を堆積
して構成したことを特徴とする高移動度半導体材料。
(6) Claim No. (In the semiconductor material according to claim 0, a laminated portion made of a semiconductor with a low impurity concentration has a band gap wider than that of the laminated portion, and an effective lattice of the laminated portion. depositing a semiconductor material with a low impurity concentration having a lattice constant equal to
A high-mobility semiconductor material further comprising a p- or n-doped semiconductor material deposited on the semiconductor material with a low impurity concentration.
JP4135482A 1982-03-16 1982-03-16 High mobility semiconductor material Pending JPS58158912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4135482A JPS58158912A (en) 1982-03-16 1982-03-16 High mobility semiconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4135482A JPS58158912A (en) 1982-03-16 1982-03-16 High mobility semiconductor material

Publications (1)

Publication Number Publication Date
JPS58158912A true JPS58158912A (en) 1983-09-21

Family

ID=12606162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4135482A Pending JPS58158912A (en) 1982-03-16 1982-03-16 High mobility semiconductor material

Country Status (1)

Country Link
JP (1) JPS58158912A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154511A (en) * 1987-12-11 1989-06-16 Hitachi Ltd Crystal growth method
US5450934A (en) * 1991-11-26 1995-09-19 Luk Lamellen Und Kupplungsbau Gmbh Friction clutch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J.CRYSTAL GROWTH *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01154511A (en) * 1987-12-11 1989-06-16 Hitachi Ltd Crystal growth method
JP2828979B2 (en) * 1987-12-11 1998-11-25 株式会社日立製作所 Crystal growth method
US5450934A (en) * 1991-11-26 1995-09-19 Luk Lamellen Und Kupplungsbau Gmbh Friction clutch

Similar Documents

Publication Publication Date Title
US8395042B2 (en) Quantum dot solar cell with quantum dot bandgap gradients
US12027588B2 (en) Field effect transistor including channel formed of 2D material
Javaid et al. Thin film solar cell based on ZnSnN2/SnO heterojunction
US20090180215A1 (en) Tunneling magnetoresistive effect element and spin mos field-effect transistor
US6828579B2 (en) Thermoelectric device with Si/SiC superlattice N-legs
JPH054812B2 (en)
CA2530067A1 (en) Semiconductor device including band-engineered superlattice
JPS60111412A (en) Method of growing ge/si semiconductor different type structure
US20200365798A1 (en) Double-channel topological insulator structure, and method for generating quantized anomalous hall effect
TW201044570A (en) Apparatus and methods for improving parallel conduction in a quantum well device
US20200365804A1 (en) Multi-channel topological insulator structure, method for making the same, and electrical device
US20150144882A1 (en) Controlled epitaxial boron nitride growth for graphene based transistors
JPS62229894A (en) Monolithic semiconductor structure of hetero-junction bipolar transistor and laser
JPS60100424A (en) Doping method and its application
US20200365805A1 (en) Topological insulator structure having insulating protective layer and method for making the same
Ni et al. Status and prospects of Ohmic contacts on two-dimensional semiconductors
US20240038903A1 (en) Two-dimensional material-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices
JPS58158912A (en) High mobility semiconductor material
KR102429848B1 (en) Method for manufacturing three-dimensional laminated structure, three-dimensional laminated structure manufactured thereby and photo sensor using the same
Pan et al. Realization of dirac cones in few bilayer Sb (111) films by surface modification
JPS5963769A (en) High-speed semiconductor element
US20230352538A1 (en) Applications of two-dimensional silicon carbide as the channel layer in field-effect transistors
KR101456518B1 (en) Crystal and laminate
Guerrero-Sánchez et al. Ab-initio study of the Y adsorption and YN formation on the GaN (0001¯): Diffusion pathways and stability
TW200807699A (en) Semiconductor device including a floating gate memory cell with a superlattice channel and associated methods