JPS5815494A - Control circuit for pulse motor - Google Patents

Abstract

PURPOSE:To perform control a pulse motor with a high speed and high resolving power by a method wherein exciting conditions of the respective phases of the pulse motor are controlled to be in the staircase type consisting of steps of a large number. CONSTITUTION:Outputs are generated in order at terminals QA, QB, QC on the output side of a counter 4 every time of coming of the reference clock signal CK, and a decoder 9 outputs in order outputs 0-7 according to outputs of the counter thereof and outputs of a phase change-over wave form generating circuit 21. Outputs of the decoder 9 are inputted into operational amplifiers 17-20, and by applying outputs thereof to transistors Q1-Q4 through switches S1-S4 to be made to ON, OFF by outputs of the phase change-over wave form generating circuit 21, the staircase type waves are applied to the A phase - the D phase of the pulse motor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control circuit for a pulse motor, and particularly to a control circuit for a pulse motor that can utilize a high-frequency reference clock signal and that enables minute angle operation control of the pulse motor. .

Pulse motors are widely used in devices that accurately position movable bodies at predetermined positions in response to input signals, such as X-Y stationary printer drive units.

In such devices, the resolution (the amount of movement per pulse of the input reference clock signal given to the pulse motor)
In order to increase the moving speed of the movable body without reducing the dl,
Generally, the frequency of the reference clock signal must be increased.

However, in order to increase the frequency of the reference clock signal,
A pulse motor with excellent high-speed response must be used, which has the drawback of increasing costs. Furthermore, even if a pulse motor with high response characteristics is used, allowing for an increase in cost, if the frequency of the reference clock signal is increased, so-called slow-up control is used, in which the frequency is sequentially shifted from a low frequency to a high frequency at startup. Is required. Therefore, a complicated control circuit is required for this purpose, resulting in an increase in the cost of the -J6.

If you look at pulse motors from a mechanical perspective, there are two ways to increase the operating resolution: using a high-resolution pulse motor, or using a gear-down method using gears, etc.
The former method does not increase the cost, while the latter method not only increases the cost but also causes backlash (backlash) caused by the gears, which reduces the speed.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, improve the frequency of the reference clock signal and the mechanical resolution of the pulse motor, and enable high speed and high resolution, regardless of the response characteristics and resolution of the pulse motor itself. The object of the present invention is to provide a control circuit for a pulse motor.

In order to achieve this object, the present invention is characterized in that the excitation state of each phase of the pulse motor can be controlled in a staircase waveform (microstep) consisting of a large number of steps, and the control circuit thereof can also be realized at a low cost. It is said that

Before describing embodiments of the present invention, the drawbacks of conventional pulse motor control methods will be described.

The first IJα) (b) shows a control circuit and a manner in which a four-phase pulse motor is operated using a two-phase excitation method. In the conventional control system, the current flowing through the windings of each phase of the pulse motor is controlled to be on/off by switching between 101 and a predetermined value. As shown in the figure, the on/off state of each phase changes, and the rotor of the motor receives an attractive force (straddle repulsive force) from the phase that is in the on state, and rotates stepwise by a predetermined angle to perform positioning. Therefore, when the frequency of the reference clock signal becomes high and the pulse interval becomes narrow, the rotation of the rotor at each predetermined angle becomes unable to follow the pulses. Therefore, in order to increase the frequency of the reference clock signal and perform high-speed rotation, it is necessary to improve the characteristics of the motor itself so that it has excellent high-speed response characteristics with a short rotation time for rotating a predetermined angle in response to one pulse of the input clock signal. A pulse motor must be used, and as mentioned above, the cost of the pulse motor is also high.

Next, embodiments of the invention will be described with reference to the accompanying drawings.

Fig. 2 shows a control waveform diagram of a pulse motor using the microstep control method of the present invention, Fig. 3 shows an embodiment of the control circuit of the invention, and Fig. 4 shows an operation sequence of the control circuit of Fig. 3. FIG. 5 shows an equivalent circuit of the main part of the control circuit of FIG. 3, and FIG. 6 shows another embodiment of the control circuit of the present invention.

In FIG. 2, in the control method of the present invention, the current flowing through the windings of each phase of the pulse motor is controlled stepwise in eight levels, for example, as shown in FIG. 2 (0) to (r). This level is changed for each pulse of the reference clock signal. Therefore, the pulse motor rotates stepwise by a predetermined angle corresponding to each of the 8 levels every time the reference clock signal pulses, and when it reaches 8 steps, the conventional method shown in Figure 1 rotates. Control is performed so that the rotation angle is the same as that obtained in response to one pulse of the reference clock signal. Therefore, the frequency of the reference clock signal is 1. ! 86, the resolution can be improved and the speed can be increased.

FIG. 3 1l-1 shows a control circuit that realizes the control waveform shown in FIG. 2. 1 is an inverter, 2.3 is a Nando game.

-t, 4. When the UP large input clock is input to the h up/down counter, an addition count is performed, and when a clock is input to the dovm input, a subtraction count is performed and a galley CA and borrow BO signal are output.

5 to 7 are exclusive OR gates, 8 is a Nant gate, and a 9-digit decoder decodes, for example, an input binary coded octal code and generates a Voa voltage at its output side O to 7.

10 and 11 are the first. Alternative or gate, 12 and 13 are D'! Flip-flop, 14.15 is and gate,
16 is an OR gate, 17 to 20 operational amplifiers, 21 is a phase switching waveform generation circuit, Q1 to Q4 are transistors, D+-
D4 is a Zener diode, and 81 to S4 are analog switches, which switch the phase in which the pulse motor is excited by the output generated by the phase switching waveform generating circuit 21.

Next, the operation of the control circuit of FIG. 3 will be explained with reference to the waveform diagram of FIG. 2 and FIG. 4.

When the clock CK shown in (cL+) and the rotation direction instruction signal CW/ccw shown in (b) in FIG. The counter 4 performs an octal down count using the octal ``γ up count CCw signal, which is a penalty signal.Also, when the content changes from 7 to OK during up counting, the counter 4 outputs a carry signal CA.
1. ．． When the count goes down by 1 from 0 to 7, a signal BO is generated (FIG. 2(f)). In this way, each time the reference signal CK comes, the outputs shown in FIG. 4 are sequentially generated from the output sides QA, Qll, and Qa of the counter 4 as shown in FIG. in/
/iM o I is represented by φ). These outputs are given to one input of exclusive or gates 5 and 6.7, respectively, but the other inputs are determined by the output from the or gate 16 so that the outputs of exclusive or gates 1 and 5.6.7 are given to Iol.
or 11' is determined. In this case, the output of the OR gate 16 is determined by the conditions of the CW/ccw input and the signal output from the counter 4 via the Nandt gate 8. That is, exclusive or gates 10, 11 . The output determined by the phase switching waveform generation circuit 21 consisting of D-type flip-flops 12 and 13 is applied to the OR gate 16 via AND gates 14 and 15, and as shown in FIG. Since it changes when the pulse reaches 8, the output of the OR gate also depends on the logic in the phase switching waveform generation circuit 21. That is, at clock pulses 0 to 7, the output of gate 16 1d'11
11 Clock pulses 8 to 15 teha"o1. Therefore, exclusive OR) At 5, 6.7, exclusive OR logic is taken between the output of gate 16 and QA, Qll, and QO, and A and B of decoder 9 , C inputs are changed and given as shown in FIG.

Resistors R8I to Rs are connected to decode outputs 0 to 7 of decoder 9.
s and Rs l' to Rs s' are connected, but Rsl and Rs1', Rs27R82',...R
Bs and Rsa' have the same resistance value but are connected in reverse order, and their common terminals R point and 8 points are connected to operational amplifiers 17 to 8.
2o are respectively applied to negative input terminals. Therefore, every time the reference clock pulse CK is supplied, the output from the decoder 9 is connected to the output side of the operational amplifiers 17 to 20 through the resistors Rs 1 % Rs s , R81'-Rs
A summed output is generated via s'. The details will be explained using the equivalent circuit shown in FIG.

In FIG. 5, if the above-mentioned resistors Rs1 to Rsa are set as Rsn and Rss'xRss' is set as Rsn', then the output voltage Voxt of the operational amplifiers 17 to 20 can be calculated using the well-known circuit calculation as feedback resistors Rf and Rf'. From (input voltage V
i%), vo,, = -n x Vtn across R57゜■...t = -''' normal pressure drop V,
is the value obtained by subtracting Vi? L=■c6-V7]
Since this voltage drop ■p is less than 0.5V in one line, Voc-Vp is almost constant and the operational intensifier 1.7
．． 18 output voltage VoutAB, that is, the output voltage of A and B phases is V(+1ZtAB = 4'x (Vcc
-Vp) Output voltage VO of operational amplifier i9.20
1LtoD1, that is, the output voltage of c and D phases is Vout'=-"l-x (Vea-Vp)OD
Ran', and its level is determined by the resistor R85 ('f 1? 8? l') connected to the terminal on the output side of the decoder 9 and the feedback resistor U ('4 taba R/). Therefore, the analog switches 81 to S4 fN connected to the output sides of the operational amplifiers 17 to 20 generate the waveforms generated by the phase switching waveform generating circuit 21 described above as shown in FIGS. When switching by on/off output,
Step outputs as shown in (o) to (r) in Fig. 2 are obtained from the calculation tfl (additional step outputs (Fig. 2 (g) to (j)) outputted from the converters 17, 18, and 19.20. can be generated, i.e. when the reference clock pulse is 0
7, while addition is being performed on one side depending on the values of the input resistances Rs1 to Rss and Rs1' to R88' of the operational amplifiers 17 to 2o, addition in the opposite direction is being performed on the other side. Reverse calculations are performed for reference clock pulses 8 to 15, and step waves as shown in FIG. 2(o) to (.tau.) are applied to phases A to D of the pulse motor. Therefore, in the pulse motor according to the control method of the present invention, the rotor is rotated in small steps by the drive signal that changes stepwise together with the reference clock pulse, so that it can be started quickly and follows the frequency of the reference clock signal well. be able to. Gao, Zener diodes D1-D4
The function of is to prevent the back electromotive force generated from the pulse motor from destroying the transistors Ql to Q4 that amplify the output signals from the operational amplifiers 17 to 20. be.

As can be seen from the above, another effect of the present invention is that by connecting two sets of resistors to the output of one decoder 9, the number of decoders can be reduced, and the supply voltage Vac of the decoder can be relatively reduced. Freely selectable (normally 3V~
(approximately 15 V), so it can be constructed using a CMO8 type integrated circuit. Therefore, the input voltage Vt of the operational amplifier
n can be determined relatively freely, and the resistance groups Rs l to R8g,
The values of Rs s' to Rs m' can also be selected over a wide range.

The output of the decoder 9 that is not turned on yet; M;
is at the ground level, so for the operational amplifiers 17 to 20 whose inputs normally operate at
Even if it is applied to the operational amplifier via ', it has almost no effect.

FIG. 6 shows another embodiment of the control circuit of FIG. 6th
In the figure, the reference numbers used for major parts are the same as in FIG. 3. The difference between the circuit shown in FIG. 6 and the circuit shown in FIG. 3 is that the circuit shown in FIG.
A power supply of -12V to 24V is applied to the common terminal side of ~D4, and two sets of resistor groups Ra1~R on the output side of the decoder 9 are connected.
ss and R81' to Rs a' to the negative polarity input terminals of each pair of operational amplifiers 17 and 18, and 19 and 20. In the circuit, transistors Q1 to Q
The point is that 10 to 24 V is used as the collector power supply of 4.

Therefore, in Fig. 6, the resistance Rs1% Rss, R
The common connection points R and S of at' to Rss' are respectively provided with the negative polarity input terminals of one operational amplifier 22 and 23, and the output of each operational amplifier is connected to a pair of operational amplifiers 17, 18 and 19., respectively. It is given to 20 people.

These outputs are turned on and off by analog switches 81""84, but since the operation is substantially the same as that of the circuit shown in FIG. 3, further detailed explanation will be omitted.

As described above, in the circuit according to the present invention, even if the frequency of the reference clock signal increases, the rotation of the pulse motor can follow the rotation at high speed, and the pulse motor can be operated with high precision and high resolution with a relatively simple circuit configuration. You can wander around.

In the present invention, the case has been described in which the reference clock signal changes from gradual increase direction addition to gradual decrease direction addition (or from gradual decrease direction addition to gradual increase direction addition) at the 8th reference clock signal, and phases A to 'D also change accordingly. It goes without saying that the number can be n, which is an arbitrary number greater than or equal to 2.

[Brief explanation of the drawing]

Figures 1 (α) and (b) are the excitation sequence and drive circuit of a 4-phase 2-excitation pulse motor using the conventional method, Figure 2 is a control waveform diagram of a pulse motor using the microstep control method of the present invention, and Figure 3 is a diagram of the present invention. An Embodiment of the Control Circuit According to the Invention - FIG. 4 shows the operation of the control circuit of FIG. FIG. 5 shows an equivalent circuit of the main part of the circuit in FIG. 3, and FIG. 6 shows another embodiment of the control circuit according to the present invention. In the figure, 1 is an inverter, 2 is a Nant gate, 4 is an up/down counter, 5 is an exclusive OR gate, 8 is a Nant gate, 9 is a decoder, 13 is a D-type flip-flop,
15 is and gate, 16 is or gate, 17-20,
and 22, 23 are operational amplifiers, 81 to S4 are analog switches, Q1 to Q, 4 lZt l-transistor 1
．． DI %D4 indicates a Zener diode. Patent applicant: Hiroshi Mori, μP patent attorney representing Alps Electric Co., Ltd.

Claims (1)

[Claims] An up/down counter which receives a control signal consisting of a clock signal and a rotation direction instruction signal, performs counting according to the clock signal, and switches between up counting and down counting according to the rotation direction instruction signal; A phase switching waveform generation circuit receives the carry signal, borrow signal, and rotational direction instruction signal to determine excitation of the pulse motor, and a stepwise wave generation circuit generates a stepwise waveform generation circuit in accordance with the output of the up/down counter. The stepwise wave generating circuit includes a decoder receiving the count output of the up/down counter, a plurality of resistors connected to each output of the decoder, and an operational amplifier, The step wave level of the excitation signal to the pulse motor is determined by the ratio of the resistance corresponding to the output and the feedback resistance of the operational amplifier, and the excitation state for each phase of the pulse motor is controlled in the step wave form. A control circuit for a pulse motor characterized by: