JPS5815319A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To count a long time with an oscillator only with small capacitance of a capacitor, by counting the number of times of repetition of a saw-tooth wave. CONSTITUTION:When an input signal IN is applied from an input terminal 7, a counter 26 is reset. The output of an inverter 27 is inverted to H level. A voltage V1 is increased in accordance with the constant of a time constant circuit 2. When the voltage V1 reaches a reference voltage, the output of a level detector 3 is inverted to H level. As a result, a flip-flop 20 is set. Thus, a driving circuit 5 is turned on and the output S of the level detector 3 goes immediately to L level. Then, the flip-flop 20 is again inverted to reset state. Thus, the number of pulse signals generated with the flip-flop 20 is counted at the counter 26. When the count reaches a set value, the output pulse is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generation circuit with variable pulse width.

BACKGROUND ART Conventionally, a monostable multipipelator (hereinafter abbreviated as mono-ilti) has been generally used as a pulse generating means with variable pulse width.

Figure 1 shows the conventional circuit, and Figure 2 shows the waveforms of the main parts of Figure 1. In Figure 1, 1 is an IC Yasuko, 2 is a time constant circuit, and 3 is a time constant circuit.
4 is a level detector, 4 is a reference voltage source, 5 is a drive circuit, 4 is a control circuit, and 7 is an input terminal.

In such a circuit KjP, the time constant circuit 2 has a variable resistor 8.
．． Resistance9. It consists of 10 capacitors, and 3 level detectors.
are transistors 11-14. It is composed of a resistor 15.14 and an inverter 17, and the pace voltage of the transistor 11, that is, the voltage r of the IC terminal 1, is the transistor 120.
When the base voltage becomes higher than the reference voltage tag, the output S of the inverter 17 becomes the logical I level. The reference voltage source 4 is composed of resistors 18 and 19, and outputs a voltage value determined by the division ratio of the resistors 18 and 19. The control circuit 6 is composed of an RS flip-flop (hereinafter abbreviated as RE-FF) 20,
The output S of the level detector 3 is connected to the S input, the input signal IN is connected to the R input, and the output Q is applied to the next stage drive circuit 5. Further, the drive circuit 5 includes resistors 21 and 22 and a transistor 23. A signal Q is output from the output terminal 24.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. First, during normal operation, B5-FF20 are in the set state. Therefore, its output Q is I level.

The transistor 25 is in the on state 1aK, and the terminal voltage r1 is at the L level. Now, when the input signal IN is applied from the input @y, the R5-#2Q beam is set, the output Q goes to L level, and the run raster 25Ixt turns off tm. As a result, the terminal voltage scale gradually increases due to the time constant circuit 2.

When the terminal voltage ^ reaches the reference voltage V, the level detector 5
The output S of RE-F is inverted from L level to H level, and
F20 is returned to the set state, and as a result, the transistor 23 is turned on, the terminal voltage r, returns to the L level, and the signal S returns to the L level.

At this time, the pulse width 7'j is generally set shorter than the period 9 of the input signal IN, and the signal Q of the circuit shown in FIG.
, S, and desks are k, respectively, as shown in FIG.

However, in the conventional pulse generation circuit described above, when trying to generate a low frequency pulse, the time constant circuit 20
The disadvantage was that the time constant had to be increased, which increased the external capacitance 10, which was a major hindrance for Jakuden crystals aiming to be compact and lightweight. Furthermore, when changing the pulse width by a large amount, simply changing the resistance value is not sufficient, and generally it is necessary to change the capacitance value in parallel, which has the disadvantage of requiring a complicated and large-scale external circuit. There was.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, and to easily switch pulse widths of arbitrary length without switching the resistor in the capacitor. ! can be expressed. It is an object of the present invention to provide a pulse generation circuit suitable for IC implementation using a small capacitance.

In the present invention, the silver wave is repeatedly generated, the number of repetitions is counted by a counter, and when the number of repetitions is counted up to a set value of the counter, the repeating operation is stopped. The present invention is characterized in that the pulse width can be arbitrarily and easily changed by obtaining a pulse width signal and then changing the set value of this counter.

One embodiment of the present invention is shown in Fig. 3, and the main waveforms of the same figure are shown in Fig. 4. In Fig. 3, parts having the same functions as in Fig. 1 are given the same reference numerals. . Here, 25 is a level detector, 28 is an AND circuit, 29 is an inverter, 1 time constant circuit 2, level detector! , 25. Reference voltage source 4. Drive circuit 5. A silver wave generation circuit is constituted by the RE-FF20, ANI) times 11i 28, :tr Yohi imperter 29. Further, 27 is an inverter, which functions to control the positive feedback of the silver wave generation circuit. Sara K.

26 is a counter that counts the number of repeated operations of the silver wave generator.

Next, the operation of this embodiment having the above configuration will be explained using FIG. During steady state, RE-FI'20 is in a set state and its Q output is at H level.

Further, the Qc output of the counter 26 is at I level.

Therefore, the output of the inverter 27 is at L level. As described above, the q output of the RE-FF 20 is at the H level, and the output terminal N voltage of the drive circuit 5 is at the V@+tL level. Therefore, the output S of the level detector 5 and the output A of the level detector 25 are both at the KL level. At this time, the output signal OUT output from the 11% output terminal 24 is at H level.

Now, when the input signal IN is applied from the input terminal 7, the counter 26 is reset, and its output Qc is inverted to low level and pel, and at the same time, the output of impark 27 is inverted to high level. At this time, looking at the AND 28 Tsuru input, RE-F
The Q output of F20 is H level, and the level detector 25 is L level.
The output of the inverter 29, which inverts the level output, is also at H level. Therefore, when the Qc output of the counter 26 is inverted to L level, the output R of AND 28 becomes H level.

As a result, the output Q of RE-FF2a is at L level jc.

The drive circuit 5 becomes off-state 111, and the terminal voltage r begins to rise. Level detector 250 reference voltage P″eL is approximately 1
Since the output A of the level detector 25 is set to a small value such as r, the output A of the level detector 25 is inverted immediately after 11 and becomes H level.
, the output of the inverter 29 is inverted to L level.

Next, the waste voltage ^ rises according to the constant of the time constant circuit 2, and when the voltage V reaches the reference voltage V@IK, the level detector 3
The output S of is inverted in Hv level.

Secondary, 1 As a result, RE-FF20 becomes set state, and its Q
The output becomes H level. Therefore, the drive circuit 5 becomes on-state IIK, and the terminal voltage ^ begins to fall. ``As a result, the output S of the level detector 3 immediately becomes the KL level.

Now, when the voltage ^ falls and finally reaches the reference voltage r·LK of the level detector 250, the output A of the level detector 25 is inverted to the L level and the output of the inverter 29 is inverted to the I level. At this time, all inputs of AND2B become I level, and RE-
The FF 20 is again inverted to the reset state. As a result, the drive circuit 5 becomes trapped in the off state, and the terminal voltage begins to rise again.

As described above, the KRE-FF 20 repeats setting and resetting alternately, and at the same time, the terminal voltage ^ also repeats rising and falling. At this time, the output S of the level detector 3 is input as the trigger signal T of the counter 26. Therefore, counter 2
6 counts the number of input signals S, and when the counted value reaches a set value (for example, N), its output Qc is inverted to I level.

Therefore, as shown in FIG. 4(d), the signal 5
When rJN is applied, output Qc becomes I level. As a result, the output R of the AND circuit 28 is
It becomes @KL level regardless of the output of 9. On the other hand, B5
-FF2o is set to the Nth signal SK, and the drive circuit 5 is turned on. Therefore, the terminal voltage r, decreases. However, since the output of ANI)@path 28 is always at L level, the terminal voltage is set to the reference voltage V@
Even if LK is reached and the output A of the level detector 25 changes from 1 to L level, B5-FF2o will not be reset again.

As described above, the terminal voltage ^ repeatedly rises and falls due to the application of the input signal IN, and when the number of repetitions reaches the set value, the terminal voltage r becomes the L level and returns to its original state! IIK back.

At this time, the pulse width of the output signal OUT obtained at the output terminal 24 becomes KTn as shown in FIG. This pulse width Tj is determined by 4. without changing the capacitance or resistance in the time constant circuit 2. This can be changed simply by changing the set value of the counter 26. Furthermore, the capacitor has a small capacitance value, and is preferably integrated into an IC.

In the above embodiment, as the T input of the counter 26, the I/
The output signal S of the bevel generator 3 was used.

In place of this, a level detector 25. The same effect as the four embodiments can be obtained by using the output signal of the inverter 29 or R5-FF20.

FIG. 5 shows another embodiment of the present invention, in which the T of the counter 26 is
This is an example in which the output signal A of the Sepel detector 25 is used as an input.

In the figures, parts having the same functions as those in FIGS. 1 and 3 are given the same reference numerals. The configuration of the main parts of this embodiment is almost completely different from the first embodiment shown in FIG. The points are T input ttctrt of counter 26, output t of p2t, R5-1#tofJs, and the output of AND circuit 30 is connected to the input.

The input of the AND It path sO is the output S of the level detector.
This is the point where the output of the inverter 27 is connected. Here, the output of the counter 26 has QI and (h, and sr
It is configured to be switched by s.

In this embodiment, 1 time constant circuit 2. Level detector5.
25. Reference voltage source 4. Drive circuit 5°RE-FF20,
A wave control generation circuit is constituted by an AND circuit 28, an upper 28, and an inverter 29, and the inverter 27 and the AND circuit 3
0 constitutes one control path for controlling the positive feedback of the wave suppression generation circuit.

Next, the operation of this actual example will be explained using FIG. The operation from the time the input signal IN is applied to the input terminal 7 until the terminal voltage repeatedly rises and falls is the same as the operation of the first embodiment shown in FIG. However, the difference is that the counter 26 is triggered by the output of the inverter 2t.

Now, assume that the terminal voltage ^ repeats rising and falling operations a predetermined number of times N times, and the Nth trigger signal (output of the inverter 29) is applied to the counter 24.

Then, the Q output of the counter 24 becomes H level, and the output of the inverter 27 becomes L level.

At the same time, xs-FF2o is in a reset state, its Q output is at L level, and the IP drive circuit is in an on state. As a result, the terminal pressure begins to rise again. However, AND IIl road 3 route 0 inverter 27
Since it is closed by the L level output of the RE-FF 20, even if the terminal voltage ^ reaches the reference voltage V@IK and the output signal B of the level detector 3 becomes H level, the state of the RE-FF 20 does not change.

In other words, as the terminal voltage continues to rise, it tries to reach the saturation voltage.

At this time, when the primary input signal IN is applied, the Q1 output of the counter 26 is inverted and inverts! The output of 27 becomes I level. Therefore, the output of the AND I circuit 3° becomes H level, putting the RE-FF 20 in the set state. As a result, the drive circuit 5 is turned on and the m-child voltage V instantaneously reaches the KL level.

Next, an example of the counter 26 used in each of the embodiments of the present invention described above is shown in FIG. 7, and the main liquid type of the same figure is shown in FIG.
In FIG. 7, gK is shown.

51 is the Dan counter, 52 is! Trix m@, 1m.

! 4 is RE-FF, and QJF-QJF is Q in Figure 5.
Compatible with c-Qck. It was. The reset signal Rc and the trigger signal T are input to respective terminals of the direct II% stage counter 51.

Now, in the steady state m, as mentioned above, the output (h ktH rehe hK b la, 19 RE -F
F 55, 54 are in set ll#c.

At this meeting, when the input signal IN is applied to the input 1117 and the set signal Rc is input to the 1% step counter 51, each output Ql @Q鵞+...-"Qn of the step counter 31 becomes L level. When the i-trix circuit 32
-FF 55 K is supplied with the 9-j bit signal R, and its output Qy is inverted to L level. As a result, the terminal voltage V and Izt rise and fall repeatedly as described above.

Trigger signal T is repeatedly input. When the count value of the step counter 31 reaches N (≦xt&-1), the matrix circuit 32 outputs the set signal SJI and RE
-FF5B becomes set state. As a result, the output QI is inverted to the level, and as described above, the terminal voltage becomes L level and the operation is stopped.

In other words, jllllll (Rinoyo K, reset signal Rc
Pulse width 1 from the time of input to the N11th trigger signal T
A signal having a set is obtained.

On the other hand, the reset signal RJ1.BS-FF s<. The set signal SN is configured so that the -v trix circuit s2 can select an arbitrary signal from the trigger signal T, that is, the set value of the counter 26 can be switched. For example, as shown in Figure 6 (f) to 0), the reset signal R is set to the first signal T (0≦L<N).
By setting the *t signal 5xtl*th (L (ffi≦N), a signal having a pulse width switching smaller than the pulse width T1 can be obtained. Note that the pulse width T, and Tj
! It goes without saying that the relationship can be changed to any arbitrary relationship by setting the matrix circuit 52.

As described above, according to the present invention, when a large number of pulse widths are to be changed, it is possible to easily change a large number of pulse widths by changing the set values of colors without having to change the capacitance as in the prior art. . In this case, these pulse widths can be accurately and easily set at any ratio.

In addition, the number of elements used is small, and large capacitance is not required.
Moreover, since it has a simple configuration, there is no need for an increase in IC bins or external circuits, making it suitable for IC implementation.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional pulse generation circuit, Figure 2 (-)
~(d) is a main part waveform diagram for explaining the operation of FIG. 1,
Fig. 5 is a schematic diagram of an embodiment of the present invention, 1114 Fig. 0
~(A) is a waveform diagram of the main part of the third WJ, FIG. 5 is a block diagram of another embodiment of the present invention, a waveform diagram of the main part of the fourth crystal T5, and FIG. A block diagram showing a specific example of the counter in the figure, FIG. 8 (-) to (
1) is a waveform diagram of the main part of FIG. 2・・・・・・・・・Time constant circuit 5.25・・
・・・・Level detector 4・・−・−・・・・・Reference voltage source 5・・・・・・・State circuit 20・・・・・・−・・・RE−FF
(12) 26−−−−−−−“°
°”fyyl (b)51---
-------- 8-stage counter 52-...*6*#a
e Matrix circuit (s(d> M 1 Fig.

Claims (2)

[Claims] (1) A sawtooth wave generation circuit, a counter for counting the number of repetitions of the sawtooth wave generation circuit, and a control circuit for controlling feedback of the rust liquid generation circuit based on the count value of the counter, and the counter The signal input to the control circuit triggers the -wave generation circuit to start repetitive operation, and when the counter reaches a predetermined set value, the output signal of the control circuit causes the cough sawtooth generation circuit to operate. 1. A pulse generating circuit characterized in that the pulse generating circuit stops and its output signal is held in an initial state 1aK inverted. (2) Level detection means for which the #ItIL generation circuit detects two levels, high and low; a flip-flop that is set and reset by the output of the level detection means; a drive circuit that is turned on and off by the output of the flip-flop; and a time constant circuit connected to the level detection means and the test drive circuit. (3) The pulse generating circuit according to claim 1 or 2, wherein the pulse width of the output signal is changed by changing the setting value of the counter.