JPS58152536A - Computer type electric eye position drawing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

This invention relates to a computerized electrical eye position description system. More specifically, the present invention relates to a system that performs an electric eye position depiction test, automatic processing of the test, and automatic processing of the test results. Automatic management of the test may be performed either directly by an operator or indirectly by automatic control of a computer program. For a long time, the technique of electrooculography (EOG) or electronystagmography has been used to obtain information useful in the diagnosis of a variety of patients, particularly those complaining of balance disorders. Such information is generally obtained by providing visual and vestibular stimulation to the patient and observing the patient's eye movements. Sometimes these are the only physical evidence that supports a patient's complaint, and they provide the doctor with an anatomical clue to the affected area. Initially, doctors look directly into the patient's eyes and monitor eye movements.
1. Ta. However, this method often misses important points because it does not prevent patients from fixating their gaze. Certain types of nystagmus can be effectively prevented by fixating the gaze. There are several ways to overcome this drawback, but EOG has been the easiest for doctors to use. EOG has been widely used for psychological and ophthalmological research. Because it has been used extensively in the study of nystagmus, it gradually became better known as a nystagmus recorder, even though it was also used to record other eye movements. There are many ways to arrange the electrodes, but clinically it is common to use two electrodes bilaterally, one on the right temple and one on the right temple.
One pair of electrodes is placed on the left temple to monitor horizontal eye movements, and another pair of electrodes are placed above and below one eye to see vertical movements, with the other electrode as the base point. or a standard point), usually placed on the forehead. When observing eye movements with such electrode placement, a major problem with conventional methods arises from the need to maintain a constant relationship between the center position of the eye and the measured electrical variable (e.g., zero voltage). If measurements are continued for a while with the electrode in this position, voltage deviations will occur. That is, the measurement of the measuring device changes so that it no longer corresponds to the gastrointestinal voltage at the center of the eye, but instead shows a specific value known as the offset voltage. This phenomenon is obviously detrimental to the accuracy of eye movement measurements. Typically, such electrode measuring devices are equipped with an amplifier (or preamplifier), and in order to eliminate voltage deviations, there is no conventional method other than manually adjusting the amplifier to zero. There wasn't. This method provides coarse adjustment at best and does not provide the fine adjustment needed for very accurate measurements. No matter how regularly the manual adjustment is repeated, it cannot compete with the efficiency of continuous and automatic zero adjustment to eliminate misalignment. As mentioned above, eye movements can be recorded by attaching small electrodes to the patient's head. EO measures eye movements in horizontal and vertical directions using electrodes placed on the head.
It is possible to measure G and afterglow. In this way,
The patient's eye movements and visual responses are recorded during the test. Typically, six ocular and balance tests are performed: (1) Gaze test (2) Sudden movement reaction test (3) Follow-up test (4) Visual motor test (5) 'a fever nystagmus test (6) Visual evoked response The above tests have traditionally been performed piecemeal. done in a non-uniform manner

【came. Unify various inspections! There is no system for coral
Because of the wasted time and more importantly the inaccuracy of statistical data
appears as a result. Moreover, the results of the above tests include electronic noise, blinking, and unconsciousness.
This includes errors caused by unexpected eye movements, poor electrode contact, etc.
be caught. Finally, traditional methods do not amplify the data obtained from the electrodes.
It is later displayed directly on the recording device, but at this time the recording device measurement
The data may be damaged due to a defect in the data or a signal unrelated to the data itself.
data becomes inaccurate. To summarize the above, automatic test vR (test stimulus control)
(including control), immediately record data, real-time
EOG system for display and quick and accurate data analysis
The need for a system has long been felt. Such a system
With this system, doctors can receive important information in a short time and in an appropriate format.
Obtainable. This invention is a computerized electrical eye position diagram (CE).
OG), and more specifically, the
The patient undergoes a series of eye position diagram examinations and visual response tests.
automatically and record the results directly online.
, analyze data quickly and accurately, and make decisions quickly.
Continuous and automatic data processing of essential information in an appropriate format,
Errors (electronic noise, blinking, unintended eye movements)
"Edit" to remove any problems (caused by bad electrode contact, etc.).
When to provide. The CEOG system consists of the following parts. i.e. with a patient system or test lllill;
This device can be used for rotating chairs (e.g. for visual motor testing),
each test stimulus @lF (e.g. visual movement @pupil 1, flashing
equipment, light W) and rotating chair and visual stimulation device respectively.
including the control device. The CEOG system also has various
to receive or send electrode data to a computer.
various inputs (provestrum amplifier, amplifier and digital
computer (central processing unit, storage medium,
Including display/keyboard and bartcoby printing@stomach
), a computer, and the aforementioned control device and input device F.
and an interface device for connecting the two. This interface device is used to present test stimuli, respectively.
and facilitate control of input of inspection data. The integrated CEOG system of this invention
Each inspection is performed by operating the data control unit (console).
Select the type of stimulus needed for the patient and automatically present it to the patient
I can do it. In addition, the stimulation characteristics can be varied.
. Data obtained through electrodes placed on the patient's head also
After the data is amplified and digitized, the system performs arithmetic processing.
Appropriate display stored in the crocodile and connected to the system @
J: can be displayed immediately. This CEO
The uniqueness of the G system lies in the fact that the misaligned voltage seen in the electrode data
(initially takes the form of an input voltage signal) jP! influence,
in that it can be corrected by manual or automatic methods. the
Above, this CEOG system allows inspection operators to
It is possible to automatically adjust the zero using the system calculation processing 11i@.
There is an advantage. Finally, this invention can reduce electronic noise, patient blinking, etc.
Immediate processing of input data, removing errors caused by
Enables online processing where collections can be made. Also, microscopic
Detects voltage changes and amplifies thousands of cases without distortion.
Record the processed data on a storage device in preparation for future use.
, processed data can be displayed in “real time”. This system
Tim can do the above things without any command from the ``outside world'' or internally.
This can be done without emitting any unnecessary signals. In this way, the CEOG system of this invention allows doctors to
So that you can get important information in a timely manner,
Enables quick and accurate analysis of data. like that
The data show that both slow and slow changes in nystagmus amplitude and frequency occur.
Duration of minutes; maximum and minimum of 5 accades
and average velocity and amplitude (eyes move from one target in a short period of time)
(synchronized jumps made when changing);
Comparison of optical jump amplitude and optical jump amplitude;
It is a measurement of the leap delay between the jump and the jump of the eye. De-described later
The data is based on statistical data analysis using the CEOG system.
Obtained by display. Therefore, it is an object of this invention to
Electroophthalmography (CEOG) system, i.e. patient
Automatically performs various EOG and VER tests on
and then automatically process the results to provide necessary information to the doctor.
A complete system that displays the necessary information in a suitable format within a short time.
The aim is to provide a Yet another object of this invention is to
EOG or VER tests are incorporated into the system.
A complete set of tools for quick and efficient use of various stimulators.
The aim is to provide a system that is Yet another object of the invention is to provide data from the electrodes immediately.
Online recording, unprocessed data available to inspection operators
Direct display and electrode data automatically processed.
The information that doctors need can be displayed in an appropriate format in a short time.
We provide a system that automatically performs test stimulation that allows
Is Rukoto. Still other objectives are to manually or
or an integrated C lost by an automatic zero adjustment device.
The objective is to provide an EOG system. The above-mentioned and other objects and special features of this invention
The characteristics can be seen from the detailed description below with reference to the accompanying drawings.
It will become even clearer. FIG. 1 is an external diagram of the CEOG system of the present invention. This invention is designed to
Electric eye position depiction (EOG> examination and
This test is for visual evoked response (VER) testing.
. Usually, the electrode junction box 6 is placed on or near the head of the subject 2.
Attach it to the The electrodes 6a to 61 connected to the electrode junction box 6 are
Attach the head skin of subject 2 in such a way that it can be inspected.
. For VER testing, two pairs of electrodes are placed on each side of the patient's right back.
Attached to the head and left earlobe, the fifth electrode 61 is the ground electrode
Attach it to the patient's forehead. Inspection station 4, where the examinee is seated, has (necessary equipment for the examination)
case) there is a rotating chair 8 for rotating the subject 2,
The rotation of the chair is controlled by a control device 110. station
The unit 4 also includes a light point source 12 for presenting a light point and a pair of X-
There is a Y scan #R14. This scanning mirror reflects the light spot into the cylinder of inspection station 4.
Shape! ! used to appear on 18
. Scanning of the mirror 14 in the X and Y directions follows the pattern required by the inspection.
The light point moves in the X or Y direction along the
controlled. Visual movement device 16 (projection that shows II stripes)
gun) has vertical stripes (appropriately determined by inspection) on the cylindrical wall 18.
Project. Light spot 1112. X, Y scanning mirror 14. ? jjlj
1620, operated by 1620
is operated by the control device 10. In the example shown in FIG. 1, the electrodes 6a, 6b, 5e, 5
f detects the horizontal movement of the right eye and left eye of subject 2, respectively.
are connected so that Similarly, electrodes 5c, 5d and
and 6o and 6h are the vertical positions of the right and left eyes of subject 2, respectively.
coupled to measure movement. Finally, the reference electrode 61 is placed on the temple of the subject 2.
. Depending on the test, other arrangements of electrodes 68 to 61 may be used.
Sometimes it's necessary. The electrode 68 used here
Although the arrangement from 61 to 61 is pathological in EOG examination,
, an electrode on this fiber (not seen here) is used for VER testing.
Iga) can be attached to Subject 2 using the ``Ochigaka'' method.
Ru. Electrodes 6a to 6: are connected to painter amplifier group 24, and 2
The output of 4 is provided to filter/amplifier 26. fill
The amplifier/amplifier 26 outputs the measured values of the electrodes respectively.
RH (right horizontal), RU (right vertical), LH (left horizontal), L
tJ (left vertical), RO (right IN head). Analog output through a channel called LO (left rear)
Strengthen. The analog output from filter amplifier 26 is a digitizer.
28 and converts the analog signal into a digital signal.
It will be done. The digital signal from the digitizer 28 is
via the computer interface circuit 30.
Enter Ta 32. In its most modern form, the digitizer 28
The digitized data entered via the interface 30
Using a computer program 36 for processing test data
A processor 34 is housed in the computer 32 and operates as
It will be done. Also, a display device 3 that makes the data visible
8. Printing to record test results in hard copy @
Peripherals such as 1140° floppy disk 42
Permanently stored inspection data recorded using the computer
It consists of 32 parts. The computer 32 also has a test tube
lIIIm@keys used for setting, result processing, result display, etc.
-Includes board. The CEOG of this invention also auto-calibrates (or biases)
circuit 46, which automatically controls the forestomach amplifier network 24 (in the processor)
A more controlled bias is achieved. will be explained in detail later
When the subject's eyes are directed toward the center, as shown in
, by compensating for the voltage deviation of each of the electrodes 6a to 61.
In order for each electrode to maintain zero adjustment, the forestomach amplifier network 24 must
Preamplifier network 2 manually and preferably automatically
It is desirable to be able to adjust 4. Processor 34 connects computer interface 30 to
The chair is rotated via the control device 10 and the test is performed on the subject 2.
The test stimulus presentation is performed by the control device 10 and the panel 20.
Ru. Ideally, the preamplifier network 24 is located within the electrode junction box 6.
It is desirable to be noticed by the public. Figure 2 shows the CE of this invention.
FIG. 2 is a more detailed diagram of the OG system. C used in Figure 1
The display numbers indicating each element of the EOG should be kept as they are as much as possible.
Also used in Figure 2. As shown in Figure 2, the patient system (examination station)
) 4 includes a rotating position in which subject 2 sits during VER and EOG tests.
Including chair. Chair 8 is powered by a power source (e.g. 110 volts).
, 60 Hz) is connected to the motor control device ff152.
It is rotated by a controlling motor 50. Motor control system W
52 is the input from the control panel 54 in the control ll@device 0.
Controlled by force control signal. Furthermore, as explained later,
The motor 50 outputs various output status signals (e.g.
(related to the position and speed of the chair) is motor control p@stomach 52
to the control device [54, other parts of the CEOG system]
Sent to be distributed into minutes. Electrodes attached to subject 2
The electrode test data from 5a-5i (Fig. 1) is
Analog to digital converter in data stage 56
data (ADO). Electrode test - evening there
EOG interface with digital shape
3o to the processor 34 as input data.
It will be done. A desirable R1 is the amount generated from the amplifier circuitry.
Displays electrode test data to the test operator.
A number monitor scope 58 is provided. for example,
By viewing the data on scope 58, CEOG
The system user manually installs the preamplifier network 24 in 11 sections.
Therefore, deviations in electrode voltage can be easily and quickly corrected. difference
Furthermore, as shown in FIG.
Data from a pair of electrodes on the scope
Display the signal and determine the corresponding bias of the front amplifier.
Can be corrected. The processor 34 processes digital data (DATA).
As a result of processing, output #BIAS is interface 30. Ko
inverter stage 56. Preamplification via amplifier network 26
output to the device circuit network 24. Preamplifier circuitry 24 includes input
In response to the force BLAS, the electrode shear voltage is continuously and
Automatically adjust to correct automatically. The control panel 54 is a power source that distributes power throughout the system.
It is a distribution junction box. Specifically, control panel 54 includes 110
A power source of 60 volts and 60 hertz is supplied, and this AC power is
Give to 1160. The power supply 60 is for each element of the system.
Necessary DC power FE (+5V', +1'
2V, +15V, -15V, etc.). control panel
The circuit 54 also receives various DC power from a power supply 60 to provide system power.
Distribute to each part of the system. As shown in Figure 2,
, the power supply output PWR is controlled by the control panel 54 from the preamplifier.
Circuit network 24. Amplifier network 26. Converter stage 56°
It is supplied to the digital camera 62 and the like. Control panel 54 also conveys logical control signals throughout the system.
fulfill the functions of As mentioned above, there is a model that rotates the chair.
The data control section 52 controls the logic circuit section 62 and the processor.
34 via the control panel 54.
receive. As mentioned above, the control signal sent out by the control panel 54 is
, commands the motor IIIJ immediate device 52 to operate the motor 50.
and rotate the chair. The chair moves at the commanded constant speed S.
rotate, 1' rotation model or a predetermined number of rotation models,
Or stop when commanded and automatically move in the opposite direction.
Resume rotation. Control panel 54 also includes motor 50;
Chair position sent to chair 8 via motor control man 52
various status signals such as display signals and chair rotation information.
accept or send an issue. Status signals like this
logic section 62 and sent to interface 30.
Ru. For example, the motor 50 and the motor control device 52 are
Tachometer information (regarding the actual rotational speed of chair 8), chair
Position information regarding child 8's relative position to the starting point, chair
A status signal such as rotation information indicating completion of rotation (second
(not shown in the figure, but will be discussed later), the position detection circuit
Each time it is detected, it is sent to the control panel 54. control panel 54
Also, together with the relay panel 20, as will be described in detail later.
A light point source 12 is operated to control the test stimulus.
, X-Y scan 1114. visual motor apparatus 116, strata
By controlling the drive cage 76 and flasher 70,
to control the examination of the subject 112. More specifically, the relay panel 20 connects the light point source 12 (
(e.g. lasers). This light point source is a circuit breaker
66, operate with X-Y scan 11114 to
Provide testing stimulation. This light spot is used for inspection (e.g. EOG)
pre-programmed to match the test stimulus for the test)
move according to the established system. Light spot It (or laser
)12 is Metrologlc 1 aser, model number
ML-600 or ML620 (these are Metrol
ogic lnstrument. INC.). Shutter 66° This is
This is a device that blocks laser beams, and the laser flashes
Since it may cause damage, it is better to use the shutoff method, and the
Columbia, Maryla
P frlzer M edlcal in nd
3 It can be purchased from ystes, and
(model number T6x 12-Cl2V DC)
Good. The solenoid attached to the shutter 66 is simply a shutter.
- to move a small piece of metal that blocks the beam freely.
Only. Finally, the X-Y scanning mirror 14 is
Q en in WATERTOWN, Husetts
era 13 manufactured by canning
It is better to use the equipment shown. X Y -3Q Q 3
canning A 88131bay series, 2
Two G-330 galvanometers. One (7)X-'7Mount and one A-102 dry
Baanbrihuaiia. Furthermore, the relay panel 20
A motor 68 that moves the washer 70 up and down is controlled. this
Accordingly, 7 lashes 70 give subject 2 a flash test (
VER). flash
The shutter 70 is operated by a photostemulator 72.
It will be done. This flasher 70 and the logic section 62
controlled according to processor 34 via interface 30.
be controlled. Flasher 70 is located in Massachusetts, Qui.
Q rass medical edlcal n
Photo stay simulator made with instruments
Alternatively, @@ (model PS22) may be used. lastly
, the relay panel 20 controls visual motion @1lf16.
It includes a motor 74. The motor 74 is
It is used to move the Ipcage 76 up and down.
There is such a visual motor device ff16, for example,
This is used when performing an EOG test on person 2. Figure 3A shows the preamplifier network 24 of the CEOG system.
show. As seen in Figures 1, 2 and 3A
, preamplifier circuitry 24 includes electrode junctions, as previously described.
It would be best to put me in box 6 (Figure 1). From electrodes 6a to 61
, each connected to preamplifier circuitry 24. To explain in more detail, the prefix in Figures 1 and 2
The amplifier circuit network 24 includes amplifiers A1 to A6 in FIG.
, electrode pairs attached to subject 2, 6a/6b, 6c/
Corresponds to 6d,... The preamplifier network 24 includes
Each preamplifier △1. A2. ... Compatible with A6 size
The test data signal is input from the electrode pair, and then the amplifier circuit
Preamplification output PREMP corresponding to network 26 (FIG. 2)
1. PREMP2゜..., sends out PREMP6. Preamplifier AI. A2. ... 86 is also explained in Fig. 5.
2, an automatic deflection adjuster controlled by the processor 34 of FIG.
Or the zero control input ZRADJ generated by the manual deflection adjuster.
1, ZRADJ 2. ...Receive ZRADJ6
Ru. Test data signals from specific electrodes (e.g. left vertical
(measured value of
> is sent to terminal 10. Amplified by preamplifier A1
(i.e., the preamp output from preamplifier A1
The amplified output is sent as signal PREMP1 via terminal A.
). Zero adjustment signal (e.g. deflection adjustment signal of preamplifier A1)
Then ZRADJ 1 ) is the preamplifier to be regulated (
In this case it is received at terminal 2 of the preamplifier AI). ZRADJ 1. ARADJ2. ...is the zero adjustment signal
(B [AS signal in Figure 2), manual deflection adjustment is required.
When necessary, the amplifier circuitry 26 also automatically adjusts the
In this case, the DAC in the converter stage 56 and the interface
After passing through the source 30, it is sent from the processor 34. Power signal (called PWR in Figure 2. Specifically,
+15 DC volts, -15 DC volts and ground signal G
ND) are terminals F, E of preamplifiers A1 to A6, respectively.
, H as input. In this case, the terminals of preamplifiers A1 to A6 should not be grounded.
Ru. Input/output connector terminals 102 are connected to the respective preamplifiers.
Figure 3A shows how to connect Al-A6 with a coaxial cable.
In , only preamplifier A1 is shown. each
Terminal B of preamplifier Al-A6 is connected to the outer shield of the coaxial cable.
It is desirable that the wires be commonly joined to the mold. share ground
By doing so, the performance of common mode removal is improved,
A considerable amount of the normally occurring system noise is eliminated. FIG. 3B shows a preamplifier within the preamplifier network 24 of FIG. 3A.
Width gauge A1. A2. ...It is an A6 ridged view. Each 1tIMMIIIl device A1. △2. ...A6 is an amplifier
Contains AMP1, which is the Massachusetts Anal
. Using AD522 amplifier from G Devices Sharin
It is good. Amplifier AMP1 is connected via terminals and 10.
Receives electrode test data signals. The electrode test data signal is
Terminals 1 and 3 of amplifier AMI receive it. Diode CR1
and CR2 protect the preamplifier AMP1 from electrostatic discharge.
. Capacitors C7 and C8 are connected to terminals and ground, respectively. Located between terminal 10 and ground, the high frequency of the electrode inspection data signal
Used for wave removal. terminal and between 10 and ground.
Grounding resistors R13 and R14 are connected to amplifier A before electrode insertion.
This is to eliminate the current leaking from MP1. too
If not removed, the voltage (which can reach +15 volts) will
stored in capacitors C7 and C8 and delivered to the patient via electrodes.
May cause shock. Also, the amplifier AMP1 is
External gain setting resistor connected between terminals 2 and 14
Contains R8. If the inputs are shorted at terminals 1 and 3,
, zero potential offset (offset nullpo
The variable resistor P1, which acts as a tentral
Adjust the voltage to zero at terminal 7 of the APMI. amplifier AM
A voltage -Vte is separately supplied to the terminal 5 of P1. amplification
The device AMP outputs PREMPI (+-1, 2,...
6) to amplifier circuitry 26 (FIG. 2). As mentioned in Figure 3A, the image quality amplifier circuitry 2
4 each amplification IA1. △2. ...A6 each has a heno
Power ZRADJ1. ZRADJ2.・By ZRAOJ6
You can adjust the zero. In FIG. 3B, the signal ZRADJI
(+-1, 2, ... 6) is the operator (@
test operator) or processor 34 (test operator) or processor 34 (inspection operator)
Through interface 30 and converter stage 56 of FIG.
zero adjustment). Signal ZRADJI (i-1, 2,...) is amplified
input to terminals 2 and 3 of the device AMP2. AMP2 is
Zero adjustment input current (ZRADJi (1-1°2,・
) as the output voltage Vl! Current-voltage conversion amplification to convert to F
It is a vessel. The input ZRADJI is the circuit shown in Figure 5 below.
Exit from 46'. Remove noise from input signal ARADi (
For this purpose, input capacitor C9 is inserted. to amplifier AMP2
is the capacitor Cl as a feedback RC network.
0 (also serves as noise removal) and resistor R11 of AMP2.
Connect in parallel between output terminal 6 and input terminal 2. Terminals 7 and 4 of the amplifier AMP2 are supplied with a power supply, respectively.
There is an indenter vCC and -vee, and a bias capacitor C1
l and C12 are respectively connected to terminal 7 of AMP2 and ground,
It is connected to the darkness between terminal 4 and ground. The AMP2 has a zero adjustment current ZRADJi (1-1,
2,...) and for zero adjustment, amplifier A
The voltage output VREF is sent to the terminal 11 of MP11. The supply voltages +VCC and -Vee are connected to the respective circuits 10
0 and 102 (Figure 3B) to amplifier AMP2.
enter. Circuits 100 and 102 are an RC network (circuit 10
At 0, resistor R1 and capacitors C1a and C3, the circuit
102 resistor R2 and capacitors C2 and C4)
Consisting of These RC circuits each have a voltage of 115 volts or
and +15 volts, supply voltages -via and +V c
Works to output c' and at the same time blocks noise
fulfill. FIG. 4 is the amplifier circuitry 26 of the CEOG system. Amplifier circuitry 26 includes amplifiers Al1. A12...
A16 and, as mentioned above, the corresponding preamplifier
Output signal PREMP1. PREMP2. ...PREM
Receive P6. Amplifier A11°A12. ...A16 is
Amplify the corresponding preamplifier output signal and left vertical eye movement
, right vertical eye movement, left horizontal eye movement, right horizontal eye movement,
Corresponding to the electrode test data signals of left occipital movement and right occipital movement.
The amplified output signal AMPOUT1. △MPOUT2.・・・
・Take out AMPOLIT6. Output A~IPOUT1.・
..., AMPO, UT6 is the converter stage 56 (Fig. 2)
sent to. Input PREMP1. PREMP2. ..., PREMP
6 is sent to the selection switch 59 as shown in FIG.
and certain preamplifiers when switched on by the operator.
The output is displayed on the scope 58. Image quality amplification output
By looking at the visual display, coarse adjustments can be easily made.
It becomes easy to compensate for the adjustment toward H. signal monitor scope
58 and any oscilloscope will do, but
B&K PRECISION; t cilloscope, model number
1403A (DYNASCAN, Chicago, Illinois)
It is best to use the jaw). Figure 4B shows the amplification of the amplifier network 26 seen in Figure 4A.
Vessel △i i, Al 2. . . . is a detailed view of A16.
. Amplifier Ala'(Ω' = 1.2...) is basically
Ideally, one amplifier AMP3 each, preferably
AD522 (Massachusetts ANALOG D
(manufactured by EVICES) is preferably used. amplifier times
Network 26 (Figure 4A > Basic amplifier used in AIO'
AMP3 is preamplifier AI of preamplifier network 24
Amplifier AMPI used for (1-1, 2,...)
(Note that it is the same as AMP2>)
sea bream. However, the external connections of amplifier AMP3 (Figure 4B)
The continuation is for amplifiers AMP1 and AMP2 (Figure 3B).
That's interesting. Preamplifier output signal PREMPJ (J-1,2°・
) is connected to the amplifier AMP3 via the input circuitry 120.
are sent to terminals 1 and 3, respectively. Specifically,
The network 120 includes a resistor R3 in series with capacitor c5 and a capacitor c5.
It consists of a resistor R5 in series with a capacitor C6. This RC circuit
The net is used to filter the input PREMPJ
. Diodes CRI and OR2 of network 120 are
The function is similar to the similarly cut-out diode in amplifier A1.
(Figure 3B). Capacitors C7 and C8 are the third
Corresponding to the similar capacitor in Figure B, during inspection, high frequency
remove. Resistors R13 and R14 are the same as in Figure 3B.
This corresponds to the ground resistance. In an ideal form, the VER test and EOG test respectively
It is possible to use an amplifier R1, which has been developed in for example
, if AC coupling is desired, resistors R3 and R4 are
Capacitors can be replaced. Amplifier AMP3 has input PREMPJ (J −1°2
,...) and converts it into the rate determined by the gain setting resistor R8.
only amplify. R8 is terminal 2 and 1 of amplifier ΔMP3
Connect to 4. Same as in amplifier AMP1 of Fig. 3B.
Similarly, terminals 8 and 5 of amplifier AMP3 are supplied with
Supply voltages +Vcc and -Vcc come. Amplifier AMP3
External IIX is provided by variable resistor P1. Amplifier A
1J (J −1°2,...), that is, △MP3
is the terminal △ and the amplifier output AMOUT'J (j-1, 2
, -> output 1° output A M P J is the converter stage 56
(Figure 2). . FIG. 5 illustrates the vias included in amplifier network 26 of FIG.
46 shows the switching circuit 46'. In FIG. 1, the offsets of the individual amplifiers within preamplifier 24 are shown.
An automatic calibration circuit operated by the processor 34 for adjustment of the
46 were seen. In the ideal form of this invention, such
The auto-calibration feature includes a bias circuit within the amplifier circuitry 26.
It is done by road. In FIG. 5, the bias circuit 46' basically consists of many points.
Function meter POT1. ..., consisting of POT6, output
Force ZRADJ 1, ..., to issue ZRADJ6
The vias of the individual amplifiers of the preamplifier network 24 are
(Figure 2). Manual override of each amplifier in preamplifier network 24 (Figure 3A)
Adjustment is performed using the bias selection switch (l! connection switch S1.
...consisting of S6) is AUTO or MANUAL
It is done when the value is entered. Bias selection switch is up
If it is in the 1s digit in any of the above, the operator
Adjusting POTI-PO1'6 changes the resistance. sand
That is, the current passing through resistors R31-R36 changes,
Zero adjustment current signal ZRADJ 1-ZF<ADJ6
occurs. Each amplifier in preamplifier network 24 of FIG.
Itch 81. ..., S6 (Fig. 5) is ranked AIJTo -
If it is, it will be adjusted automatically. Entered AUT 0th place 1st
Automatic adjustment input signal @B AS1-B IAS6
enters from converter stage 56 (FIG. 2). Signal B
IAS1-BIAS6 have corresponding resistors R21-R26
Through zero ll J [+ electric IZRADJ 1-ZRADJ
Generate 6. Bias selection switch is set to At, position 110-
and each amplifier in the preamplifier network 24 (FIG. 2).
Both manual and automatic adjustments can be made. This consists of resistors R21-R26 (for automatic adjustment) and resistor R3.
1-R36 (for automatic AM) is connected in parallel in this state.
This is because However, the switch is in MANUAL position.
in the preamplifier network 24 (FIG. 2).
Each amplifier can only be adjusted manually. This is resistor R31
- Potentiometer only compatible with R36 (for manual adjustment)
(POTl-POT6), and resistor R21
- because R26 is in an “open circuit” situation under these conditions.
be. Something that handles this CEOG system rather than the above devices
The preamplifier network 24 (second
Check the deviation or offset potential of each amplifier in
Can be dynamically corrected. This allows the CEOG system to
The operator must adjust each amplifier (i.e., left eye vertical movement, right eye vertical movement)
Coarse bias correction (corresponding to direct motion, etc.) can be performed. So
So, coarse! The first section allows the electrode to be connected to the subject's head and stomach.
Kururi, C. Most of the offset voltage can be removed. Do manual AT first or occasionally use the system.
You may “line up” the CEOG of this invention.
The system also includes a preamplifier network 24 (Figure 2).
Automatic fine bias adjustment for each amplifier in the 6
Fine adjustment of each amplifier in such network 24 is performed by a professional
To generate the BIAS signal in the sensor 34 (Fig. 2)
It will be done more. B rAs signal is interface 3
0 and bias circuit 46' via converter stage 56.
(Figure 5). BrAS input ([31 to 81
, B IAS 2. -”) t, outputs the v4m signal
Stop by Z RA DJl, ZRAOJ2 and more! and each electric
The remaining O, C, and offset voltages at the poles are automatically removed.
It will be done. FIG. 6A shows the ΔDC portion 56 of the converter stage 56 of FIG.
′ is shown. The ADC section 56' of the converter stage 56 (FIG. 2) has multiple
A/D1. A/D2. A/D
3, the amplifier network 26 (FIG. 4A)
Al1. △12.・・・A pair from each of A16
Analog electrode data input signal AMPOUTI /△M
POtJT2. AMPOUT3/AMPOTJT4. fart
Receive MPOUT5/AMPOUT6 and send them respectively.
The f digital output is converted to DATO-DA 9. sand
That is, converter A/DI-△, /r)5 is the timing
to be clocked by clock input SAMPLE
, which allows each converter to connect to each analog input.
Signal (△MPOUT1.ΔMPOUT2 etc.) 10-
Converts bits to digital words and converts them respectively
A, , /D 1- A, /D Stored in internal buffer of 5
be done. II, computer processor 34 (Fig.
), input goo r d [◇]■]-℃--ff1 mouth m,
gda T Kings T “When Y is generated,
Converter A/DI-A/D5 outputs from internal Balanoa
transfer data to the digital channel at an appropriate time.
output DAT' O-DAT9. Furthermore, another converter A is installed in the △DG portion 56'.
/D4, and analog signal rAcH2 (moves chair 8).
1111 to the speed of the scrap motor 50 (FIG. 2));
SIRIP):SF'l) (Visual motor system in Figure 2)
Motor 74 that moves stripe cage 76 in station 116
) and converts it into a digital signal.
Ru. There is also another converter in the ADO section 56' of Figure 6A.
Ta A/D! : There is +, analog signal PO8X and
PO8Y (Regarding the X and Y positions of 1t14 in Figure 2)
) and converts it into digital form. Analog belief @
IA CH2 is connected to the control panel 54 in FIG.
Motor control device via Science Department 62! b2
data stage 56. Analog signal S I RI
P E S F-'D can be directly controlled by the control panel 54.
is supplied to an inverter stage 56. analog signal posx
and PO8Y are the control panel 54 and logic section 62 of FIG.
to converter stage 56 by relay panel 20 via
Ru. Finally, as shown below, each converter A/DI-A
105 receives the human-powered SAMPLE and converts the analog data.
Start digital conversion. When the conversion is complete, the output D
ATRDY is generated. These two control signals are discussed further below.
Ru. Figure 6B shows half of the converter A/DI of Figure 6A.
FIG. The other half of converter A/D1 is the sixth
It has the same structure as the half seen in Figure B. Also, each component
Converter A/DI-A/D5 is the same as converter A/D1.
It is one. Calibration of converter A/DI (half) is done in sample hole.
lead circuit 150. ADC device 154. Buffer 158
and 160. The sample and hold circuit 150 is shown in FIG.
As seen in amplifiers 166 and 168 . AND
It consists of a gate 170. As a sample hold circuit
, AD582@ place (A naloo D evlc
es Newsletter) is desirable. Also, the ADO device 154 is normally
analog-to-digital converter, preferably
AD571 installation @ (Analog Q evlce
s company newsletter) is good. Buffers 158I6 and 160 are
, three-state amplifiers 172 to 177 and an AND gate.
178. In other words, the output of gate 178 is
–”, amplifiers 172 to 177 are in an open circuit state.
It is in. When the output of gate 178 is "high", the amplification
The outputs of the devices 172, 173, ... are from the ADC 154.
Input signal B1.82. It is the same as... buffer
158 and 160 are 6/3 state buffers, type
1lSN 74 L S 365 or 5N74365
<Made by Texas Instruments Inc.) is preferable. Output AMPOUT1 is output by sample hold circuit 150.
is received from amplifier circuitry 26 (FIG. 2). Faith
The signal D A T R D Y is normally “high” and the signal S
AMPLE is usually [low J. SAMPLE is
When the signal becomes “high,” the signals r, Tπ, and Y also become “high.”
, the gate G1 of the sample and hold circuit 150 is closed.
AMPO (voltage at JTI is applied to the input to amplifier 168)
be exposed. Then, the signal AMPOtJT1 is output to the amplifier 168.
It depends on the output. That is, current on both sides of capacitor C1
You will be killed. Gate when SAMPLE goes low
G1 opens (S A M P L 'E and σ M TR
(keep opening until both DY are high), AMPOL
The I T 1 voltage remains at the output of amplifier 168. this voltage
, AMPOUTl changes from analog to digital △DC
It remains unchanged even if it changes while being converted within 154. Therefore
When gate G1 is closed, signal AMPOUTI is
When the gate G1 is opened, the sampled input signal is
The force signal is held at the AIN terminal of ADC 154. Described later
As shown in FIG.
In response to the signal from 0 @SAMPLE going low (
(Fig. 6D), convert analog input AMPOUTI to digital
Convert to the form . During the digital conversion, ADC@I
I! 150 keeps output DATRDY high and DATRDY
Set TRDY low. But when the conversion is finished, AD
C unit 154 generates a low output DATRDY. output
In order for DATRDY to go high, the individual converter
A/D 1,... Each of the two ADC devices j154 in the A/D6 connects to the terminal DA.
Must produce a low output on TRDY. To be so
If so, the output DATRDY becomes high and the ADC logic circuit
200 (Figure 60). Digital bit outputs B1 to 86 are sent to the X buffer 15
It is sent to the three-shaped butterfly buffers 172 to 177 in
Digital bit output B7 to 810 is in pan frame 160
(not shown). join it
What, the buffer in buffer 158? 172 to 177
(and a corresponding buffer (not shown) in buffer 160)
) at the output point until it receives a clock type signal.
It's an open circuit type thing. to be specific,
When processor 34 (FIG. 2) sends an address input signal,
The dress decode logic circuit 190 (FIG. 6C) is a clock
Type of signal (M-TT). 9-cho 1 generates 1 gogo, etc. (details are explained below)
do). In this way, 5TROBIO is buffer 1
Sent to 58 and 160, buff? digital pit
Data is output from DATO to DAT9 and interface
via the interface 30 to the processor 34 (FIG. 2).
. If you run it over, Figure 68 shows the converter A/DI in Figure 6A.
Detailed view of half, and each converter A/D2-A
/D5 has the same structure as A/DI. the above theory
As is clear from the light, the first half of A101 and A/D5
The minutes are each clock type input signal @dingffdingdingdingstone,
..., Bl 6.5TROBX at Tacho■ (Fig. 6A
) in response to the digital output DATO-DAT9.
The latter half of converter A/DI-A105
minutes for each clock type input m-1.・
..., in response to TTV, 5 TROBY
Output the data DA0-DAT9. jFI6c is the address in the converter stage 56 of FIG.
This is a diagrammatic representation of the decode logic circuit 190.
Ru. The logic circuit 190 is basically a binary/octal decoding circuit 1
It consists of 92, 194, 196. Main to logic circuit 190
The inputs are address inputs ADDR1, ADDR2, AD
DR3, and further input GRP1ST8. GRP2STB,
It is GRP3STB. The binary/8-selection decoder 192 is a signal human power GRP1STB (
(acts as decode clock signal) and input ADR1
-Receive and respond to ADR3 and perform 8-way conversion. i.e.
, 8 from QO to 07, corresponding to a specific decoding input.
Select and issue one of the outputs of I. The clock mentioned above
The output of type 5TROB10-8TRO817 is like this
This is how it was obtained. 5TROBIO-8TR
OB17 is the ADC section 56' (sixth
A/D1. A/D
2. It turns out that it was a clock type signal sent to...
I would like you to remember that. Similarly, the binary/octal decoder 194 outputs the signal GRP.
In response to receiving 2STB and ADDR1-ADDR3
to perform octal conversion and correspond to a specific decoder input.
Select and output one output from QO to 07. in this way
Clock type output 5TROB20-3TROB
27 are obtained, and their clocked outputs are as follows:
used in the DAC section of the converter stage 56 (Fig. 2).
It will be done. Finally, 23! /83m decoder 196 inputs GRP3
In response to receiving STB and ADDR1-ADDR3
Performs octal conversion and outputs depending on which decode input
Choose one from 07 from QO. Clock type output ST
ROBMB and STROBMY are obtained in this way,
In the DAC circuit 300 (FIG. 6E), as described below,
Used as a clock type input. In addition, the decoder 19
6 (Figure 6C) is the clock type output 5TROBPX and 5T.
ROBPY, these are clocked inputs to A
/Proceed to D5 (Figure 6A). Binary/octal decoder 192, 194 and 1 of FIG. 6C
What kind of binary/octal converter circuit do you use as 96?
5N74L842 converter circuit if possible.
(manufactured by Texas Instruments) is good. FIG. 6D shows the ADC logic circuit of converter stage 56 of FIG.
This is a more detailed illustration of 200 and 250.
. Is the logic circuit 200 a timer 200 (preferably in seconds)?
The system “turns on” and turns on the inverter.
output R8T through the A, /D and D/A systems.
reset the system. In particular, R8T is as described below.
, latch circuit 3 in the DAC circuit 300 (FIG. 6E)
Used to reset 02-305. Logic circuit 250 (Figure 6D) is basically a NAND game.
252 and One Shot I [W1254 and 256?
It will be. NAND gate 252 has input CMPSAMP(
One bit from interface 30 of FIG.
is bit number 14) input) or 5MSSAMP (second
Input from logic section 62 in the figure) is discovered, and
Trigger @11254 and output SAMPLE to each
Converter A/D 1-A/D5 (Figure 6A and
6B) is transmitted to the ADC device 154 in FIG. signal SAM
The trailing edge of the PLE initiated the conversion process in each ADC device.
I want you to remember that. Also, as mentioned above, all ADC1ilf154
When the conversion process is completed, the output DATRDY goes high.
I want you to remember that you can. Then, one shot
device 256 (Figure 6D) is triggered to output 5NOD.
AT occurs and via interface 30 (FIG. 2)
It is transmitted to processor 34. Processor 34 outputs 5ND
Digital data converted from analog by DAT
data is ready for transmission to computer processor 34.
I know it's over. In response, processor 34
The appropriate decoder input GRP via interface 30
ISTB (also 4, t G RP 2 S T B
. GRP3STB) and ADDR1-ADDR3,
As a result, address decoder logic circuit 190 (first
Figure 6C) is a lock type output (STROBL 0-
Take out one trading card from 8TROB17 and use the digital
Converter A/D with appropriate data I,... A/D
5 (Figure 6A) to the processor 34.
I'll do it. FIG. 6E shows the DAC section 300 of converter stage 56 of FIG.
This is a detailed diagrammatic representation of the Basically, the DAC part 300 is a latch circuit 3゜2゜J:
and 303. DA (41f306 and IQl! (7) increase
It consists of a width gauge 308. In operation, latch circuit 302
and 303 by the input R8T entering each R terminal.
will be reset. After that, connect the clock to each GK terminal.
In response to lock type input 5TROBN, each latch circuit 3
02 and 303 respectively from the processor 34 (Fig. 2).
The digital data DTOA6-DTOA9 and DT
Receive and latch OAO-DTOA5. For latches 302 and 303 in FIG.
A latch circuit of 7418174 latches may be used, but if possible, a latch circuit of 7418174
A device (manufactured by Texas Instruments) is preferred. The DAC device ff306 has latch circuits 302 and 303.
The latch circuit 302 outputs a latch output Ql.
-04, and the latch output Ql from the latch circuit 303.
-06 received. After that, is the DAC306 digital?
The analog output signal AMA is converted from
LOUT is output and applied to amplifier 308. amplifier 308
connects the DAC device W306(7) ANALOUT output to the
The output voltage signal B IASN (
N-1, 2,...6), and the bias shown in Figure 5 above.
to circuit 46'. Any conventional digital analyzer can be used as the DAC device 306.
A log converter device may be used, but if possible, an AD
561J converter equipment (ANA in Massachusetts)
LOG Devices Inc.) is preferred. Therefore
Therefore, the supply voltage to the DAC306 is Vcc and Vcc (the
+5 and -15 volts respectively). DAC@@
The gain and bias of the output of 306 are determined by the respective potentials.
It is set externally by the yometers P1 and P4. Finally, which operation is common for amplifier 308 in Figure 6E?
Although it can be used with an amplifier, it is preferable to use the UA741 amplifier.
Manufactured by Analog Devices, Inc., Sachusetts) is preferred.
stomach. Therefore, the supply voltage for amplifier 308 is +15 volts.
and -15 volts. Analog output ANALO
UT goes to terminal 2 of amplifier 308, terminal 3 is grounded resistor
Connect to ground via R1. Furthermore, the amplifier 308
The output is sent to the DAC@device 3 via potentiometer P1.
In addition to connecting to 6 in a feedback manner,
Also feeds to terminal 2 through back capacitor C5.
back connection. Finally, amplifier 308 has a feed
Buck capacitors C6 and C7 are included. The calibration of the DAC circuit 300 in FIG.
latch circuits 302 and 303. 1 DAC each@1
Although I mentioned f306 and an amplifier, the DAC circuit 300 is not possible.
If so, one more pair of latch circuits and one more DAC installation
It is desirable to have a device width switch and have 2 channels output.
stomach. In such a desired arrangement, the output B IAS
N (N-1°3.5) is the
For bias adjustment of odd-numbered preamplifiers, the DAC
The output of the second portion of circuit 300 (B IASM (M-2
゜4.6)) is the even numbered prefix of the preamplifier network 24.
It is used for amplification. In summary, processor 34 (FIG. 2) outputs the output signal DTO
AO-DTOA9 (Fig. 6F) is connected to the latch circuit 302 and
and 303 to the DAC device 306, where the
A conversion to analog is performed. The resulting analog output ANALOLJT is the amplifier 3
The bale converted from current to voltage in step 08, output voltage signal B
Becomes IASN. As explained above, the desired shape of the arrangement
In the position, the output BJASN (N-1°3.5) is
Bias of odd number 1 preamplifier in amplifier network 24 (FIG. 2)
Adjust the as and send another set of output signals! (BIASM
(M-2,4,6)) is the even numbered preamplifier bias
Adjust. Figure 7 A CE OG System 7 (7)
Ta1111111! ii Diagrammatic representation of If52
It is. The motor control device 1f52 is basically a linear servo control l
l1iiili place 320. Dynamic cutoff relay 322
゜Motor speed buffer 324. Brake command input (feed)
Ill-Safe) Circuit 326 and Chair Ink-Lock Circuit
It consists of 328. In actual operation, the primary servo controller 320 operates
As a result of the device selection, the control pattern starting at logic section 62 is
Control signal MTR8 sent by channel 54 (FIG. 2)
Accept PD. Linear servo 320 also controls motor 50.
The motor 50 and associated tachometer 51 indicate the actual speed.
tachometer output signal TACHrN. Traditional
In this way, the linear servo controller 320 actually controls the motor
Speed (TACHIN> and setting motor speed (MTR8PD
). of such a comparison
``As a result, the control device @320 adjusts the motor control power (LOA) as appropriate.
DLO/LOADHI) signal. motor control power
is controlled by the dynamic control brake relay 322.
is sent to the motor 50 and increases or decreases the speed of the motor 50.
control the rotation speed of chair 8 (Fig. 2), and control the overall operation.
You will be controlling the speed. Speed input signal sent to linear servo controller 320
TACHIN is also sent to rate buffer 324. There
From then on, the subsequent digital conversion and interface 3o
for preparation to the processor 34 via the analog signal T
ACH2 of converter 56 (Fig. 2 and Fig. 6A)
The signal is sent to the ADC section 56. In this way, the processor
34 always knows the actual speed of the motor moving chair 8.
There will be. Speed buffer 324 is commonplace
A buffer amplifier is sufficient. Ring servo control I device 320 is safe at terminals 4 and 6 @
Brake command signal BRK sent by line 326
6 and BRK8 respectively. The ring-shaped servo control device 2320 receives the brake command signal BRK.
6 and BRK8 in response to the brake command input signal.
The motor control power sent from the controller 320 is used for braking operation.
Set it to zero during the work. The input signals BRK6 and BRK8 are
are the BRKI and R sent from the control panel 54 (FIG. 2).
Output of fail-safe circuit 326 receiving ELBRK input
It is power. Figure 7B is the fail-safe circuit 3 of Figure 7A.
26 is a detailed design drawing. The input signal BRKI is the control
through channel 54 (FIG. 2) to logic section 62 (second
(Fig.) and is always kept high (for example, +5 volts).
dripping The input signal RELBRK is normally kept high and the
Lenoid 362 is inactive, switch 36
4 is normally kept closed. In this device, the control unit @320 (Fig. 7A) is set to LOADLO.
/LOADHI output has zero amplification.
Ru. However, when RELBRK goes low, solenoid 36
2 is energized and the normally held switch 364 is turned on.
Open and connect the light to the rod-shaped servo-controlled stomach 320 (Fig. 7Δ).
Human power BRK6 and BRK8 are connected to linear servo controller 2.
320 to guide the speed of the motor 50 to the desired motor speed.
degree (MTR8PD) and actual motor speed (TACHIN
) to match. FIG. 7C shows the chair interlock circuit 328 of FIG. 7A.
This is a detailed blueprint. Basically chair interlock times
Path 328 is connected to resistor 330. as shown in FIG. 7C. transient die
Consists of 1 for the ode 332 and the solenoid, Fig. 7
A, C connected to power switches 338 and 340 as shown in
seat belt 334 (chair shown in Figure 142).
child 8). In actual operation, start switch S2 (chair motor
With the motor activation switch, press the control panel in Figure 2 as shown below.
When the positive
DC voltage is applied to the solenoid 1 through the resistor 330.
1 is A for the solenoid. C9 power switches 338 and 340 are moved to the closed position.
A, C11ll is equipped with servo control ff11320
(Figure 7A). What you need to be careful about is the chair.
As a result of activation of child interlock circuit 328, seatbelt
334 (attached to chair 8 in Figure 2).
If so, solenoid 1 will not be activated and connected to positive DC voltage.
The idea is to keep the underground circuit closed. This way
Sea urchin chair 8 is equipped with a safety @ stomach, and with this device
The subject sitting in the servant chair 8 fastens the seat belt 334.
When removed, A connects to the servo control device 1320 and motor 50.
C power supply is interrupted. Motor control fil! 52 further includes a position detection circuit 336.
In actual operation, it is attached to chair 8 (Fig. 7A).
I'm wearing it. In detail, a reflector 350 is attached to the chair 8.
This is the lamp 352 (voltage + PO8L I
reflect the rays received from the
, the reflected light hits the photodetector 354, and the chair position
The information PO8DER is generated and this information is used for motor control.
52 and control panel 54 (FIG. 2).
The information is sent to section 62. For signal PO8DET, chair 8 is normal.
It shows that it is at the position 906 on the right side of the position. The motor controller 52 (FIG. 7A) also has a start limit.
A switch 356 (normally open) is installed.
In actual operation, it cannot be installed on chair 8 (Fig. 7A).
be. Start limit switch 356 is not open
At this time, the signal STRLIM is set high. However, circuit S
As long as TRC0M is connected to ground, the star limit
When closing switch 356, STRLIM goes low.
become. This low state is controlled through the control panel 54 (FIG. 2).
It is then sent to the logic section 62. Star as shown below
Open the limit switch 356 and turn the system on with the actuator.
When reassembled, chair 8 is shown as indicated by the high STRLIM signal.
will automatically close start limit 1 to switch 356.
and return to normal position. Figure 7D shows the dynamic brake relay 322 of Figure 7A.
This is a detailed blueprint. Dynamic braking relay circuit 32
2 is a relay switch 370 and 372, and - an example resistor.
374, drive solenoid 376 and transient diode 3
Consists of 78. In operation, relay switches 370 and 372 are normally in the down position.
LOADL of control II @ position 320
O/LOADHI power control signal to motor 50 (Fig. 7A)
). Input +BRAKE is positive voltage (high level)
relay switches 370 and 372 are kept in their normal
It is maintained in the downward digit 1. Once BRAKE goes low
This activates solenoid 376, causing switch 370 and
and 372 to the upward position. This is the power control signal.
LOADLO/LOADHI to the motor 50.
In addition to interrupting, it also connects switches 370 and 372.
The input terminal leading to the motor 50 is cut off due to a short circuit.
This provides a dynamic control effect. Figure 1118 is a diagonal view of the relay panel 20 of the CEOG system.
This is a perspective view. Typically, relay panel 20 includes control panel 54 and logic section 62.
In response to various input control signals from the optical II
I 2. Reflection III 4. Shutter 66° visual motor organ
16 (motors 74 and 74' and stripe cage 76
), a flasher motor 68 and a flasher 70
Control. Furthermore, the relay panel 20 is
signal (XBACK and YBAC)
K) and this feedback is transmitted via the control panel 54.
A read signal is sent to the logic section 62. In this way, below
As explained, the cylindrical shape of inspection station 4! l(th
This will correct the distortion of the light source irradiation on the area shown in Figure 1. The relay panel 20 accepts various DC voltage inputs (+12V and
AC power (15v) and AC human power (110v) are accepted. relay
The A, C inputs to panel 20 simply pass through, A, C1l;
b is applied to the laser 12 (FIG. 2). 12VD, C input
is connected to relay switch 402 and 404 and resistor 4
Illuminating stripe cage 76 (second) through 06
Input to lamp 400 (LITEl and LITE2)
Supplied as. To explain in detail, relay switch
402 and 404 are normally in the open position, LITE
When ON (accepted from logic section 62) goes low, the
It is driven by the lenoid 408 to be in the closed position 1.
Ru. On the other hand, as LITEON goes high,
luid 408 is shut off and switches 402 and 404 are turned off.
Returns to normal position and interrupts power supply to lamp 400
do. Here, the relay panel 20 includes a capacitor 412,
Its positive terminal should be connected to the power input +RELAY.
Please be careful. Capacitor 412 is +RELAY input
Acts as a noise prevention filter for power (positive voltage, e.g. 15cm)
do. Furthermore, referring to FIG. 8, the relay panel 20 is
includes switches 422 and 424, and input (TRMTR
As long as ON (from logic 62 in FIG. 2) is high
, this switch normally remains in the open position. deer
and the signal TRMTRON is low (thus
In response to the drive command given to the drive motor 74)
Solenoid 420 then switches switches 422 and 424.
Close, +12 pol defines - input and its return. The power input circuit described above has a switch that is normally in the downward position.
416 and 418 (T from logic section 62).
+12 volts and times as long as RMTRON is high)
are routed to the A and B input terminals of motor 74, respectively. The power input to this motor 74 is
Raise the tripe cage or the raised position
I do miscellaneous things. However, the operator pulled down the stripe cage 76.
(This is described below in Figure 9A), the input
Signal T RNl 1' R℃ ball becomes low and switch 4
16 and 418 (by solenoid 414) downwards.
It will be driven to the next position. This results in
C. Change the polarity of the manual power to the opposite, +12 volts and
circuit to each of terminals A and B of motor 74.
. Therefore, motor 74 can be operated in the opposite direction to
I'll pull down the striped cage of the sex movement V41F16.
I'm going to growl. Furthermore, the motor 74 has a striped Kushif 6 on its top.
or when the lowest position is reached, the status output signal LIMLJP
Generates OK or IMDNOK. Relay panel 20 also operates flasher 70 with motor 68.
It has a switch and solenoid device that moves it up and down. Details
Specifically, switches 428 and 430
As long as @FLMTRON is high, this is the operator
wishes to keep motor 68 closed.
display and remains in its normal upward position. In fact, Sui
When the switches 428 and 430 are in the upward position, the
The power input terminal of the controller 68 is interrupted. However, depending on the operator's command to drive the motor 68, F
LMTRON goes O- and switches 428 and 43
0 to the downward position, causing motor 68
A power input circuit will be created at terminals △, B, and C.
Ru. Therefore, the motor 68 is connected to the flasher 70 and the switch 4.
It can be moved up and down according to the position of 32. upward direction
In the next position, apply a positive voltage to terminal A of the motor 68 to flush it.
Pull down the switch 432 to the lowest position of the motor.
Apply positive voltage to terminal B of 68 to pull flasher 70.
increase. To explain in more detail, the input FLSHDWN is
Keep the flasher 70 high during the period you want it to be raised.
Keep it in mind. Then, move switch 434 to the lowest position.
put. Conversely, when FLSHDWN goes low, the solenoid
436 drives switch 434 to the highest position and the flash
Lower the carrier 70 via the motor 68 (of course using the relay).
-432 is also driven). The relay panel 20 in FIG. 8 is the control panel 54 (FIG. 2).
Accepts input signals -CGMTR and +00MTR from
, and transmits this to the motor 74. This rotates the stripe cage 76 via the motor 74.
This is to control the speed. Relay panel 20 receives input from control panel 54 -5HIJ
T and +5HUT and send it to shutter 66 (
Figure 2). This opens and closes the shutter 66 as appropriate.
It's for a reason. Furthermore, the relay panel 20 beam, C, reflects the power #11
4 (via control panel 54 to logic section 62).
output signals XDRIVE and YDR
Transmit the IVE to the mirror 14 and move the reflection isthmus in the X or Y7j direction, respectively.
change. Opening/closing panel 20 is reflective @ X and Y position from 14
It accepts the position signals XBACK and YBACK. This signal is
It is communicated to the logic unit 62 via the control panel 54. This is i
PO8X to processor 34 via interface 30
This is to create a POXY status input. Refer to FIGS. 98 through 9E for the control panel 54 of FIG.
This will be explained in more detail below. Control panel 54 (FIG. 2) essentially serves two purposes.
vinegar. First, it is used as a power distribution junction box throughout the system.
Everything that is used and communicated through the CEOG system
Serves as a central point for controlling and distributing status signals. secondly
The operator can see at a glance via the switch or display @ stomach.
controls that allow you to interact with the system
Performs useful function of panel. In a preferred embodiment, the
The function of a junction box is to connect a large number of cables to various functions.
From each functional unit as opposed to passing between self-study
Control one cable (for example as shown in Figure 2)
This is done by passing it through the panel. Figure 9A shows the operator control panel 54 of the CEOG system.
FIG. 3 is a perspective view of the controller. Typically, there are multiple operator controls 450 on control panel 54.
Display device [(DS) switch (S) and potentiometer
Includes an adjustment knob connected to (P). Roughly, various tables
Display devices, switches and adjustment knobs are used for power, chair controls, and straps.
IP cage operation, flasher operation, light source (laser) and
Divided into mirror operations. Operator control 450 includes one A, C power switch S
, has. This switch drives the entire system
, C power is supplied = AC power supply is indicated @[DS
Indicated by l. As mentioned above, in connection with FIG.
The use of C power for the CEOG system, especially for power supply 60
The use is to start a variety of DC power supply voltages. In Figure 9A
Returning, operator control 450 controls the various DCIII
Indicates voltage capability, e.g. +5V, -15V, +15
V, +12V, etc. (7) DS2. DS3. DS4. DS
It has a display device such as 5. The operator control unit 450
Drives the motor 50 (Fig. 12) for moving the chair 8.
The switch S2 includes a switch S2. Display device DS6 is motor 5
DS6 will display it when a 0 is driven. motor 50
, and therefore the required rotational speed of chair 8 is adjusted.
Select with knob P1. This m-node knob P1 is a potentiometer.
connected to a motor controller (not shown here) to control the motor.
Especially the linear servo control provided to the item 52 (Figure 2)
Signal MTR8PD provided to device 320 (FIG. 7A)
occurs. Operator control section 450 of FIG. 9A includes switches S3 and
Includes $4. These are temporary suspensions of chair 8 (Figure 2).
and start and also indicates "chair ready" -1
Includes DS7 display. Further, the operator control unit 450 is configured to use a reset switch S.
Contains 5. This is a versatile switch.
It has a manual reset button. That is, (1) the rotating chair 8 (Fig. 2) is in a normal position If
so that it rotates. (2) SCAN and RECORD
ING ON D l5Kl (71J many (7
) Clear computer hits. Operator j wholesale department 450 also has stripe cage 76
(Fig. 2) including switches s7 and S8 that move the
nothing. These are one shot push button switches tS77
')' By pressing each button of S8 once
The stripe cage 76 can be moved up and down. The operator control 450 is connected to a potentiometer.
Includes Im knob P2. These are 10-turn potentiometers
Ta is better. These are the stripe cages 76 (Fig.
) to adjust the rotation speed. The operator control unit 450 controls the stripe cage 76 (12
blinking the linear light bulb 400 (Figure 8) inside the
Equipped with a switch. Additionally, the 3-position switch 814 is
Change the direction of rotation of the Lie Large 76 to the left or right or stop the rotation.
Show below. The operator control unit 450 selects the stripe preparation J-shape 11.
tDs8 and Ds9 (RECORDINGON D
ISK>Includes display device. The DS9 display device is
Display that flashes when the data is copied to disk
(This may cause the system operator to inadvertently
(Do not fill the disk all the way.) Press again
Button switches S9 and S10 are connected to the flasher 70 (
(Fig. 2) up and down. Further, the operator control unit 450 controls the light source (laser) 12
(Fig. 12) Horizontal velocity and vertical velocity of the ray generated by
Includes adjustment knobs P3 and P4 to control position. In detail
To explain, the adjustment knob P3 is a potentiometer (here
(not visible)...preferably 10 rotation potentiometer
connected to the meter and applied to Subject 2 (Figure 2).
This is to control the horizontal speed of the light spot. This light spot
By the movement of mirror 14 that reflects the beam from laser 12
The movement of 11114 is controlled via the adjustment knob P3 on the other hand.
Operator actuated potentiometer (currently shown here)
(not controlled). The vertical position of the light spot applied to subject 2 is adjusted using the adjustment knob P/I.
The laser 12 is activated via the potentiometer by the operation of
Controlled by adjusting. Operator control 450 also includes manual switch S12.
It is preferable to This manual switch allows the laser 12
The position of the light spot generated by reflection @14 (Fig. 2) is varied.
It is possible to control according to the function. Operator control section 450 includes a toggle switch S13.
, the operation of the light 11112 and the anti-F14 mirror 14 (Fig. 2) is
Choose whether to perform setup-type operation or automatic operation.
You can make your choice with this switch. In other words,
The start-up operation allows the light stimulus to be applied to the subject in advance.
The type selected by the doctor who performs the test using a method that has already been explained to you.
means to do so according to the On the contrary, automatic operation
The light stimulation is carried out by the CEOG system's computer (processor).
)34. The operator control unit 450 includes an inspection warning indicator DS10.
nothing. This allows you to try out or adjust the system (e.g. chair
8 (as in the manual operation of FIG. 2)) logic section 62 (as in the manual operation of
This is done using a manual switch installed on part L3 of Figure G).
If you want to drive. Another “inspection” as shown below
Warning", remove the electromagnetic brake on chair 8 (Figure 2) and
can be manually moved from its normal setup position.
It can be done as follows. Operator control unit 450 scans the CEOG system.
It includes a display DS11 that shows the formula operation. Also, chair 8 (second
The number of rotations of
equipped with a switch S6 automatically indicated by sensor 34.
Ru. Figures 9B to 9E show the control parameters of the CEOG system.
5 is a detailed perspective view of the flannel 54. FIG. To explain in more detail, FIG. 9B shows the control panel of FIG.
Schematic diagram and control panel regarding the power distribution function performed by 54
Various indicators (D
SL, D82, etc.) and the blinking of the AC power switch S1.
FIG. As seen in FIG. 9B, when the switch s1 is activated,
Generates AC power and connects τ via one terminal T'BI.
terminal J103. J110 (each terminal E, F, G)
and distributed to each part of the CEOG system. Before too
As explained, the power distribution 60 (FIG. 2) is the A of the system.
C'llll*electricity is required depending on the generation of C electric power.
Generates voltage (e.g. +5V, ↓12V, +15V, etc.)
do. Furthermore, in relation to Figure 9B, the state where AC power is turned on is displayed.
DS1. Similarly, the above-mentioned DCC supply voltage generation
are shown respectively by the indicators DS1 to DS5.
be done. The operation mode or status of the CEOG system is displayed in #I@.
It is shown through the display WDS7 to 0810. In detail
To explain, according to the apparatus shown in FIG. 9B,
"Completed" status means that one terminal of the display 087 is low (CH
Δr RRE A DY ) becomes
This operation is performed using a +15 volt DC power supply.
to display the display DS7, and then (visually
Displays visible chair ready indication. Indicator in the same way
From DS8 to DSlo: "Chair ready", "Recording"
or display the "inspection warning" status or operation mode, respectively.
. With respect to FIG. 9C, circuit 456 includes logic section L3 (10F).
Accepts input VTR8PD1 sent from (Figure)
signal RUNFWD, RUNBKD, or RtJNS
Convert LOW to analog signal. Circuit 456 (Figure 9C
), which is resistor 458 and potentiometer 460 (9th
through the resistance (assembled by adjustment knob P1 in figure A).
and generates an output MTR8PD. This has been explained before
As mentioned above, the motor control device 52. In more detail, the linear
An analog signal sent from the control device 320,
, the rotation speed of the chair 8 (FIG. 2) is controlled by the potentiometer 46.
0 (Figure 9C) to control the speed to the desired speed.
It has the purpose of Circuit 462 appears at switch S2, which is
This is a switch that drives the power to operate the child 8 (FIG. 2). Display DS6 shows "motor power" when power is turned on to the chair motor.
At the same time, the output signal MTRPWR and
and MTR8WON (described below). Figure 9C
The circuit 464 includes a switch S3. This-
It is a temporary switch, and when it is turned on, it instantly displays an alarm.
From about 1J to down to 11J, check the grounding condition of the terminal.
Change from 5TOPSW to terminal 5TOPSW. Terminals as shown below in relation to 2' in Figure 10 [)
5TORPSWI! :5TOPSWLt/-Rose>Susu
Used to turn on and off the switch 750.
Ru. Circuit 466 includes switch S4 and terminal 5T
R8W and 5TR8W each generate a ground condition.
・Used in the same way as the S3 switch. Furthermore, the same
Similarly, circuit 468 also connects terminals R8TSW and R8TSW.
Each generates a grounding condition. Circuit 470 includes switch 5
6 (one toggle switch) is included and this upgrade
In the closed position, the chair 8 (Fig. 2) stops.
Indicates the number of revolutions that should be made before The rotation speed is determined by the operator.
is located in logic section 11' in Figure 10B.
using thumbwheel switches 821 to 824.
Display partially. Switch $6 is in the up position, i.e.
When the chair 8 (Fig. 2) is not in the closed position,
Control is left to the computer to perform automatic control. The circuit 472 is connected to the adjustment knob P2 (FIG. 9A).
A potentiometer 474 is included. This results in -1
15 voltage input is resistor 4, 16 and potentiometer 4
The electric bar is divided into 74 and the result shows the speed of the stripe.
and shows the rotational speed of the stripe cage 76 (Fig. 2).
Represents analog output 5TRIPESPD'Fr. Circuits 478 and 480 include switches S7 and S8.
Each is included with the drive U P CG (Figure 2)
Each shows the movement of the upper F of . The circuit 482 includes a switch 813 that is in the up position.
When it is put in the position, the output Sf:TUP is driven and the reverse 1! FI
M14 (Figure 2) is connected to manual switch 512 (Figure 9A).
(located in the pelleter control unit 450)
to live. Switch 813 is reversed when entering the down position.
The computer processor 34 (Figure 2) controls the
Leave it to the automatic control. Circuit 484 has an indicator DS11 and terminal 5CNL.
Driven by 415 volt output as rT goes low.
be moved. The logic operation of terminal 5CNLIT is as follows.
When driven at part 1.9 (Figure 10L), it becomes low. vinegar
That is, (1) When turning the switch S13 to 1 on,
(2) When the computer scans in the X direction, (3)
When the computer scans in the Y direction. Circuits 486 and 488 include switches S9 and 810.
and operates similarly to circuits 464 and 466. circuit
486 and 488 terminals UPFLSW, DWNFLS
The output status of W etc. is determined by the node in the L4' (Fig. 101) part.
– Used to turn on and off the bounce switch.
It will be done. The circuit 490 includes a switch S11, and when activated,
The lamp 400 (Fig. 2) of the strip cage 76 (Fig. 2)
Output signal shown to illuminate (Fig. 8) @ S T RP
Generate SW. Circuit 492 includes 814 which causes reflection 114
Light emission under the control of [12 (Fig. 2)] will be explained in detail.
and the output signals 5QUAR, RNGL and 5INE are
Square wave, triangle wave (or ramp function) and sine wave function respectively
produce the desired scan according to the The circuit 494 has a pot according to the adjustment knob P3 (Fig. 9A).
It has a tension meter 496. As a result, the reflector 14
You can choose the horizontal speed (¥2 figure). circuit 494
outputs the output signal 08REF, voltage divider resistor 498 and
i^ that determines 500 and countermeasures regarding the minimum reference speed
The desired horizontal scan speed of mirror 14 is shown. Circuit 502 is activated in response to joint knob P4 (FIG. 9A).
A shomeometer 504 is shown. This allows the light source 12 to
Adjust the vertical position of the light beam. With this adjustment, the circuit 50
2 performs voltage division via potentiometer 504.
an output signal V indicating the desired vertical position of the light beam from the light source 12;
Generates ERTPO8. Below, part 110 (Figure 10M
), the potentiometer 5
04 works in parallel with MOVY output from the computer
or any other resulting 110-part transamplifier.
produces an output YDR[VE in response to the signal
The desired vertical position 1 of the light beam from the light source 12 is completed.
. Turning to FIG. 9D, circuit 506 includes switch 51.
4 (Figure 9A) appears. This switch
Operate the left and right movement and stop of the book cage 76 (Fig. 2).
Ru. The movement of the strike cage 76 to the left is output -〇
Corresponding to G M 'r R, the movement to the right is the output child CGM
Corresponds to TR. These two output signals are relay panel 2
0 (Fig. 8), and from there it is further transmitted to the motor 74'.
to the left and right of the strike cage 76 (Figure 2).
The movement is under the control of motor 74'. As seen in circuit 506 of FIG. 9D, switch 81
4 has an "off" position, which has a stripe cage
Movement of 76 from side to side is not implied at all. In addition, the
Circuit 506 includes a switch 814 as shown in Figure 9D.
There is a switch S14 connected to one set,
The outputs LFTSW and RH are set by driving the switch S14.
Drives the TSW to move left and right respectively. Output LFTS
W and RHTSW provide status signals to logic section 62 (FIG. 2).
sent as. For Figure 9E, circuits 530 to 533 appear.
There is. These circuits convert various circuit signals into driver signals.
Used when changing. In particular, circuit 530 provides signal T
WLON (Operator Warning Lamp On) and CHRDY
ON (chair ready) on indicators DS10 and DS7
(Fig. 9A) are changed to lights up respectively. circuit 53
1 is an adjusted +12.3 volt called +RELAY.
supply. This signal will be recalled in connection with Figure 8.
The solenoid/relay inch previously written as
is transmitted to relay 20 to drive the combination of Circuit 532 is an output signal @RELBRK (brake release)
, LITEON (lighting), FLMTRON (flasher)
motor on), FLSHDWN (flasher down)
, TRMTRON (stripe cage motor on)
TRMTRDN (stripe cage down) for each
Change to the corresponding driver signal. Finally, the circuit 533 outputs the output signal 5TRIPESPD (this
This is the adjustment) Potentiometer connected to IF5 (Figure 9A)
Also sent from the center wiper of meter 474 (Figure 9C)
This is the output signal + CG MTR and
-Convert to CG M 1'R. This is relay panel 2
0 (Fig. 8) and is further transmitted to the motor 74'.
, the stripe cage 76 (Fig. 2) is rotated at a constant speed.
let The latter (via resistor 536) is connected to transistor 5
The output TRNCR (Turn
reached by the circuit 533 affected by
will be accomplished. Transistor 535 connects -CGMTR to ground.
Then drive the stripe cage motor 74' (Fig. 8).
do. At this point, the various diagrams from Figures 9B to 9E will be explained.
operator control section 450 (FIG. 9A)
I think it would be appropriate to explain a little bit about the usage of
. Especially how to use it for EOG and VER inspection purposes.
Explain briefly. To perform EOG and VER inspections, the operator must:
You can take actions like this. (1) The operator controls the operator control unit 450 (9th A
CEOG by turning on switch S1 in Figure).
Power the system with AC power and various DC 11wA voltages
to each part of the CEOG system as described above in Figure 9B.
supply (2) The operator turns on switch 513 (Figure 9A).
and outputs signal 5ETUP via circuit 482 (Figure 9C).
generate. At this point, open the shutter 66 (Figure 2).
Ku. In this way, the patient 112 along with the reflection 11114 is
Applying light stimulation generated from a light source (laser) 12
I can do it. In configurable operation, the reflector 14 is predetermined.
[Use switch 812 to move in the X direction according to the special manual
to scan. (Figure 9A... and circuit 4 in Figure 9C)
92). Furthermore, the Y position of anti-tI411
is the adjustment knob ρ4. Also, a potentiometer circuit 502,
MOVY command from computer processor 34 (Figure 2)
Determined by a combination of ordinances. This is explained in more detail below.
Discuss in detail. Reflex 1!14 (Figure 2) Sukisen speed
is the adjustment 71 block [)3 (potentiometer circuit 494 and
is determined by the settings of The scanning cycle time has a period of 0.8 seconds to 10 seconds.
It is better to During scan type operation, it is the display [)S1
'l (see circuit 484 in Figure 9C). (3) As mentioned above, switch 813 is a toggle switch.
Automatic scan when switch 813 is toggled next time
become. When it comes to this type of operation, Skiton
This will be done under computer control. In addition,
Viewer processor 34 completely and exclusively receives patient 2.
You can program the scan pattern speed etc.
can. Another method is to program the computer to switch 81
3 depending on which scanning function you manually selected.
The goal is to make it possible to scan. The horizontal speed of the scan is also controlled by the operator l1 section 450.
Adjustment knob P3 is set so that it can be operated manually.
be able to adjust according to the horizontal speed of either side.
Ru. Furthermore, as another method, the computer processor 3
4 to adjust the vertical operation at the speed determined by knob P3.
It can be adjusted according to the degree of
P3 is simply used to determine the horizontal speed of the scan.
). (4) The operator activates switch S5.
You can reset the system. In Figure 9C
Relatedly, the driving of the switch S5 is the driving of the signal R8TSW.
and informs the logic section 62 (FIG. 2) as shown below.
and processed. The CEOG system can also be used to perform other EOG tests.
It can be done. For example, using operator control unit 450
It is possible to perform inspections that control the rotating chair 3 (Fig. 1).
It is Noh. In other words, (1) the system is
81 switch (as discussed in connection with the
do. (2) The chair motor is activated by turning on switch S2.
(This is displayed on the display DS6). As previously explained, this is circuit 462 (Figure 9C).
as a result of activating signal MTRTWR via. (3) The operator switches switch S5 to circuit 4 in Figure 9C.
Reset the system by entering via 68
. As a result, R8TSW is driven, which further logic section
62 (Figure 2). At this point the chair has returned to its normal position and is ready to rotate.
No, "Ready" status is displayed on display DS7.
. (4) The operator should now, for example, rotate the chair.
You can enter data about the number of times. This is a sliding door
This will be explained in detail using the circuit 44 (FIG. 2).
. (5) When switch S5 is turned on, the chair rotates for the planned number of rotations.
can be rotated. (6) When switch S3 is turned on, the chair will rotate at the scheduled rotation speed station.
It can be stopped before. At this time, the display DS7
A flashing "chair ready" light will appear. (7) At this point, the operator turns on the switch S4 and
Child rotations can be reset and the planned number of rotations completed
It becomes possible to do so. When the planned number of rotations is completed, the chair
will stop automatically. and a flashing “chair ready” display.
is shown on the display DS7. (8) The CEOG system (as seen below)
The rotation continues in response to further driving switch S4.
but this time in the opposite direction to the clock hands (the previous rotation is the clock hands).
(assuming it was in the same direction as )
can be gram. (9) During this operation, the operator must press the button on the computer.
Press the button to command the test results to be printed or
is a character predetermined by the computer (e.g. R
) can be typed. The test results are like this
permanently stored (e.g. disk 42 (as shown in Figure 2)).
) can be recorded. (10) As explained in more detail below, the system
may operate with an automatic reset type of operation.
I can do that. In this method, the reverse rotation of the chair is a slow motion method.
The CEOG system is reset to normal position 1.
Set the corresponding limit switch. at the time
The chair stops rotating. This will be explained in more detail later.
Ru. (11) Finally, as shown below, switch S6 is
Set the number of rotations until chair 8 comes to the point where it automatically stops.
Part-controlled or computer-controlled! Do you want to do it?
Give you a choice. As recalled from the previous explanation
, the number of rotations of the rotating chair is determined by the Ll' section of the logic section 62 (Fig. 2).
Decoded thumbwheels in minutes (Figure 10B)
Switches 521-324 can be energized to locally define
can. When testing patient 2, test station part 4
50 (Fig. 9A) to create a striped cage (Fig. 2).
) can be controlled. i.e. pushbutton switch
stripe cage by energizing switch S8 once.
76 can be folded into a predetermined position. At this point,
Switch 811 is turned on and switch S14 is turned off.
Linear light bulb when placed in left or right stomach position
400 (Fig. 8) lights up, and the stripe cage 76 is at its highest position.
As soon as it reaches the bottom, it starts rotating. During inspection (when X deviation
If switch S7 is turned on even at the point, the strike cage 76
The rotation is automatically stopped and the light bulb 400 is turned off.
Pull the stripe cage 76 up to the uppermost position. Before
As explained in , the rotational speed of the stripe cage 76 is
Control is provided by adjustment knob P2 and circuit 472 (Figure 9C).
This is done by an associated potentiometer 474. Display ID 58 displays the stripe preparation completion state. Display ID59 is RECORDING ON DIS
Display K shows the inspection data of Melter 2 on disk 4.
2 (Figure 2). From Figure 10A to Figure 1ON, there is a discussion of the CEOG system.
6 is a detailed logic circuit diagram of the logic section 62. FIG. Logic section 62 (FIG. 2) receives electronic signals from three sources.
Let's go. Through the EOG interface 30 (Figure 2)
Computer processor 34 and control panel (Figure 9A)
and related circuit switches (Figures 9B to 9E);
Other parts of the CEOG system (detailed below)
There are three sources: The logic section 62
All incoming signals are processed and sent to other parts of the CEOG system.
produces control and display signals that feed the Logic part 62
is the logic part L1 to L15 part and 1 for convenience to be explained below.
This section will be divided into sections 8 to L11 and discussed in detail. 11oA and 10B show the logic section 62 (FIG. 2).
FIG. 3 is a logic diagram of the Ll and Ll' portions. The Ll and L1'1 parts of the logic section 62 have the following four functions.
Do the following. (1) Automatic system initiation for “power on” (2) Resetting the system (3) Activating the inspection warning light (4) Calculations and calculations to determine the rotation speed of chair 8 (Figure 2)
9A and 10A, the switch $1 is actuated.
When the system is turned on, various DC and A
C voltage flows throughout the system. When receiving DC output, timer 628 (10th
Figure A) is adapted to generate an output INIT. superior
is provided to NAND gate 608 and NAND gate 60
8 performs an OR operation, and the output R8T and (inverter
612) generates R8T. NAND gate
The output of 608 is provided to a one-shot device 616;
Its Q output serves as an enable input to a NAND gate 60.
8, the R8T and R8T outputs are 0.8.
A square wave duration of 1 second or more. In other words, onesie
shot device f616, the R8T output is immediately closed.
prevent. For example, a high signal from NAND gate 626
As soon as I received it, if NEARR8T or ZERO
If it goes low. This can be understood more clearly in the following explanation. Further, the NAND gate 608 is connected to the operator control unit 45
0 (Figure 9A) to drive the switch S5.
No-bounce switch 600 in response to R8TSW input
(NAND gates 602 and 604 are connected as shown.
connected> to generate output R8T. (times
468 (see FIG. 9C). Finally, NAND gate 608 has inputs ZERO and N
EARR8T (given to NAND gate 626) and
produces an R8T output when is high or on.
It becomes like this. Input ZERO is 11' (Figure 10B)
This is the output of the decoder 664 in the
The chair rotates in the opposite direction a predetermined number of times to
Display that the data has been changed. In this context input NEARR
8T is the output of the L2'2 section (Fig. 10D), and is as follows.
The chair is in a "backward rotation" motion as shown in
This is a control signal to display. Like this NAND gate
As a result of the actions of 608 and 626 (FIG. 10A), R8
T output is generated and the CEOG system is reset.
Display. The chair returns only a predetermined number of rotations.
Counts to zero whenever rotating in the direction of
A down is performed. Further, with respect to FIG.
4, and at its Q output various selected displays
The oscillator adapted to the device generates an output BLINK and blinks.
gives the effect of For example, operator warning indicator DSI
O (Figure 9A) is the output BL of the circuit 632 (Figure 10A)
It can be made to blink when INK occurs. Additionally, the circuit
632 has a NAND gate 638, which allows
Output TEST 1. t5nibiTOOL-11,! :Seki
ilL, rOR type operation can be performed, and the output −rW
LON (warning light on) outputs TEST I or TO
Generated in the presence of OHI and output BLINK. Seen below
TEST I performs specific operator functions so that
When you move on (for example, the switch in Chair Passing Part 3 (Fig. 10F))
(When controlling manually after rotation by driving switches SA and SB)
, get high. Furthermore, output TOOH1 indicates the rotation of the chair.
Whenever the value set by the operator is exceeded,
' (Figure 10B). Regarding the Ll' part of FIG. 10B, the rotation speed of the chair 8 is
into the computer console or circuit 44 (Figure 2).
Specified under computer system only or
is the thumb that includes switches 821 to 524 (Figure 108).
Local by predetermined reset of wheel switch
Specified by control. In this way, the multiplexer
(MLIX) 650, the computer
Pit 1-4 from Figure 2) or a switch.
Rotation information locally commanded via channels 821 to 824
and multiplex it. Multiplexing of multiplexer 650
The output is given to the latch circuit S52, and further
The latch output is given to AO-A3 of comparison circuit 654
. The circuit 656 in the Ll' portion of FIG. 10B has an output PO8DE.
Analog comparison according to T (representing chair position information)
to the chair via the device 658 and the NAND gate 660.
A certain reflected spirit 350 (FIG. 7A) is a photodetector 35.
Output PO8CLK is emitted whenever the output is set to 4.
live. Output PO8CLK is the CK terminal of counter 662
generates a clock output at This counter 662
counts up the number of revolutions of the chair (e.g. clock hands)
(while rotating in the same direction as the direction) and count down the rotation speed in the opposite direction.
(for example, while rotating in the opposite direction to the clock hands)
It is a drop-down counter. Output QA of counter 662
-QD provides 5o-83 output to computer 654
. Digital comparator 654 thus calculates the actual rotation of the chair.
Compare the number with the desired number of rotations, and when the numbers match, the ratio
Comparator 654 produces an output MATCH. Counter 662 can be counted by logic output Go.
(This is shown in Figure 10D as explained below.
Emitted by the Go flip 70 knob 752 in the Noshi 2 part.
born). Counter 662 is R3T (system reset).
(representing a cut) occurs and is reset. cow
The up or down count of the counter 662 is 1lail.
Output DOWN (UP/DOWN in Part 2 of Figure 10D)
(generated by flip 70 knob 772)
Determined by The output QA-QD of the counter 662 is
the chair rotation is completed.
At the same time, a ZERO output is generated. (Rotate counterclockwise after clockwise direction). ZERO out
The force is connected to circuit 618 (already described in connection with Figure 10A).
Ru. Circuit 656 (returning to FIG. 10B, the output of comparator 658
is sent to the instep stabilizer 666 and sent to the NANO gate 660.
Generate Q output, output poscLK is compared 11658
or the minimum depending on the output coming from the monostable @1f666
It will have a period of . The first part of the circuit 668 consists of NAND gates 670, 672 and
and 674. and inverters 676 and 678.
Inverters 676 and 678 meet the following two conditions.
The clock output is sent to latch circuit 652 below. (1) When locally controlling the rotation speed of the chair, use the 10th
as specified by closing switch S6 in Figure B.
The data is latched by the latch circuit 652 using an AND gate.
Controlled by the R8T (reset) signal received at port 674.
(from switch S6 through inverter 676)
). Also, this R8T signal
Latch via OR gate 672 and inverter 678.
is sent to the CLK output of circuit 652. (2) Specified by opening switch S6
When controlling the chair rotation speed with a computer, use the latch.
Data is latched by the circuit using AND gates 670. Sui
When activated by the output from switch S6, the OR gate
5TR sent through 672 and imperter 678
By OBX (computer driven strobe signal)
controlled by Switch S6 is operated by operator control section 45.
Toggle switch correspondingly specified in 0 (Figure 9A)
I would like to be reminded that I am close this switch
This causes a power interruption and the AND gate 670 is
– Disconnects a computer-controlled latch that brings the output to
AND gate 674 has a data reset function.
Produces a high output that performs a control latch. On the contrary, the switch
When S6 is opened, AND gate 670 is computer controlled.
Provides +5 volts (high) to enable control latch.
, AND gate 764 is disabled to reset the control latch.
It will block the Finally, with respect to circuit 656 of FIG. 10B, as described above,
The input PO8DET is the counter in the chair 8 (Figure 7A).
Analog that appears when the light beam coming from the radiation pattern 350 is detected.
It is a log signal. This ray is transmitted to the comparator 658 (Fig. 10B).
), whose negative input is the level detection potential
regulated by the yometer P2. When a ray is detected
, comparator 658 is a one-shot device f666 (preferably
has a one-shot duration of 0.25 seconds)
and the NAND gate connected to the output of comparator 658.
to maintain the output PO8CLK sent from the port 660.
Make it. This means that NAND gate 660 is connected to comparator 658.
Performs the 0RIII function between the output and the one-shot device 666.
It means that you are doing something. In this way, the circuit 656 outputs
ensure that the force PO8CLK is of the minimum allowable duration;
The output PO8LK is used as a clock input to the counter 662 (
It is sent to the L2' section (counting the rotation of the chair), and then to the L2' section (the first
0D diagram). Figure 10C, Figure 100(1) and Figure 10E are respectively
L2. of the logic section 62 in FIG. Details of L2' and L2'' parts
It is a detailed explanatory diagram. Figure 10D(2) is Figure 10D(1)
This is a diagram for explaining the operation time of the section 12" in the figure. Basically, the sections 12, 12' and 2" are the output signal 5.
TR8W (start switch), 5TOPSW (start switch)
top switch), R8T (reset), 5TRL IM
(start limit switch), MATCH (chair
(indicating that the number of rotations matches the predetermined number) is accepted. L2. The L2' and L2'' sections perform various logic functions.
Drive the logic circuit as shown below and set the following signals to the correct sequence.
Occurs in Kens. CHRDYON (chair ready),
RUNlB (motor start), RELBRK (brake
remove), FWD (proceed), R8LOW (proceed gradually)
Do), DOWN (countdown). seen below
In addition to these, there are also input/output signals that can be accepted or
tell. In particular, with respect to section 12 of Figure 10C, the three flip-flops
The drop device (cross-coupled NAND gate) is
Installed as follows. (1) RLJN flip-flop (NAND gate
700); This controls the chair motor through the inverter 701.
When the motor is running, it generates output RUN1B and this output
The force is sent to section L3' (Figure 10G). flip 70
The output hRUN from Tsubu 700 is the same as the output VANBKRL.
Together (at NANO gate 702) OR gate processing
and the motor is running (indicated by RUNIB).
) or when a manual movement of the chair is indicated.
! (by MANBKRL from part 13 of the 10G diagram)
, generates the output RELBRK (release brake). (2) Forward/reverse flip 70 knobs (NAND gate 70
4): This produces an output FWD. This is with the chair in front
It becomes high when moving in the direction and low when moving backwards.
Become. (,3) RUN 5LOW flip flop (
NAND gate 706): This generates an output R8LOW
When the chair moves gradually, it becomes low. from NAND gate 704 via inverter 708.
output FWD from device 1706 (most ten N△ND game)
The chair should be tilted backwards as occurs when feeding
Please note that it only moves gradually. More equipment! 7
06 is started by output R8T and the operator
When you reset the system, the chair will gradually rotate backwards.
This operation is intended to return the chair to its normal position.
Please be careful what happens. As explained previously, reset the CEOG system.
Recall that signal R8T is generated. 10th
Regarding diagram C, input R8T is output via inverter 710.
Transferred to lip 70 knob 712, flip 70 knob 7
Resulting in 12 resets. As a result, the output MECRD
Y (to NAND gate 714) goes high. M.E.
For CRDY, chair 8 presses the start limit switch 356.
The NAND gate 714 outputs CHRDYON.
goes low when occurs. CHRDYOH occurs.
when signal HLDBLNK goes low. child
The signal HLDBLN, associated with Figure 10D(1) below, is
Occurs due to hold flip 70 knob explained as
be done. Furthermore, Shin@CHRDYON (chair ready)
) is applied to circuit 530 (FIG. 9E) where the output C
HRDYON, which further displays the display DS7 (
(Fig. 9B), and the state of "chair preparation" is performed.
The status will now be displayed. Furthermore, with respect to FIG. 10C, the system reset is f
No. 1 RS 1- is checked via inverter 710.
Provided as a clock output to the configuration preparation flip 70 knob 716.
From there, a Q output is produced to NAND gate 718. Open the start limit switch 356 on chair 8.
to indicate that the chair is not in its normal position (reset)
Shin@S King RLIM becomes high (+5 volts) and inva
The output STRLIM of data controller 720 goes low. As a result
NAND gate 722 (this is STRLIM and 7 rip
between the Q outputs of the 70-tube 716 (which performs the NDII function) is
, get high. At the same time, the output NAND gate t-718 is
output (STRLIM and Noritsubu 70 Tsubu 716)
As a result, the low output (STARTLOOK) is maintained.
Acts on star 1 ~ terminal of run flip 70 knob 700
do. This means that chair 8 (Figure 17A) is in its normal position (
This indicates that a reset is requested. fruit
In this case, the R3T will use the starting output as the front '15/rear slope.
The output FWD is given to the knob 70 and the knob 704.
- indicating backward rotation. At the same time, signal R8T is
LIN SOW flip 70 knob 706 start
The output R8LOW becomes low due to the force, and the chair's low
Indicates fast rotation. In summary, the reset operation is performed when chair 8 (Figure 7A)
Rotate in the dipping direction each time, and return to its normal (reset) position.
I will be asking for a place. Reached normal (reset) position
When the start limit switch 356 is activated
TRLIM goes low and STRLIM goes high. So
As a result, the INAND gate 718 closes, and the NAND gate 7
22 goes low and the run flip-flop 700 is reset.
will be played. Therefore, the output of clip 70 tube 700
RU N goes high and output RLINIB goes low.
(Motor 8 (Fig. 7B) turns off), the other output
RELBRK goes low and fail-safe circuit 326 (
7A and 7D) and linear servo control lIF52
0 and brake relay 322, and motor 50 is activated.
Braking is applied to stop the rotation of the chair 8. In addition, STRLIM (inverter 720) and free
When the Q output of the top 70 knob 716 goes low, the NAND
Gate 722 goes high, resulting in flip-flop
1E cRDY is started. centre
When it is necessary to reset the flip-flop 712
, signal GOB (from Figure 10D). ffi@GOB rotates chair 8 (Figure 1). signal
G OB is RUN (low level in flip-flop 700)
coming from the NAND gate) and the ANDed t! A structure
R before the preparation flop 712 is turned off.
Make sure UN flip-flop 700 is turned on.
keep This is because MECRDY is NANDing the signal GOB.
-1-752 (see Figure 10(1))
I need help moving. Additionally, the check mechanism preparation flip-flop 716 is reset.
The set (R) input is resistor 730 (this is the shutter 732
) through the NAND gate 72
Note that it is connected to 8. in this way,
NAND gate 728 performs ANDI on the inputs to it.
Perform Noh. To explain in detail, when RtJN goes high, N△N
D gate 722 becomes a low output, resulting in the inverter
732 output goes high, resulting in flip 70
The Q output (MECRDY) of block 712 becomes high and the check
The lock mechanism preparation flip 70 knob 716 is reset.
Remove the Q input from NAND gates 718 and 722, respectively.
I will have to leave. As explained above, resetting the system is
As shown, slow backward rotation of the chair is its normal (reset)
Continue until you reach Iso, and then proceed to the spot on chair 8 (Fig. 7A).
It is detected when the start limit switch 356 is activated. Regarding Figure 10D(1), regarding the chair rotation starting operation,
I will explain. Start switch 84 (Fig. 98 to 1)
00 figure), the signal 5TR8W (described above) will be added.
bring momentum. This signal is part 12' in Figure 100(1).
If you receive it with a no bounce switch (flip 70 knob)
device) 750. NANO gate 7521. child
This is the input coming from the flip 70 knob 712 (Figure 10C).
In connection with force MECRDY (mechanical chair preparation),
Generate force XYZ (this is a forward/backward flip
As a reset input to the 70 knob 704 (Figure 10C)
Sent). This is flip 70 knob 704 in front of the chair
Ensure that the output FWD is consistent with the directional operation.
Ru. In addition to this, the NAND gate 754 G,t
Perform OR operation between Z and input (STR8WHOLD>
Generates an output GOB that does not exist. The latter is 70 Go flips.
758 is opened and used as a clock input. Out
The power GOB is also driven by RLJN flip 70 knob 700
(Figure 10C). When chair 8 (Fig. 2) begins to rotate, the number of rotations is 108.
Counted by power distribution in figure. a predetermined number of
When the rotation is finished, the output MATCH changes to the ratio as explained before.
generated by comparator 654 (Figure 10B). At this time
A NAND gate 762 that performs an AND operation on the input F
Detect DW, Go and MATCH and flip 70
drive 764. Accordingly, flip-flop equipment
@764 receives the next PO8CLK pulse.
It is driven when the Explaining Figure 100(2) of the clock diagram in more detail.
do. Pulse PO8CLK is mainly a lock pulse.
, based on which the number of rotations of the chair is counted, preferably
In this configuration, the chair receives the first PO8CLK pulse.
Make a quarter turn before turning. 10D (2> Figure
It is assumed that the number of rotations is predetermined to 3 times.
When the 62nd and 1/4 rotation is completed, that is, 3 times
When the eye starts rotating, the comparator output MATCH is generated.
live. And Flip 70, Tsubu 766 is the next PO8
Prepare to accept CLK pulses. Regarding Figure 10D(1) and Figure 10D(2>),
The Q output of the flip 70 knob 766 is the one-shot device 7.
68 for a predetermined period of time (preferably 0.1 seconds).
(preferable) Q output is generated at the rear end of PO8CLK.
do. This output is defined as signal REVR8. this superior
is the forward/backward reset of the Noritsubu flop 704.
Orientation flip 70 given to knob 704 (Figure 10C)
This is a negative pulse that causes FWD to go low and chair 8 (see Figure 2).
) results in rotation in the backward direction. As best shown in the clock diagram of Figure 10D(2)
Then, when the edge of pulse REVR8 becomes positive, 7rip 70
Tube 770 enters the on state and generates the output GOC
. In response, output GOC goes low, resulting in NA
Free signal is output via ND gate 772 and inverter 774.
Drives flip-flop 776. (10D(2>Fig.
(See waveform NEARR8T). Output NEARR8T is a chair
The backward operation of child 8 (FIG. 2) is displayed. In this way, for the 10D (2> figure), the chair is moved 3 times and
When the chair rotates a little, the chair stops and the motor starts moving.
It reverses and starts to rotate backwards. In response to this, the counter 66
2 (Fig. 108) counts the predetermined number of revolutions three times.
When the output MATCH is generated. But this time the output
FWD goes low and NAND gate 762 also responds to this.
generates a low output. Here, flip-flop 766 has its reset input
In series with NAND gate 778 and inverter 780
Please note that eNAND gate 7 is connected
78 is an OR operation between input REVR8 and input R8T
Do the following. With this arrangement, flip-flop 766
It is reset under two conditions: (1) Negative pulse
Occurrence of REVR8 or (2) Reset manual R'ST
occurrence. Up/down flip 70 nb 782 is a flip
When the flop 766 turns on for the first time, its Q output
is driven by the counter 66 and generates an output DOWN.
2 (Figure 10B) performs a down count type operation.
Show that you are there. For FIGS. 10A and 10B, counter 662
reaches zero count, the accorder 664 outputs Z
Generates ERO. Furthermore, N△ND gate 626 (the
Figure 10A) with input ZERO and NEARR3T.
Perform an AND operation on the NAND gate 608, and
The resulting output R8T is generated by the arrangement shown in Figure 10A.
Ru. 10D (2> Please refer to the clock diagram in Figure 1.
As mentioned above, for FIG. 10A, this output R8T is
One shot @l [As a result of the operation of 616, 0°1 second
Or it won't last. The one-shot device l616 is
Then, the NANO gate 608 is shut off. When R8T occurs, the 7th lip-flop 776 (10th D
(1)) is reset and the output NEARR8T is low.
become. Therefore, the swivel chair 8 (Fig. 2) faces backwards.
Displays the end of the operation. While reversing the rotation of chair 8 (FIG. 2), the signal REVR
8 goes low! As a result, automatic stop operation may be performed.
Please note that you can Details in Figure 100<1)
To explain, the automatic shutoff switch 784 is closed.
When REVR8 becomes O~, the NAND game
S T'
Generates OP 2. Output 5 TOP2 is RLJN flip
Stop flip-flop 700, hold flip-flop 7
Drive 90. The output HOLD is sent to the NAND gate 792 (and BLI
NK and ANDed to yield HLDBLNK
, as explained earlier, this latter is CHRDYON (
NAND gate 714 for the purpose of generating (chair ready)
(Fig. IOC). In addition to this, HOLD
The output is sent to an AND gate 756, the other input is a flip
Accepts the start output of the knob 750. flip
70 Tsubu 750 is the start switch (signal 5TR8W)
(when received) is driven by the input. When you turn on the start switch like this, chair 8 (Fig. 2)
) results in reverse rotation. Chair 8 can stop automatically, or you can turn on the stop switch.
It can also be stopped manually by generating signal 5TOPSW.
Can be stopped. The latter signal is the start to flip 70 knob 794.
It is a dynamic input that results in the generation of an output STO. the latter
The output is cut off by cutting off the RLJN flip-flop 700.
Stop the rotation. Finally, manual restart for the purpose of reverse rotation of chair 8 is
As explained before, RUN flip 70 tube 700
After driving for a while, HOLD flip 70 knob 790
(predetermined result of automatic stop via STOP2)
) is now reset via the RLJN input.
Ru. With respect to FIG. 10E, section 2'' is the operator control section 4.
50 (Figure 9A) by activation of switch S2.
It accepts the input MTR8WON from the circuit 462 that is
The input RELBRK coming from circuit 532 (Figure 9E)
Accept. The brake associated with chair 8 (Fig. 1)
To remove both MTR8WON and RELBRK
Both sides need to be high, and this is done by the inverter.
The output of 802 is set high and the inverter 802 is
turns on transistor Q1, thus turning on transistor Q2.
Turn off. As a result, BRAKE goes high,
Dynamic brake relay 322 (Figure 7A) is released.
(8!1 group) is done. However, MrR8WN is RELBRK17)
When one of them goes low, the output of NANO gate 800 is
goes high, the output of inverter 802 goes low, and the output of inverter 802 goes low.
Transistor Q1 is turned off and transistor Q2 is turned off.
is turned on. This conclusion is 51! BRAKE goes low
, thus dynamic brake relay circuit 322 (first
Figure 7). The logic L2'' section (Fig. 10E) also has a manual brake on.
/off switch 804, which is in the downward position
The 2'' part of the timer can perform the above functions manually.
so that Conversely, when switch 804 is in the upward position
In some cases, the brakes must be activated to manually position chair 8.
Application is removed. In this case, the operator control section 45
Operator warning indicator DSIO at 0 is TESTI
goes low, resulting in it being driven. 10F and 10G are L of the logic section 62 in FIG.
3 and a detailed design drawing of the L3' section. First, to explain Fig. 10G, the L3' section is the input R
LJN1B (This is the RLJN flip in Figure 10D(1)
) and FWD (10D (which is the output of
1) Exiting the front/backward knob 70 knob 704 in the figure
power). Then press the switch SC at the 3' section.
Manually rotate chair 8 (Figure 12) using a button switch.
Operator driven to do so. NAND gate 87
0 and 878 perform an AND operation on the inputs that come there.
Now. NAND gate 872 connects the outputs of gates 870 and 878.
The force is 0R5filu. Like this NAND gate 8
72 will produce an output under either of the following two conditions:
. (1) Manually operate switch SC (VANMODE>
or (2) in non-manual operation.
When receiving N flip-flop output, NAND gate
The 880, 882 and 884 all operate the same way.
Ru. In other words, the NAND gate 882 meets the following two conditions.
Generate output under either, i.e. (1) non-manual
Forward/advanced flip-flop output in formula operation
when receiving FDW, or (2) in manual operation.
Drive switch SD (for commanding backward rotation)
and when. The NAND gate 876 must meet the following two conditions:
When the output RUNFWD (this is shown in Figure 10F, part 3)
) occurs. (1) The command to rotate the chair is given by hand.
(2) when moved or done automatically; (2) behind the chair;
Direct rotation is commanded manually or forward rotation is commanded non-manually
When it is done. Finally, NAND gate 886 and inverter 884
are both flJNBKD (this is
(given to part 3 of Figure 10F). (1)
(2) when the operation is commanded manually or automatically;
Dynamic slow rotation or automatic forward rotation is commanded.
when not. For Figure 10F, the input RUNFWD is an operational amplifier.
Allow current to flow to the negative input of 822. However, this
current cannot be applied immediately. It has an RC time constant of resistor 830 and capacitor 832
This is because it is related to. The voltage entering operational amplifier 822
The current produces a voltage output from operational amplifier 822. this
Preferably the voltage output is +5 volts, which is
A potentiometer P" associated with amplifier 822
It is adjusted. Input RLJNBKD (this is specified in the logic part of Figure 1oG)
RLJNFWD) is mutually exclusive with the commanded RLJNFWD).
The other output of operational amplifier 822 is generated. As mentioned above, the voltage output of this operational amplifier 822 is
5 volts is preferred. Finally, the input RUNSLOW is set so that the RUNBKO output is
Allows to decrease in amount <-5 volts to -2
, preferably reduced to 5 volts). R8LOW is only on during system reset (previously
commanded by the signal R8T mentioned above). The above input signals processed in the three parts are each as previously described.
12 of Figure 10C, Figure 100(1) and Figure 10E
．． Mainly begins with L2' and L2''.
(Figure F) has switches SA and SD to switch the chair mode.
50 (FIG. 2). and
For example, for the purpose of testing the system. Inputs RUNBKD and RUNFWDLt each 'rt
sent to physical couplers @11810 and 824. Enter
When the power RUNBKD goes low, the current flows through the resistor 812.
flows, closes the NPN transistor 814, and a negative current flows.
Applied to operational amplifier 822 via resistors 816 and 820.
It brings about the effect that can be achieved. As a result, the operational amplifier 1B22 is
Generates negative output. On the other hand, when RLINFWD goes low, the optical
Plastic mounting H824 allows current to flow through resistor 826.
, turn off transistor 828, and turn off the operational amplification.
Negative I to the device 822! ! Let the input flow. As a result,
Operational amplifier 822 produces a positive (+15 ports) output. Input R8LOW is for non-manual operation of chair 8 (Fig. 2).
This low input is connected to the optical coupler.
Detected by device 1826. Non-manual operation is indicated when VANπn goes high;
Same as when given to NANO gate 829 <R8L
MANRLIN, which occurs together with OW, is connected to the inverter 82.
It can be changed to R8LOW by 6. optical cup
The controller 812826 outputs a PNP signal in response to detecting a low input.
The transistor 832 is turned off, and the operational amplifier 11822 is turned off.
A negative voltage is sent to the negative human power. But resistor 834 and
and 838 are the corresponding resistors 816.830 (mentioned above)
and has an impedance value twice that of 820.834.
Therefore, the input to operational amplifier 822 is half the negative voltage.
It just flows. As a result, the operational amplifier 1822 is
It generates an output that is half of the output that was generated. When switches SA and SB are in their normal positions,
The output of computational amplifier 822 is connected through resistors 848 and 850.
and is sent to the output terminal VTR8PD1. This output is
Analog input to s456 (Figure 9c), the circuit
456 generates the other analog output ~1TR8PD
It is a linear servo control device F320 (Figure 7A)
The motor that moves the chair 8 serves as a speed display input to the
Determine the operating speed of 50. Therefore, RUNFDW
and the low outputs on RtJN8KD are positive and negative voltage outputs.
Generates power VTR8PD1. This is the front direction of the chair and
Corresponds to full speed rotation in the direction of erosion and erosion. Furthermore, low power R8LOW is a negative voltage output VTR8PO
yields I, whose value is halved, resulting in M at half the speed.
Rotate in the opposite direction. The third part includes switches SA and S that can be driven to manual position 1.
There was B. In this position, the output VTR8PD1
of operational amplifier 822 via potentiometer 852.
Connected to the output. As a result, the motor speed [MTR8P[
) can perform m sections of 1. Furthermore, switch 8
When B is placed in the manual position, the output MAN'R'LJN is low.
' to display manual operation. On the other hand, the output MANM
ODE going high produces the same display. In addition,
EST1 (this was previously explained in connection with Figure 10A)
) goes low and operator warning display ID5I0 (No.
Figure 9A) is the result of output TWLON < Figure 10A) flashing.
Start. Finally, part 3 is the zero bias potentiometer.
There is a potentiometer 844 with [NFWD and R
When both UNBKWD is high, that is, R(J
Both N F W D and RtJNBKWD are off.
When > m-thick amplifier 822 output is zero volts
It is used for the purpose of confirming. 10H and 1101 are L of the logic section 62 in FIG.
FIG. 4 is a detailed diagram of the 4th part. 4 and L4'
The logic circuit of the section is the operator rllll 111 section 450 (
Accepts signals coming from various switches shown in Figure 1@9A)
and the flasher 70 and stripe cage 76.
Motors 68 and 74 (Fig. 2) move up and down, respectively.
The limit [-] signal coming from the switch is turned off. When such a signal is received, the logic circuit of L4 and L4' section
The relay panel 20 (FIGS. 2 and 8) described above
(Fig.) generates a signal to perform the relay and τ flasher 70 and
and lift the stripe cage 76 up and down, and also move the stripe cage 76 up and down.
Rotate the lie cage 76. Finally 14 and L4
'The logic section is connected to the processor 34 (Fig. 2) by the 7
and a status output signal indicating the status of the stripe cage 76.
Occur. For part 4 of Figure 10H, INIT goes high.
When the Noritsubu flop 900 is driven, the result is that
The Q output of becomes low. Limit switches 902 and 904 are upper and lower limits, respectively.
a lower limit switch and associated with the visual motor device 16;
Ru. To explain in detail, the motor 74 in FIG.
Preferred embodiment for raising and lowering the tripe cage 76
With switches 902 and 904 (Figure 10H)
Ru. Switches 902 and 904 are normally off, but
The stripe cage 76 is moved to its upper limit by the motor 74.
and are turned on at any time when the lowest limit is reached. At the beginning of the system, the stripe cage 76 is usually
in its upper limit position and switch 902 is therefore on.
, switch 904 is off. Furthermore, when resetting the system (R8T), the upper limit
Operate switch 902 (L IMUPOF)
When the motor energizes switch s8 (lowers the stripe cage)
To get...DNCGSW), up flip 7
0 knob 906 and down flip-flop 908 are N
TRMT to drive the motor via AND gate 910
RON goes low), lower the stripe cage 76
(TRMTRON goes low)
). Driving the motor 74 to lower the stripe cage 76
is by the signals TRMTRON and fKVlRDN.
Each is performed as previously described in connection with FIG. strike
When the lower limit of the lie cage 78 is reached, the switch 904
is turned on and [Striped Ready
RDY) is the NAND gate 912. Inverter 914F
3 and NPN transistor 916. At this time, switch 511 (operator control section in FIG. 9A)
450) is energized and the striped cage lamp 400
and stripe gate rotation motor 74' (Fig. 8).
It must be turned on. NAND gate 9
12. by circuits 532 and 533 (Figure 9E)
TRN through driven inverters 918 and 920
Output LITEON via CG! occurs and further outputs
Relay ITEON and +CGMTR/”-CGMTR
- panel 20 and motor 74' (FIG. 8). Related to Figure 8, when LITEON goes low, the power
is applied to the striped cage lamp 400, while the input
-CGMTR and +00MTR to motor 74'
and the stripe cage 76 due to the influence of the motor 74'.
Recall that forward/backward rotation is provided. The direction of rotation of the stripe motor 76'' (Fig. 8) is determined by the operator.
switch 814 in the controller 450 (Figure 9A).
Therefore, it is ordered. This is the input LFTSW and R)-
Selectively output ITSW to NAND gates 922 and 924.
Inverter 926 and 9
Output DATIN13 and DATIN14 via 28
is sent to computer processor 34 (FIG. 2). DAT
IN13 is rotating [stripe normal J status, D
ATIN14 indicates a "stripe on" state. Finally, the signal LYTEON (which is a strip
command to drive the cage lamp 400 (Fig. 8)
) is connected to switch S7 via flip-flop 906.
(UPCGSW) or NAND gate 91
2 and inverter 918 to drive the stripe cage.
It is prohibited when raising the Similarly, the output TRNCG (
command cage rotation) is NΔND goo (912 and
is prohibited from being generated via the inverter 920.
Ru. Regarding Fig. 101, there is a flip-flop in the L4' section.
It has 950. This is activated when the system is powered up.
However, at this time, the Q output of Noritsubu 70 and Tsubu 950 is N.
One shot via AND gates 952 and 954
Device I! Sent to 956. This produces a short (preferably 0.15 seconds) pulse Q.
Ru. NAND game I-952 corresponds to the input that comes there.
The NAND gate 954 performs an OR operation, and the NAND gate 954 performs an OR operation.
The output of ND gate 952 is TRNTR0N and L.
IMDONF (The latter two signals are shown in Figure 10H.
(sent from the department). Q output of one shot device W956 is NAND gate 95
8 output FLMTRON (flasher motor drive)
) and the winner sends a high signal to circuit 532 (Figure 9E).
Calibrate the input and generate a low output FLVTRON. child
This provides power to the 7 lash motor 68 (FIG. 8). Furthermore, the Q output of the one-shot device @956 is flip 7.
Reset the 0 knob 950. The L4' section also accepts the human-powered LIPFLSW (this
The operator system shown in Figure 9A is used to raise the flasher.
By driving the switch S9 in the control section 450,
). Input UPFLSW connects flip-flop 960
and its energizing output is applied to NANO gates 952 and 9.
54 (TRNTR0N OJ: (7L
NAND games unless blocked by IMDNOF
(sent to port 954). As a result, the flasher up
When switch 89 (Fig. 9A) is energized, the flasher mode is activated.
Automatically drives the motor (FLMTRON). Similarly,
When flasher down switch S8 is turned on, DWNFL
Drive the flip 70 knob 962 via the SW and its output.
The force is applied to the FLM through NΔAND gates 964 and 958.
Generates TRON (also NAND gate 964 generates TRON)
Blocked by RMTRON and L IMDNOF
(assuming you haven't). W41 OJ diagram is a detailed diagram of the 15th part of the logic section 62 in Figure 2.
It is. The 5th part generates 5YNCIN and 5M5S△MP
do. This is the Photo Stimulator 72 (Figure 2).
The flasher 70 is activated through the This operation is EOG
computer via interface 30 and 5
This is done under the control of processor 34. In general, 5
The part energizes the photostimulator 72 and fires the flasher.
At 70, the bird sends a pulse to the 1m franchise regarding the command.
cause a nuisance. The CEOG system also has photo-steel
When patient 2 requires stimulation via emulator 72
(e.g. 2.5 ms, 5 ms, etc.)
It is possible to In this way, the electrode inspection data
may also be sent to computer processor 34. Regarding the 1st OJ diagram, the 15th part has a flip-flop 97
0 and 972, these are power-on initial setting inputs.
(INIT> or Computer On Initial Settings Input (C)
OMPINIT> is reset, and the NAND gate 97
4 and flip 70 tube 9 via inverter 976
70 and 972. Q output of flip 70 tube 970 is one shot device W1
978 and series connected one-shot device 1980
by driving short (preferably 10 microsecond) pulses
, and this pulse is longer (preferably 5 ms)
) separated by time periods and such output is
5MSSAMP. The latter is an “initial sample”
” pulse to circuit 250 of FIG. 6D.
given, it is the output SAMPLE (in Figure 6A)
(used for ADC)
Ru. The flip 70 knob 972 is connected to the sole through its -◇- output.
Drive the node/switch combination 982 to turn the switch.
Turn it off, one shot @I! 980 with variable time control
(via potentiometers 984 and 986)
). As a result, one shot @@980 is adjusted and 5
the beginning of a duration of less than a millisecond (preferably 2.5 milliseconds)
period sample pulses can be given. One shot @ff1978 is flip 70 tube 970
Driven by the falling edge of the pulse output from the Q output of
Please note that This fall is D input D
OUT13 (This is the computer processor 34 (Fig.
Flip 70 according to ) consisting of Go bits coming from )
Driven by knob 970. DOUT13 is typical
specifies a predetermined pulse that occurs at intervals of 5 milliseconds. Similarly, processor 34 controls the D input of flip-flop 972.
Send the input DOUTI 1 to the force, and as a result of this, one
Adjust the shot 980 to set an initial sample pattern of 2.5 ms.
It works to generate a pulse interval. Flip 70 knobs 970 and 972 are converter 98
computer-generated streams sent via 8
To be clocked according to the lobe input 5 TROBO
Please be careful. 5TROBO is shown in Figure 2 as shown below.
interface 30 (first
(see description of 1D figure). Furthermore, regarding the Noshi 5 section in Figure 1 OJ, the processor 34 (
Figure 2) generates the flash bit DOLITI2 and
Sent to the D input of lip 7O tube 990. The latter is a con
The strobe 5TROBO generated by the computer
is clocked. The Q output of the flip 70 tube 990 is connected to the inverter 994.
via a short-term III (15 microseconds is preferred) square wave
occurs. to transistor 996 as emitter input
The collector output is the flasher synchronization pulse 5Y.
Generate NCIN. 5YNCIN is one short pulse
preferably have an amplitude of 25 volts, which is
The flash that is sent to the stay simulator 72 and generated there
synchronize the files. Flip 70 knob 990 is an operator operated reset (
R8T> or NAND gate 998 and inverter
Q output of one-shot device 992 sent from data 999
reset by . Figure 10 is a detailed diagram of the L8 section of the logic section 62 in Figure 2.
be. The 8th part is the feed from the X mirror signal (XBACK>
YI114 (Fig. 111112) (more details) using the bag.
To be more specific, the signal sent to the Y reflection circuit of Gorge 14 @YFIX
) to generate the cylindrical shape 1!18 (No. 1) of the inspection station 4.
Correcting the distortion of the light spot (laser spot) in Figure 1)
. This Y pole is affected by laser 12! It is located above the head of 2.
Therefore, the cylindrical shape W18 is directed downward.
Ru. 10th, regarding the figure, the L8 part is the analog from #A14
Accepts input XBACK, which is a signal. isolation
The operational amplifier (voltage follower) 1000 has a positive input XB.
ACK and negative bias/gain adjusted input (by
and gain are controlled by potentiometer 1002 and gain, respectively.
and 1004)
is sent to the positive input of multiplier 1006. Multiplier 1006 increases
Square the output of the scaler 1000 and isolate the result.
output via operational amplifier (voltage follower) 1008
Occurs as YFIX. This YFIX will be explained below.
10 (Figure 10M). As a result of the operation of the L8 section, the light source (laser) 12 and the cylindrical shape
118 (Figure 1) Vertical angle of gaze in the dark and patient 2's eyes
and correction or compensation of the vertical angle of the line of sight of the cylinder 1lIl.
Atonement will be made. FIG. 10L is a detailed diagram of the 19th section of the logic section 62 in FIG.
be. Normally, part 19 is the MOveX register (described below).
receives and stores four bits coming from , 4
The two bits are specified as follows: DOUTlo (Go X bit): This bit will be used later.
According to the circuit in Part 110 (Figure 10M) to be explained,
It works to scan the cans in the X direction. DOUTI 1 (CMPSIME): This bit
Can Chin is MOV
Scan in the X direction using bits from to 9.
and the deflection in those 1024 increments is -306
It works so that it is within a range of +30° from . DOLITl 2 (CMPSHTR): This bit is
It acts to open the shutter 66 (FIG. 2). DOUTI3 (YSCAN): This bit is scan
To the signal from part 110 (Fig. 10M), the mirror is explained below.
In response, it works to scan in the Y direction. As mentioned above, the output DOUTIO to DOUTI3 is
via NAND gate 1024 and inverter 1025.
and each 7 lip 70 lip 10 by STRBMX
Notice that it is strobed between 20 and 1023.
I want to be The Q output of flip-flop 1020 is NAND gate 1
026 to form the output X5INE. NANO game
port 1026 has its output connected to switch 513 (operator
is connected to the control unit 450 (located in FIG. 9A),
Set the auto/set amplifier switch 813 to
” position (i.e. DOUTlo), X5IN
Generates E. X5INE, which is the output of inverter 1028, is NANO
Q of flip 70 knob 1022 at gate 1032
It is ORed with the output and is connected via transistor 1036.
and generates output 5HUT. 5HUT is mirror 14 (second
) and the associated shutter 66.
. Furthermore, X5INE coming from inverter 1028 is N
In AND gate 1030 and inverter 1034
AND processed with the Q output of flip 70 and knob 1021.
and generates an output CMPSINE. Each of inverter 1028 and NAND gate 1030
Their outputs are ORed in NAND gate 1038.
The latter has a base control input to transistor 1040.
Send power. Transistor 1040 has collector output 5CN
Generate LIT. 5CNLIT has an isthmus 14 and a shutter 66 (Fig. 2).
The associated laser 12 operation is displayed. The Q output of the flip 70 tube 1023 is a wired OR connection.
Transistor 10 via connected inverter 1042
Note that it is sent to a base of 40. In this way, D
The presence of OLITl 3 (YSCAN) makes the scanning light
drive Every time the computer is turned on or turned off
, NAND gate 1044 and inverter 1046
The input signal CMPINIT generated via Noritub 7
0 knobs 1020 to 1023 are reset. INI
When T occurs, the operator must reset the system.
emitted each time the chair enters the reset mode.
The input R3T that generates
゜ and flip 70 via NAND gate 1044
It functions to reset the knobs 1020-1023. There is also a flip-flop 1050 in the 9th section, and the initial
Configuration input fNIT (this is used when power to the system is turned on)
(occurs for 1 second after flip
Flop 1050 has input WRTONLY (computer
If the data controller wants to write data to one of its register addresses,
) and input STRBMY (MOVY register)
Strobe for loading data into the star. This is later
(described in ). These inputs
via inverter 1052 and NAND gate 1054
Sent. The Q output of flip 70 tube 1050 is output 5
It is TOREV. This will be explained later in relation to Figure 10M.
. 10M and 1ON are each of the logic section 62 of FIG.
FIG. 4 is a detailed diagram of the L10 and L10' sections. 110 o
and 110 sections perform various analog switching functions.
respond as if it were true. This is the scan mirror 14 (Figure 2)
can move in the X direction under computer or local control.
have them do this. Furthermore, the Llo and L10' parts are as follows.
Various summation functions and analog switching functions such as
respond in order to do so. (1) Adjust the scan 1114 (Fig. 2) by adjusting the adjustment knob P3 (
Operator controls 450 (located in Figure 9A) and computer
It is driven in the Y direction by the computer processor 34 (Fig. 2).
control. The latter is the MOVE Y register (described below).
). (2) In response to the correction signal coming from the 18th section (Figure 10)
In response, adjust the scan in the Y direction of #114 to create a cylindrical shape.
! ! The distortion of the laser point above 18 is corrected. (3) In the generation circuit in part 111 of the 111100 diagram
Therefore, a drive signal for scanning the mirror 14 in the Y direction is generated. As explained below, the latter is the drive signal for the X direction scan.
also occurs. In addition to the above, the signal feedback from the isthmus 14 (Fig. 2)
There are two buffer amplifiers for the purpose of
Computer processor 34 registers the X and Y position registers.
X and Y corresponding to data (described in detail below)
can read and display the location of Regarding Figure 10M, part 110 is part 111 (Figure 100).
) accepts the analog signal 81GOUT generated by
It will be done. This analog signal is transmitted to the laser 12/1114 (second
Figure) determines the shape of the scan to be performed. 110 more
The section is generated by the section 9 of Figure 10L explained earlier.
Accepts output X5INE. The latter is gate 1100 (electronic
(preferably a field effect transistor analog switch) is 8
10OUT to the negative input of summing amplifier 1102
form an input that allows Positive input of amplifier 1102
is grounded. As a result, summing amplifier 1102
A drive output signal XDRrVE is generated. The 110th section is the input MOVX (MOVXI,' register bit
(described below). Similarly, input M
OVX is connected to the summing amplifier 1102 via gate 1104.
Gated to negative input. Game) 1104 is input CM
PSINE (generated by section 9 of Figure 10L mentioned above)
made possible by Total amplification 111102
Appropriate biasing of the negative input of is provided by bias circuit 1106.
It is done. Input X5INE or CMPSI into 110 copies like this
5IGOtJT depending on which NE was accepted
(This pattern is generated by section 111 of Figure 100.
) or MOVX (computer-generated
pattern) is gated via summing amplifier 1102.
to form the chain actuation output XDRIVE. Output XDR
IVE is an analog input to the X driver card.
The driver card is supplied together with the scan tool 14 (Figure 2).
It is a normal hardware element. Furthermore, regarding copy 110, the system initialization (INI)
T) results in the generation of 5TOREV, the latter being amplifier 1
switch 1114 as an enable input via 112
sent to. As a result, bias circuit 1116 transmits
The bias voltage obtained is the negative input of the summation amplifier 611118.
gated via switch 1114 to Input YSCAN (located according to pattern 5IGOLJT)
switch 1 in response to commanding the desired Y-direction scan).
On the 10th, 5IGOLJT was applied to the negative input of amplifier 1118.
start. As a result, the layer width unit 1118 becomes YDRIVE (
Figure 2: The signal that operates the noscan mirror 14 in the Y direction is 5.
IGOUT (generated by part 111 of Figure 100)
pattern) or MOVY (computer-generated pattern)
(turn). YSCAN anti
The output is input as an enable input to switch 1122.
1120 and thus amplifier 111
Disable further inputs to the negative input of 8 (thus,
Parabolic correction when using YSCAN). in more detail
To explain, when the switch SW is in the upper position, the input
YFIX connects gate 1122 with resistor 1124 and
summing amplifier 1118 via potentiometer 1126
is sent to the negative input of , thus scanning 1114 in FIG.
produces a correction factor for the YDRIVE output that operates the YDRIVE output. 110 sections supply voltages -VSS and +vdd, respectively.
It has circuits 1130 and 1132, which are connected to the
It is used to send voltage to the power meter 504. potato
The adjustment meter 504 is located in the operator control section 450.
It is connected to knob P4 and the light is connected as explained before.
used to adjust the vertical position of the laser from source 12.
It will be done. As a result of adjustment of potentiometer 504, the center
The tap is another summation input to the negative input of amplifier 1118.
send. Thus, the Y-direction scan mirror operation output YDRI
Make the necessary adjustments to the VE to achieve the desired vertical positioning of the beam.
Make sure to do the following. Regarding the first ON diagram, the L10' part is basically one performance.
It consists of a computational amplifier (voltage follower) 1150, which
It comes from the mirror operation circuit in can all (Figure 2) 14.
Analog output after receiving feedback signal XBACK
amplify it properly to obtain posxt-. analog
As mentioned above, the output from the inverter stage 56 (
(Fig. 2), i.e., to its ADC part.
The digital input display for mirror position 1 is displayed on a computer programmer.
Send to Sesa 34. L10' section is feedback signal YB
ACK (Y direction feedback from scan rust 14
analog output PO
It should be understood that the circuit that generates 8Y is the same. Figure 100 shows details of section 111 in logic section 62 in Figure 2.
There is a diagram. Basically, the 111th part contains the scan pattern of the light beam.
There is a sine wave oscillator used in connection with creating a tone.
Ru. This ray is generated by light 112 inside the case.
manually operated switch 512 (operator control section 45
0 (Figure 9A)) is generated according to the sine wave pattern.
Prompts scanning drive of the light source 12. As shown below,
Frequency of the sine wave generated by the 11-part sine wave oscillator
The number is determined by the adjustment knob P3 in the operator control section 450.
various input signals corresponding to the operating speed generated by the
controlled by Furthermore, part 1.11 of Figure 100 is a manual operation
Various scan waveforms are displayed each time the operation switch 812 is selected.
It has the necessary circuitry to select from patterns. Regarding Figure 100, @@1200 is a conventional device.
(Intersll of Q in California)
IC18038 manufactured by 3T by uppertlno
preferable). It emits a sine wave at its output terminal 2.
Live, l1il! The ljn terminal of 1200 is supplied.
determined by adjustable sine wave timing circuit 1202.
It has characteristics that make it Furthermore, the device ll 200
square wave output (at its terminal 9) and its square wave output (at its terminal 3)
) has a sawtooth output. Regarding Figure 9C before
As explained above, switch 812 requires an operator.
Used to command specific output. Switch 812 is signal 5
QUAR. Generate TRINGL and S, INE as needed
. These inputs each have a 11°K12 or
and 13 (Figure 10L). 11 on the switch. selectively generate 12 or 13 on
As a result, the device 1200 produces a square wave, sawtooth or sine wave.
The output is sent to the negative input of isolation amplifier 1204.
and its positive input is grounded. As a result, amplifier 1204 produces an output 5IGOUT
do. Positive input of isolation amplifier 1204
Biasing is performed by bias circuit 1206.
. The device 1200 has a frequency IIJ111i1 on its terminal 8.
Input 08REF is attached. Input 08REF is partial pressure
resistor and voltage divider resistors 498 and 500 (see Figure 9C)
source to potentiometer 496 connected to. Faith
No. 08REF is sent to the operator control section 450 (Fig. 9A).
of the frequency term resulting from the actuation of a certain adjustment knob P3.
Remember that this is an input. This signal turns on
The pelleter adjusts the horizontal speed of the scanning plow 14. this
As a result, input 08REF is used as frequency control input I@12
This is done by giving it to 00. Finally, the reference voltage
The pressure inputs +VREF and -VREF are the
Supply pressure input terminals V ccJ5 and V ee' respectively.
sent for. The latter terminals also each have a supply voltage circuit 1
210 and 1212. Part 111 is connected to terminal 10 of device 1200.
There is an interlocking switch SN. Switch SN in the downward position
When you put it in, the normal frequency of operation of l1l11200 is brought about.
be done. However, if switch SN is placed in the upward position,
This results in a high frequency of operation of the device 1200, which causes the output
This is indicated by the signal TEST I going low. Figures 11A to 110 and 11G are Figures 12
Detailed logical diagram and interface of the CEOG system
3 is a circuit diagram of a base 30. FIG. Figure 11E, Figure 11F and
Figures 111 and 111 are from the CEOG system interface shown in Figure 2.
The order in which data is written in relation to operations on the face 30,
FIG. 4 is a timing diagram of the order in which data is read and the order in which data is interrupted. Regarding FIG. 11A, three three-state buffs F1230.
1232 and 1234 are provided. Both are responsive to input signal GATVEC. To explain in detail, when GATVEC goes low, each
The three-state buffer is energized and the processor 34 (see FIG.
) at a prewired address (e.g. the preferred
In a preferred embodiment, address 000°154) is a three-state buffer.
Output DA via 1230.1232 and 1234
so that it reaches TO-DAT15. The output of the latter is the first
18, which is explained in more detail below.
. Conversely, when GATVEC goes high, three-state buffer 1
230.1232 and 1234 are output terminals DATO-
Appears as an open circuit to DAT15. This result is 0AT
ODATI 5 (coming from processor 34 in Figure 2)
These data are sent to the arrangement shown in FIG. 3 state bag
1230.1232 and 1234 open circuit condition.
As a result, outputs DATI 0-DATl 5 are not active.
stomach. Three-state buffers F1230, 1232 and 1234 are
In the example, it is 5N74LS365@ (Texas
(Repurchased by Swiss Instruments). In Figure 11B, its internal arrangement is a bus transceiver.
Ba-stomach 1240-1243 and 3-state bat F124
4 and 1245. bus transceiver 124
0-1243 receives and responds to input DGATE. Specifically, when DGATE goes low, the data DAT
O-DAT 15 is connected to internal inverter 1246 (for purposes of illustration).
(appears only on device 1f1240) via terminal D
ALO-DAL15 (the latter terminal is a computer processor
34 (showing the common data bus to Figure 2), the data
DALO-DAL 15 is connected via inverter 1247.
and reaches the output terminal DALO-DAL15. Conversely, when DGATE goes high, data DATO-D
ATI 5 no longer passes through internal inverter 1246
, the data DALO-DAL 15 is again connected to the inverter 12.
47 to the output terminal DALO-DAL15. Output terminal DALO-DAL11 is 3-state buffer 124
4 and 1245. more details
To explain, when GATWRIT goes low, input D
ALO-DAL11 sends to output DTOO-DTOI 1
It can be described. The latter is the DA in the inverter stage 56 (FIG. 2).
Generates input to the C circuit. , conversely, GATWRIT
When high, the three-state buffers 11244 and 124
5 becomes an open circuit and cuts off the output DTOAO-DTOAI 1.
cut off To summarize the above explanation, when DGATE goes low,
Data DATO-DATI 5 is the computer bus (D
recorded on the computer via ALO-DALL 5)
It will be done. On the other hand, DGATE is bypass transceiver 12
40-1243.3 state buffers 1244 and 124
5. and via output terminals DTOAO-DTOAI 1.
The computer processor 34 (FIG. 2)
is sent to the DAC circuit in the pattern stage 56 (FIG. 2).
. In an embodiment, a computer-generated control
Data (details include DOUT, DIN, 5INC, WTB
T, IAK I, B57J5 and rN summer, T) are comp.
Another path transceiver without going through the computer bus
Device F (not visible in the diagram) (this is a bus transi- sion
server 1240-1243) and its output
The corresponding control data DOUT, DIN, 5INC as
,WTBT. Generates IAKI, 887 and INIT. these
The control data is used as described below. lastly
, bus transceivers 1240-1243 are shown in the embodiment.
Bus transceiver: Model number DM8838
(Reimbursed by National Semiconductor Company). Additionally, three state buffers y1244I3 and 1245. teeth
In the embodiment, the buffer device 5N74LS365 (
(manufactured by Texas Instruments). 11C, the interface 30 (see FIG.
) further includes buffer devices 1250-1253I3 and
It consists of a switch circuit 1254. In actual operation, the device 1250 has GATWRIT
In response to going low, data DAL8-DAL13
(This is the bus transformer in Figure 11B discussed immediately above.
outputs of server devices f1240 and f1241).
Send to power terminals DAUT8-DALIT13. After this
force is indirectly sent via the corresponding embuta path)
Transceiver device I 240
and 1241, especially the control word register (described below).
It is there to bus control bits 8-13 located in Conversely, when the input GATWRIT is high, the 3-state
1250 becomes an open circuit and no data passes through it.
. The 3-state buffer 1251 is GRPISTV (Group 1
strobe) goes low, the output DAT
10- DATl 5 is installed, thus DATl 0-
Set DATl.5 to low (zero) output state. GRPI
STB is the second largest data converter from analog to digital.
(coming from converter stage 56 in the figure) enters processor 34.
Be careful that it goes low whenever you try to
. Returning to Figure 6A, converter A/D 1-A/D
5 is data (DATO-DAT9) 1OL'y to tr
The 3-state buffer 1251 is the most important 6 pits for sending
Place the first zero in position ff (DATl 0-DATl 5).
Perform the necessary functions to insert the file. In Figure 11B
Go back and try to enter the data into computer 12.
Recall that DGATE goes low when
. Therefore, from the three-state buffer 1250-1252
The coming 0ATO-DATl5 is the device 1240-1243.
Pass through the computer bus (DALO-DALl 5)
given to. Furthermore, regarding FIG. 11C, the three-state buffer 1252
is 5 TROBI (1 status instrobe)
logic section 62 (second!!l and
10A-100))
Output AT lN9-DAT lNI4 DAT9-DA
Tell TI 4. The latter is equipped @1240 and 1241
(Figure 118) to the computer as previously explained.
data bus. When 5TROB 1 goes high
, a three-state buffer 1252 prevents data transfer. The latch circuit 1254 is connected to Scho ROBO (control register list).
data DALO-DAL4 (first
Computer bus and devices 1242 and 1 of FIG.
243 from the processor 34 of FIG.
Strobes the latch circuit 1254. 3 state battle
1253 is 5TROB1 (Status register strobe)
latched by device 1254 in response to going low.
Output the data DALO-DAL4 DATO-DAT
Send to 4. The latter are devices 1242 and 12 of FIG. 11B.
43 to the computer bus. 3 more states
The state buffer 1253 is the input DO8AMP (this is
"write" and "g" signals, which are used when performing a write operation.
5TROB
DO8AM to output DAT15 in response to I going low
Give P. When 5TROB1 goes high, the three-state bar
The buffer 1253 prevents that data transfer. FIG. 11D shows the readout at interface 30 of FIG.
3 shows the write/write decode and control circuit. Next, Thailand
This will be explained with reference to FIG. 11 and FIG. 11F.
do. For Figures 11D and 11E, Invar 912
70-1273 are each human-powered DAL from the circuit in Figure 11B.
12. DALIO, DAL9. DAL8 and DAL7
accept. NAND gate 1274 has input BS7. D
AL15. DAL14, DALl3 and inverter 1
270-1273 and decodes these inputs.
and input (address line input) D△7-10.
DALI 2-15 is located on processor 34 (Figure 2).
Logic part 1 output indicates a block of specified addresses.
You will begin to draw out your strength. In this particular case, the input DAL
7-DALIO and DALl2-DALl5 are addresses
Block 164.0XX or 164,1XX is shown. To explain in more detail, DALO-DALl 7 is the second
Address input coming from the processor 34 in the figure, various
When the DAL bits of have the values shown in Table 1 below, the corresponding
address block. Address 17 16 15 14 13164, O
XX O0111 164,1xx OO111 Address 12111098 164, Oxx O1000 164,1xx O1000 Address 7 6 5 ... 0164, O
xx OO・・・・・・・・・・・・・・・・・・
・・・164.1XX O1・・・・・・・・・
.........Table 1 When human power 887 is logic 1 (on) and NAND
Gate 1274 decodes the desired address block.
When the computer inputs its address DALO-D
Retrieve data at a desired address via AL17. death
Therefore, the output of NAND gate 1274 is
1278 and flip through AND gate 1280
Plow 70 whelks 1276. This is AND gate 128
Input WTBT to 0 goes high to command a write operation.
(i.e. send computer data).
Become. Manual 5 INC (one address synchronization pulse)
A is applied to the clock input of lip 70 tube 1276
The output of the ND gate 1280 is 7 rip 70 Tub 1276
If you make it strobe, RDYWRIT will
Become a good person. 5YNC is further connected to NAND via inverter 1282.
A gate 1284 is provided. NANO gate 1284
Another input is the decoding of NAND gate 1274.
Receive output. In this way, 5YNC is low
or the output of NAND gate 1274 is high.
(address blocks required for the computer to call)
), flip-flop
1276 is reset by NAND gate 1284.
I can't cut it. However, once 5YNC becomes high
or when NAND gate 1274 goes low,
Flip 70 knob 1276 is reset. The above description described achieving the "ready to write" state.
Flip-flop 1276 is a write-ready flip-flop.
specified by the read-ready flop)
The same basic operation applies to Lip 70 Tube 1286.
It is done. Input BS7 becomes 11 (on) and WTBT
goes low indicating a read operation, and NAND
gate 1274 (more desired address block is decoded)
When read read preparation knob 70 is inverted.
1288 and AND gate 1290. Flip 70 tube 1286 is the above-mentioned Noritsub 70 tube.
It is strobed like the 1276 (its C input
(via force) is also reset. (via its R input
hand). The stomach of FIG. 11D also includes a latch circuit 1292.
Ru. This is due to the computer generated from the distribution of Figure 118.
It receives addresses DAL1-DAL6 generated by centre
Either the rip-flop 1276 or 1286
When working, latch 1292 connects to NAND gate 1294.
More strobed. In the clock diagram of Figure 11E
Address data 8A generated by the computer
L (N), N-1-6 is computer bus DALq-
The desired address block is given through NAND gate 1274.
When decoded, WTBT (Fig. 11E) becomes
goes high, indicating a write operation, AND gate 1280
drives write ready flip 70 knob 1276
(This is 20 days after WTBT goes high)
(preferably within seconds). Once ready to write
When the flip 70 knob 1276 is energized, the NAND game
1294 goes high. This is AND gate 1280
Preferably within a maximum of 14 nanoseconds after becoming high. aforementioned
As mentioned above, the high output of NAND gate 1294 is
Latch the response data (coming from processor 34 in Figure 2)
Strobe to 1292. Returning to figure 111D, Noritsubu 70 horn 1276 is AN
Energized by D gate 1280 to output RDYWRY
When T is generated, the output of the latter is further output W'RT
ONLY<via amplifier 1295) and σAT
(via inverter 1296). Output R
DYWRIT is also sent to NAN[>Gate 1298
. Another input of NAND gate 1298 is the signal DO
Take UT. This signal is used by the computer to
A minimum of 25 nanoseconds after data output begins is preferred. No.
(Refer to the clock diagram in Figure 11E) When the output starts, it goes high.
. NAND gate 1298 connects inputs DO (JT and RD
For YWRI T, perform AND operation, NΔAND game.
The output of gate 1298 is NAND gate 1 which performs an OR operation.
Activate one-shot device f1302 via 3'OO
let The one-shot device f1302 is short (1 microphone
output a negative pulse (preferably 0 seconds) with a trailing edge that flickers.
Activate the push button 1304. The Q output of flip-flop 1304 is NAND gate 1
Enter 306. There is also a NAND gate 1298.
The inverted output is received via inverter 1308. NAND gate 1306 performs an AND operation in response to inputs to
to produce a negative pulse, whose previous rut is another one-shot rut.
Activate @1f1310. NAND gate 13
The output of 06 is called 5TROBWRITE. This out
The power becomes one of the inputs to NAND gate 1312, which
OR enzen will be held accordingly. NAND gate 13
The output of 12 is sent to the decoder 13 via the inverter 1314.
This is the strobe input to 16. The decoder 1316 latches 1292 when there is an /IO input.
Address human power △DDR4-△DDR6 is received from. La
DR1-ADDR3 to address output of switch 1292
Go to yet another decoder 1” 318 (.This decoder is
, strobed by the 07 output of decoder 1316.
(if D input is present). To summarize, ADDR4-ADDR6 human power and human power S-r
10 balls ``WlR-Ding''-King-NoM Ka,-F' Kota
1316 is a group of strobe signals, G RP OS
T B, GRP lower 3-cho 1. -01] Ding n OJ:
and nTB. Output GRPi 5jB-GRP3
The STB has corresponding decoders 192, 194, 196 (the
6C), where it is decoded and an appropriate stroke is sent.
converter stage 56 (first
2(4) DAC circuit (FIG. 6E). deco
The output from da 1316 is further decoded.
Proceed to step 1318. Also here is the latch from latch 1292.
Address inputs ADDR1-ADDR3 are provided. So
As a result of , decoder 1318 outputs S rROBO
(via amplifier 11320), output 5 TROBO (input
via converter 1322.1324 and NAND gate
"Control word cost strobe" and "output termination" that occur when
Generates a 111 go (status word strobe). In summary, the circuit of FIG.
Decode AI-DAL6 and various strobe signal groups
(GRPO8TB, GRPISTB, GRP2STB,
GRP3STB) and outputs the logic part 62 (see FIG. 10A).
(Fig. 100) and the converter stage 56 (Fig. 2 and Fig. 100).
Send to the DAC/AOC circuit in Figures 68 to 6E)
. These strobe signals are sent to the computer processor 3.
4 (Figure 2) is an appropriate address from an appropriate address in the storage device.
Searching for data and placing the appropriate data at the appropriate address
Compensates for writing data, various transfer and analog
to digital (or digital to analog)
Accurately time the conversion line section. As mentioned above, the leading edge of the NAND gate 1306 output
Oneshot 1310 was activated. After that,
The trailing edge of the output of the shot device 11310 is 7 lips.
73, 38 (t?foot'!j). Therefore,
The Q output of flip 70 tube 1338 is a negative pulse.
, NAND gate 1340 and inverter 1342
through which the output [rLY is brought low. The latter is combination 1
- Computer processor 34 (FIG. 2)
It was given to. NAND gate 1340
RP L Y 2 (Jl! 11 G l!21
@Stomach to computer by circuit i.e. CEOG
(generated during a system interrupt)
Perform the OR operation and flip 70 to 1338 -0
A negative pulse output of - occurs, but when W goes low, R, P
Make LY go low. Finally, once R (unknown) time has passed (i.e., the asynchronous
operation), explained in Figure 11B.
The input DO received via the computer busbar as
UT goes low (see timing diagram in Figure 11E);
Accordingly, the output of NANO gate 1300 also goes low.
Ru. This low signal is connected to NANO gate 1356 (OR gate).
) and inverter 1358.
Reset the top 70 knobs 1304 and 1338,
As a result, output RPLY is high (or RPLY is low,
). Please refer to the timing diagram of FIG. 11E. Shortly after, signal 5YNC also goes low and the write (data
The procedure (data out) ends. Furthermore, referring to the timing diagram of FIG. 11E,
Ideally, the timing should be as follows:
. The time interval TIA is a minimum of 75 nanoseconds, and the time interval
TIB is up to 66 ns (27 ns setup)
(including time). T2A is a minimum of 25 nanoseconds and T3A
is a maximum of 14 nanoseconds. D4A has a minimum of 25 nanoseconds. T5△ is
Minimum 190 nanoseconds. T, 5B is a minimum of 220 nanoseconds. T
6 is a maximum of 120 nanoseconds (typically 60 nanoseconds). The preferred time intervals described above are shown in FIGS. 11A to 110.
As explained above, the ideal CEOG system
It was obtained by the specific equipment mentioned in the configuration.
Ru. In the timing diagram of Figure 11F, the read operation
Data entry into the computer is performed as follows. The computer creates an address input DAL (N),
They go to latch 1292 in FIG. computer
The data processor 34 (Figure 2) further generates 5YNC.
, this is a flip 70 knob 128 as a strobe input.
To 6 (Ready RE A D flip 70 knob)
carried. If the D input is logic 1 at the leading edge of 5YNC,
Strobe (SYNC) is flip-flop 1286
set. While W T B, T is low indicating a read operation, A
ND gate 1290 is inverted when NAND gate 1274 is inverted.
Kamigyo address decoded in relation to data 1278
If a block is detected, in response (BS7 is a logic 1
．． As long as it is on, Noritsubu 70 Tsubu 128
6's D input gives logic 1. NAND gate 1344
is the input RDYREAD (flip-flop 1286
) and DrN (when the computer is ready to accept input).
), perform the ANDIII calculation,
5 TROBERE ll: Tall. DIN is RC (
delay) network (resistor 1346 and capacitor 1348
) to the NAND gate 1344, consisting of 5
Delay required for YNC and DIN leading edge darkness (60 nano
(preferably seconds). When IR-σdr■TT becomes low, decoder 13
16 (NAND gate 1312 and inverter 13
14) to strobe the output from latch 1292.
Decode inputs ADDR6-ADDR4. decoder
1316 and 1318 function as described above to
Herobe signal group C-RPO8TB, GRP1STB,・
...and generates 5rR080, 5TROBO, ...
do. -Tm "The signal generated by R-BREAD is
Only a specific group of data is connected to the data line DA-0.
-DA]-gate to -9. Even if G, rs T'R
OB 1 (11° Channel 1 in the Δ/D section in Figure 6A
Gate the data coming from. At the same time, data line D
A 1' 1O-DAT15 is seen in Figure 11C
J: Uni-CRPTK Shita-niyo-C zero. Furthermore, when 5RTOBEREAD goes low, one system
Shot 1302 is triggered. 1? After a few seconds, the
The trailing edge of the signal from shot 1302 is
1304. Flip flop 1304?
Their outputs are STR in gate 1350 (NANt)
AND performance with OB lgE A D, S
The belief that cents Flinofrotub 1338 through human power
make a number. Noritsub - Flop 1338 is set
C its Q output N AND gate 1340 and inverter 1
342, it responds to r, ■ r low.
Ru. In the meantime, the
and 1354 to generate DGATE. Invar
1354 is an A-bun collector device. i.e.
, its output is similar to that of other oven collections that generate TE.
can be connected to a computer device. As previously mentioned,
D G A T7 is the data DAT1~匡AT'go3
Bus ``M'' was used to put in drunkenness ■1] (
Figure 11B). When DIN goes low, 5TROBER
EAD also goes low (NAND gate 1344 and
(by the operation of the server 1352). Flip knob 1
The reset (R) terminal of 338 is a NAND gate 1300
and 1356 (the latter is ORed against input -r][T]-
calculation> and reset by inverter 1358.
will be cut. In this way, the flip 70 knob 1338 is reset.
and NAND gate 134o and inverter 134
RPLY goes high through operation 2. the result,〕
The monitor sets 5YNC low and reads this.
(Additional changes) The procedure ends. The timing in Figure 11F further describes the domestic time.
Then, in the ideal case, it would look like this: The time interval T1F is at most 54 nanoseconds (previous, therefore
The wrong code is stuck in f coater 1316 in Figure 11B.
60 nanoseconds is recommended for 12F (to prevent it from remaining for a long time).
Delicious. T3F is 80 nanoseconds. It is desirable that T4F is 1 microsecond.
The diagonal 1ilIrIJ spacing is shown in Figures 11A to 110.
This can be obtained with a solid circuit. The interface 30 and interrupt request procedure in FIG.
Logic block diagram/'circuit diagram in Figure 11G and Figure 11H
Further explanation based on the timing diagram (1sNDD)
AT is a flip-flop 1400 (data preparation flip
flop) and set it. On the other hand, input
DAL15 (most significant bit from the instruction register described below)
) is a flip-flop 1402 (on-interface)
enable flip-flop) and sends this
Flip-flops 1400 and 1240
The Q output of 2 is NAND gate 1404 (AND operation
), and the output from there is sent to the inverter 140
Norotsubu 140 as clock manual power through 6
Sent to set 8. Noritubu Norotsubu 14
Q output of 08 is output IRQ via inverter 1410.
(IRQ in the timing diagram of Figure 11H)
reference). The flip-flop 1402 is configured in the circuit of FIG.
Note that the 5 TROBO created by is clocked.
I want to be IRQ as an "interrupt computer" instruction
is communicated to processor 34. The circuit in Figure 1'IG is the circuit in Figure 1'IB @1240
= 1243 similar bus l-lance seam iut is bus
Input from the computer coming through I△ to 1
Receives input IAKIN which is generated in response. This J: U
In Figures 11G and 11G, IAKI
N and the output of inverter 1406 are both high.
and the output of NAND gate 1412 (GATVEC)
becomes low. Output GATVEC is inot<-')14
14 and the inverter via the Rcl extension network 1416.
It is sent to the data processor 1418, where it becomes the output lI*Y7. death
Therefore, RP↑■] is 0-L-D-■T℃ becomes low.
Then, it becomes low accordingly. Furthermore, 'G1-L
When ya draws 1 and - becomes low, D's ThL King - (invert)
Output of data 1420. The input to it is inverter 1414
N connected to also goes low. Finally, Noritzbufu
Lop 1408 is when Ding n goes low or KK Ding Ding is
Either goes low or <NAND gate 1409
and inverter 1411).
Set. Returning to Figure 11D, IAKrN (path transceiver equipment)
input from the computer via the Not shown. 11th
8) responds to RPLY2.
and goes low, the output σK of the NAND gate 1412
T■T goes high and as a result GATVEC goes low
(See Figure 11H). Therefore, the output DGATE
and RPLY2 also go low. IAKIN is also I
AK (zero) allows other equipment to be removed along the computer busbar.
It is also transmitted to the place. IAK (zero) is divided by CEOG Sysdem.
NA in response to IAKIN when no request is made
This is caused by the ND gate 1422. Resetting the circuit shown in Figure 11 [・ should be performed under the following three conditions.
It will be done. Manual switch 5WA (inside interface 30)
It is best to set the no-bounce switch 142.
4 and reset NAND gate 1426 (OR operation
) and the output RS J' via the inverter 1428
1 is generated. from inverter 1430 through NAND gate 1426
When IN1 becomes high. system turns on
The 1 second timer 1432 works and the output from it is sent to the inverter.
1434 to NAND gate 1426 and inverter
・-If it reaches 1428 pm. In a preferred embodiment, the input
BuJ RS A/D Amplifier 111427 and Wire
One input of NANO gate 1426 is connected via a gate OR connection.
Connect to power. In that case, RS 'T' A/D
In response to the rKT becoming low, I decided to make rKT low.
Become. In this way, within converter stage 56 (FIG. 2)
11G in response to the ΔDC circuit being reset.
circuit is reset. Thinking back to inverter 143o that receives input INIT
Then, the output of inverter 1430 is the input of amplifier 1436.
Connect to power. The output of 1436 is C
Issue MPINIT. The circuit in Figure 11G constitutes Noritub 70 and 1437.
, clocked by input 5 TROBO to input DAC
14 (the control work in the computer processor 34 of FIG.
Set by the 14th bit of the register (described later)
be done. Flip-flop 1437 is set as a result
The 151st bit of the status word register (described later)
Generates low output DO8MAP. Correspondingly,
The output CMPSMAr' of inverter 1438 goes high.
Ru. Finally, reset R from NO gate 1440 to N
"""Flip in response to 57rt or R8Tl 4
Flop 1437 is reset via inverter 1422.
is detected, its ID1)-[ goes high, and σMPSA
MP becomes low. Next, a description of the computer processor 34 shown in FIG. 2 will be given. The processor 34 is a computer program (software).
)361 display device j38. Hard copy printer 40. centre
Loppy disk 42 and (user controlled) keys
Recall that it works in conjunction with board 44. lowest
, a general-purpose digital computer having the above-mentioned elements/machines
Although any data may be used, the preferred form of this invention is
Then, the PDP II 103 is displayed as the processor 34.
38. /LJT-52 terminal V as the keyboard 44
ill, RXV-11 on floppy disk 42
computer program 36
R-11 software package (digital installation)
(available from Quitubment Corporation).
I'm there. Moreover, the times in Figures 11A to 11G
The path will add storage space to the computer. this
The increments are shown in Table 2 (below). The 1111m word register (described in Table 2) is
This is a 16-bit write-only register, starting from bit O.
Up to bit 15, it is organized as below. Bit 15: Interrupt enable bit. This bit is
Science Department 62 (Figures 108 to 100) or Compilation
Each time the computer processor 34 sets a delivery date for the system,
Be bitted. Other than that, computer programs
(Software) Set/reset by 36
. In the ring system, this bit is Noritub 7 in Figure 11G.
Generated by 0 knob 1402. Bit 14: To DC in converter stage 56 (Figure 2)
"Single Step" bit sent. In this system, this pin 1~ is flip-flop 14
37 and the signal CMSAMP (Fig. 11G
(via data pin 1-DAL 14)
Ru. This signal is used during the analog-to-digital conversion process (
SAMPLE used in Figure 6A) (see Figure 6D)
) is one of the signals that generates. Bit 13: GO bit. (at input DOUT13) 1st
It is sent to Soga in the OJ diagram and generates a signal 5MSSAMP,
111 every 5 milliseconds! l sample points (6 channels
) commands the generation of data at a rate of As previously mentioned,
DO'UT13 uses node to generate 5MSSAMP.
Operate rib 70 tube 970 and one shot h 978.
let Table 2 EOG input/'output address register
Register 164,000 Write-only information word
Register 164.002 Read only data input
Data Channel 1 164,020 Data Channel 12
22 data C ((2 324 data CH3 42G data CH4 530 data CF-15 632 data CH6 734 chair speed 8 36 stripe cage speed data out 164,040 write only
Ch i -8-164,056 1yl ove X 164,060
Write only positlon ×164,062
Only $% out pJj ova “y”
164,070 Write only Posltlon
Y 164,072 Read only 411
Child all m 164,004 writing
Only interrupt position 000,154 data
000.160 Zero adjustment bit 12: Input DOUTI 2 (CMPSHTR>
A flash bit is issued as shown in Figure 10L.
Output stone sent to P70 Tsubu 1022-1-I U T
is generated, resulting in pulsing of the flasher 70. Bit 11: 2.5 ms sample bit is input DO
7 lip-flop 972 in the 1st OJ diagram as UT11
Sent. The flip 70 knob 972 is reset by the output π.
Press relay (solenoid/switch) 982 to
Adjust the timing of cut 980. As a result, the sump
Ring time is reduced from 5ms to 2.5ms
. Bit 10: Bit DOUT10 is the flip signal in Figure 101.
70 is sent to the knob 1020 and set. the
Result flip 70 tube output (via self output)
Generates RECORDING. RECORDING
When becomes low, the display indicators in Figures 9A and 9B
The data DSQ becomes bright and the system enters the “recording” state.
Show that something is true. Bit 9: Copy bit. Hard copy mark 11 in Figure 2
1140 to print the test results. Bits 8-0: Bits 5-8 are spare bits, C
Other than the above, deemed necessary for the EOG system
Usually used for a functional or presentational purpose. Bit O-
4 is 5TROBO in the latch circuit 1254 of FIG. 11C.
is written and stored. Therefore, the computer
When rffσW becomes available, the processor 34
Read back the bits of via the 3-state buffer p1253
be able to. Therefore, users of CEOG
- Timing and interface of interface 30 (Figure 2)
of data passing through the computer bus via the bus
This will give you the convenience of checking for errors. situation word dress
The register consists of 16 read-only bits, which are
It is organized as below. Bit 15: Write and G bit, computer
writes to any register (except for control registers)
must be checked before viewing. if bit
15 is on, the CEOG system will
” during the instruction, the computer processor 34 (FIG. 2) transfers
Indicates that the word is being memorized. With this system
The bit 15 is the knob 70 knob 1437 in Figure 11G.
is generated by Output W of flip 70 tube 1437
Dear MW mouth, please refer to the 3-state buffer 1253 in Figure 11C.
Note that the computer input DAT15 via
I want to be. Bit 14 varnish drive on bit. visual exercise equipment w1
16 is moving.
and This bit is the switch 5 turned on by the user.
11 (Figures 9A and 9c), 10th
NAND gate 912 in the fourth part of figure H. inverter
918. Computer via NAND goo 1-924
Provided as input DATIN 14 to processor 34. Bit 13 is the varnish drive write bit;
The direction of rotation of the box 76 that gives stimulation (bit 13 if right)
-1. If it is on the left, it indicates bits 13-0). Bit 12: Copy in use bit. hard copy pudding
40 (Figure 1 indicates that the previous command is being printed)
vinegar. Bits 11-0: Reserved bits, but normal bits other than the above
It can be used for functions/presentation. The data-in registers are located at the input/output addresses specified in Table 2.
These correspond to information channels 1-8.
. As explained in the ADC circuit (Figure 6A),
Digital channel 1 (to analog input AMPOUTI)
Respond> is left vertical eye movement test data, channel 2 is
Right vertical eye movement test data, channel 3 is left horizontal eye movement test data
motion test data, channel 4 is right horizontal eye movement test data
, channels 5 and 6 are VER test data, channel 7
(Compatible with analog human power TACH2) is chair speed data,
Channel 8 (compatible with analog human power 5 TRIPESPD)
contains velocity test data for a striped stimulus box. Data Out Channels 1-8 (see Table 2 above) are
The computer program of FIG.
Contains digital data from sensor 34. in particular,
Data out channels 1-4 are zero adjustment signal ZRADJ
LJ-1, 2,... 6) for producing an analog signal B rAsN(N-
1, 2, ... 6) (see Figure 6E)
This is the total data. For channels 5-8, this
Since it is not essential for clarity, I will omit the explanation and just
This means that it can be used to provide various analog functions.
Let me just say that. The MOve X register (Table 2) is a 16-bit write-only register.
and is organized in this system as follows:
. Bit 10: GOXl1i1. M14 (and attached to it)
Draw a sine wave specific to the associated drive circuit) and scan in the X direction.
command to start scanning. 7th lip 7 of figure 10
See input DOUT10 to 0tube 1020. As a result
and generates X5INE. Bit 11: CMPS INE bit. @14,
A computer processor 34 controls the X deflection of mirror 14.
The lowest 10 of the MOV
bits control the operation of the X-deflection mirror. No.
101 - Input DOU to 7 lip 70 knob 1021 in figure
T11 (CMPSINE> and the resultant inverter 10
See CMPSINE generated by .34. Bit 1
2: CMPSHTR bit. Shutter 66 (Figure 2)
Open it to let the light from the laser 12 pass through. Usually bit 10
Or used with 11 or more. 7L in Figure 10L
Input to knob 70 knob 1022 DOLJTI 2 (C
MPSHTR). As a result, NPNt
- transistor 1036 produces r; Bit 13: On YSCANSC. Scan Y deflection mirror
turn on. Similar to bit 10, but scan in the Y direction
control. Input Y to amplifier 1110 of FIG. 10M
See SCAN. As a result, the output YDR that drives the mirror
IVE occurs. Bits 10-13 are on at the same time in this system
and scan the scissors in the direction of 45 degrees (one mirror tilted).
Please note that you can do this (along the diagonal line). Bit O-9: These 10 bits are interface 3
converter stage 56 (first
Figure 2). Specifically, in this system bit 0
-9 is the input DTOAO-DT○A9 in Figure 16E.
It is fed into a circuit of the type illustrated as a DAC circuit. Data is strobe input 8 ROBMX (STROB
(similar to N), the latch circuits 302 and 303
Troped. There, digital data is analog
analog output MOVX (B in Figure 6E)
(similar to IASN) and the X of 1114 (Figure 2)
An analog voltage (preferably -5 volts) that defines the movement of the canopy.
(000...000> to +5 volts (111...
・The value of 111) is produced. The position IFx register (Table 2) is read-only and
A compilation of 1112 diagrams containing information about the positions of chain 14.
Feedback is sent to the computer processor 34. This Regis
The lowest 10 bits of the data are the relative positions of each other.
represents. However, in this system the GO bit or
If any of the single step bits are on and the
If it is not the interrupt that was entered, the bottom of the X position register.
The first 10 bits cannot accept the latest data.
do not have. (This is true for A/D converter 56' in FIG. 6A.
This applies to any output. ) Y motion register is
It is write-only and controls scanning in the Y direction of 1114.
used to control The least significant bits (0-9) of this register are the
explained bits 0-10 to control the
Similarly, it is converted into D/A to form MOVY. child
This is an analog voltage and is connected to the Y position potentiometer (system
control by the system user) and working together (Figure 98 or
(see Figure 9E), move the Y deflection mirror. Circuit of Figure 9C
See potentiometer 504 within 502. The Y position register is read-only; the lowest
Ten bits signal the relative position of the isthmus 14. X position
As in the register, the lowest Y position register
10I! GO bits have the latest data.
bit or single step bit is on and
Also, an interrupt must be received. In connection with the above explanation, the address deco of the CEOG system
The list of codes is shown in Table 3. (Left below) What you should be careful about with this system is that the memory location is 11164.
000 to 167.176 are processor 34 (second
(Figure) is not the true storage location. rank @1
64,000-164.016 is the control word register
, status word register. There are chair control registers and the specification of these positions is decoded.
NAND gate 1274. Decoder 13 in Figure 11D
16.1318 etc. (send the above data to an appropriate address)
S King ROBOO to send. 5TRO81 etc.). Similarly, place 1f164.020-164.036 is CE
Data input from the OG system to the processor 34 (after input)
(previously converted from analog to digital) channels 1-8r
be. [164,040-164,056 is 70t]
34 Data Output Channel 1- to cEoG System
8 (converted from digital to analog after output). Last d, position [164,060-164,076 is X motion
register, X position register, Y movement register, Y position register
It's jista. In this way, in the system of the present invention, from FIG.
Much of the circuit shown in Figure 11G is at location 164.000-
164.076 or perform that function.
I can say it. That is, bit 1 of address 164.000
When “1” is entered in 2, the flasher 70 (Fig. 2) turns off the flasher.
generates a flash and then resets. Table 3f) Bit D6-DOLt, place ff164.000
-164,076 to specify any one address.
and represents the seven least significant bits of that address. In this system, every other place @ (for example, 164
．． 002; 164.002, etc.)
, when decoding bit D6-Do in octal system, bit
O doesn't need to think about it. That is, bit D6-DI is
The busbar transformer of Figure 11B is connected by the computer busbar.
Data sent to server@121240-1243 (described above)
Data address line input [-r-T address]
Compatible with line human power DAL6-DALI. Also, Sara
to decoders 1316 and 1318 in FIG. 11B.
It also corresponds to inputs ADDR6-ADDR1. octal de
The result of the coding (done within the decoder of the description)
, various strobe signal groups, GRDO8TB, GRPI
STB, GRP2STB, GRP3STB (see Table 3)
), specifically S1'ROBO-8TRO, B7°5T
ROB10-3TROBI 7.5TROB20-S
T ROB 27, S T ROB 30-S
'T' R0B37 can be done. As mentioned above, the CEOG system in Figure 2
34, which is executed by a computer program 36.
Preferably software controlled. Also mentioned above
, the computer program 36 includes the RT-11 software.
Software package (digital equipment package)
-Brose PDP used here by poration
11-03) is recommended. Figures 12A and 12B are the CEOG system of Figure 2.
The system processor 34 executes the program as a computer program 36.
That of the actual inspection program and analysis program
This is a general flowchart for each. Compilation of Figure 2
The computer program 36 performs various tests on the patient.
Analyze the execution program (Figure 12A) and the test results.
/process and display or display it in a format convenient for inspection operators.
is divided into an analysis program for printing (Figure 12B) and
I get kicked. Before explaining FIGS. 12A and 128,
To explain some points, this CEOG system
Specifically, there are three processes: inspection, analysis, and censorship.
The RLINTEST provides a stimulus to the patient and evaluates the patient's response.
Invoke the inspection process to record. RUNANAL
YS Is analyzes the patient's response and records it in the patient record.
Invoke the analysis process. RUNREVIEW is a patient record.
inspection of patient records, display of the list of patients examined,
Invoke a review process to create a copy, etc.
. obvious to those with ordinary technical knowledge in this field.
Programming of the processor 34 is done by the user (telephone).
the operator) on the keyboard 44 (Fig. 2).
by letters of the alphabet (for example, 王, △, R)
Choose one of the three processes (inspection 9 analysis, censorship)
It is desirable that the In Figure 12, it is assumed that the inspection process has already been selected.
The verification process will then load the system and data disks.
and “boot” the system (first
2A block 1500). This way
to combine data (such as today's date).
Put it in 7 file record (150'l block) from 1 to ri.
Ru. The inspection process starts the system (e.g.
Type RUNSYS on the keyboard 44 in Figure 2. 1502
It officially begins by blocking). Next, the patient's
The block where the data format appears on the display 38 (FIG. 2)
1503). The test operator should not have any invasive information about the patient.
information (name, ID, etc.) using the keyboard 44.
Fill out the data form (1504 block). After entering the patient's f-date, the system will check the following:
The examination form is presented (1505 block). P-Follow-up test C-Chair movement test ■-Visual evoked response R-To the CEOG system*m Follow-up test selected I (1507 block), Follow-up test
The table is displayed as follows. C-CalibrationF-Fixed TargetJ-Jump TargetM-Move TargetR-Rotate PatternS-Assuming you select the Calibration procedure (block 1510) which recalls the test format menu,
The operator first starts the calibration structure. Such a calibration procedure
is executed by the processor 34 via the computer program 36.
Responds to specific calibration commands dictated by programming.
For example, in a preferred embodiment,
Such a calibration procedure is as follows. (1) Perform automatic door opening adjustment. When finished, tie C
Click. (2) Calibration continues... Perform horizontal 15° left calibration.
Uh...When you're done, type C. (3) Calibration continues...Perform auto zero adjustment
. When finished, type C. (4) Calibration is complete... Perform horizontal 15° right calibration.
cormorant. Turn around and type C. (5) Continue calibration. ...Perform autoze-O. When finished, type all Ct. (6) Calibration continues...Perform vertical 86 rise calibration.
cormorant. Type C when finished. (7) Calibration continues. Perform auto zero. Type C when finished. (8) Calibration continues. ...Perform vertical 86 descent calibration
Now. Type C when finished. (9) Calibration is complete...the computer will display the menu
Return to tracking. Operator Fixed Target Inspection (Block 15
11). Fixed target inspection is a process
under the control of the sensor 34 and the combination 1-tablogram 36.
It is done. In the example, fixed target inspection is
The command to perform is as follows. E-Recall execution menu. Record test results. Press spacebar to start
Press again to stop. T-time scale...5.7.5.10,12゜5
．． 15.17.5 or 20 seconds...other
In this case, the time scale is 2.5 seconds. △-Auto zero; Press C when finished. Open eye 0. Press the carriage return button to stop. C- Close your eyes. Press carriage return and stop. Operator performs target jump inspection (block 151)
Assuming that you choose 2), the preferred procedure is as follows.
I'm going to growl. E-Recall Tracking Menu Press Spacebar to record, press again to stop
Ru. T-time), 'y-ru: 5.7.5, 10.12°
5.15.17.5 or 20 seconds. otherwise Thailand
The time scale is 2.5 seconds. A-Auto zero; press C when finished. 1-Horizontal; Press the carriage return to stop. ■-Vertical: Press the carriage return to stop. FH = 50 spots Horizontal FV = 50 spots Vertical Operator inspects target movement (block 1513)
It is assumed that you choose . The preferred testing procedure is as follows
Become. E-Recall Execution Menu To record press Spacebar to start and press again
Press and stop. L-time scale: 5, 7.5.10.12°5.1
5, 17.5 or 20 seconds. In other cases,
To select the time scale 2.5 seconds period, operate the potentiometer adjustment knob.
(Horizontal speed adjustment knob P3 in Figure 9A). To select a test, press carriage return and stop. A-Auto zero. Press C when finished. Select HT-Horizontal, Triangular H8-Horizontal, Sine VT-Vertical, Triangular VS-Vertical, Sine Pattern Rotation Test (Block 1514)
Assuming that, the preferred procedure would be as follows. E-Recall execution menu. To record, press Spacebar to start and then press again.
Press and stop. ■-Time scale +5.7.5,10,12°5.1
5.17.5 or 20 seconds. In other cases, the time schedule
rule 2.5 seconds. Lower the rotary cylinder (operator lll1 [1 part 4 in Fig. 9Δ)
50). Potentiometer adjustment knob to select rotation speed
(P2 in Figure 9A) is activated. P-Perform rotational pattern inspection. carriage to stop
Press return. Rotate the TP-pattern inspection drum three times. Operator selects chair motion test (block 1508)
If so, the chair rotation (block 1515) or
can select either vibration (1516). good
The recommended steps are as follows. C-Calibrate R-Rotate the chair to the right or left C- Vibrate the chair for 4 cycles. F-Rotate the chair with a fixed lamp. To rotate the chair to recall the S-examination type menu (block 1515):
Procedure is preferred. E-Recall chair exercise menu. To record, press Spacebar to start and then press again.
Press and stop. 1゛-Time scale: 5, 7.5, 10.12゜5.
15.17.5 or 20 seconds. otherwise time
The scale is 2.5 seconds. Rotation speed selection knob (potentiometer adjustment in Figure 9A)
Set knob P1). To determine the number of rotations, type N and then select from 1 to 14.
Type one of the numbers. A-Auto zero. Press C when finished. R-Rotate the chair to the right. At the end, take horizontal data. L-Rotate the chair to the left. Take horizontal data at the end. RHV = Rotate the chair to the right. Take horizontal and vertical data
Ru. LHV-Rotate the chair to the left. Finally the horizontal and vertical data
Take the tag. For chair rotation tests, data is collected during the chair rotation and again after the chair is stopped.
Please note that it is possible to Assuming vibration (block 1516) is selected, the chair
The child is automatically vibrated for 4 cycles. And data is a chair
II of the child's vibration will be taken. The preferred procedure is as follows. E-Recall chair vibration menu. To record, press the spacebar to start,
Press again to stop. 1'-time scale; 5.7.5,10,12°5.
Take the order of 15.17.5 or 20 seconds. In other cases
The time scale is 2.5 seconds. Set the rotation speed selection knob to the "oscillate" position. A-Auto zero. Press C when finished. ■--Perform inspection. As described above, the period of rotational inspection (block 1515)
Inside, the operator can command rotation with fixed lamps
. Data is obtained during chair rotation. The preferred procedure is the same as described immediately above for chair vibration.
same, but one exception is the rotation speed selection for the “vibration” position.
Change the setting of the knob as follows. Position the fixed lamp (89 and S10 in Figure 9A)
via) then lights up. Set the rotation speed selection knob to the "fixed lamp" position.
. Select Verification Reaction Test (VER) (block 1509).
Assuming that, the preferred procedure is as follows. The blinking text (above display 38 in Figure 2) indicates the next test.
is performed in normal V[ER order. B8- Both eyes open. 128 flashes, 1 every second
Fratshyu. All 84 cars open. 64 flashes, 1 flash every second
Tsushiyu. R4- Close right eye. 64 flashes, 1 flash every second
Lashyu L4 - Close left eye c64 flash, 17 per second
Ratsushiko T (f, r) - f number (f is 16.32.64 or 12
8) for r seconds (r is 1'2, 1.
Or 2)\/Perform an ER test. M(m) - Select the magnification range on the display. REC - Record display S - Recall the test type menu. To summarize the above, in either case, the operator chooses
A specific test or single test is performed by the processor 34 in FIG.
/ Automatically administered to the patient under the control of the software 36
Please note that In detail, traditional manual or semi-automatic methods are
The operator will follow the steps scheduled for each test.
(as explained in the inconvenient manual)
In contrast to having to operate various inspection devices,
In the system of this invention, it is difficult to carry out the original automatic inspection.
The explanations listed above are shown on the display 38 (Figure 2).
are displayed in order. Provide initial information to the operator
This information is also keyed by the operator.
It can be obtained using the board 44. In addition, the operator
The parameter (potentiometer)
Set the meter adjustment knob P1 to command the rotation speed of the chair.
), such information shall be
The integrated operator control 450 illustrated in FIG. 9A
can be obtained quickly and effectively by using
Ru. This automatic inspection using the integrated CEOG system
Follow-up tests, chair vibration tests, visual evoked responses
(VER) tests (these tests have traditionally
relatively inefficient) but quickly and effectively
be able to. Needless to say, this result shows that many patients
Treatment using this invention of this integrated CEOG system
It is possible. Furthermore, this integrated CEOG system
Mu's invention is extremely flexible and has already been described in detail.
As explained, the operator always performs the operations in Figure 9A.
to operate various controls in the controller control section 450.
Therefore, specific inspections can be carried out manually. Finally, any form of operation, whether automatic or
Even if the test is manual, the test results can be immediately sent to the test operator or
is provided in a video format that is easy for doctors to use (Figure 1)
(as shown in the display 38). Useful for test operators or accompanying physicians
By providing instant display of test results, operators
The data or physician may: (1) Inspection
It can be immediately determined whether the inspection was carried out correctly. (
2) The patient effectively receives and responds to the stimulation of the test given.
Decide what you did. (3) In this way, other tests (
or repeat testing) is required. Regarding Figure 1'2B, 7 software 36 in Figure 1
The analysis program will be explained below. Starting an analysis program
(See START block 1540)
Take the following steps: Reading heading information from disk 42 (Fig. 1)...
Block 1550゜Heading information is displayed...Block
1551゜The message "Is this the correct disc?" is printed.
out (block 1552). The operator will choose Y (meaning yes) or N (meaning no).
(block 1553). If no, the system will get the correct disk.
(block 1554). and return to block 1550
Ru. If yes, the system will prompt you to enter the record number.
Print Message of Message (Block 1555)
). Operator enters record number rNJ (block-1
556). N is compared to zero (block 1557) and if N
If equal to or greater than zero, N number
A record is obtained from the disk (block 1559). other
If the direction N is less than zero, further decisions are made (
Block 1558). In detail, if -1 is equal to or less than N
5TART (block 1550).
), and if -1 is greater than N, the system stops.
Stop. Once the N number record is obtained from the disc (
block 1559), the system displays form information (block 1559), and the system displays form information (block 1559)
560). whether a visual evoked response test (VER) was performed;
A decision is made (block 1561). If VER (block 1562), the system
The two channels bell and scaling (block 1563)
Display the normal hand of "Print" (this is
(explained below). If it is not VER, the data is the result of memory measurement.
Labels and schedules are normalized (block 1564) using
The four channels of the channel are then displayed (block 15).
65). If the test is a follow-up test, scan isthmus 11 (
H or V) is displayed. On the other hand chair rotation is called
And chair motor 71! degree is displayed (block 156
6) Printing procedures are entered. In the printing procedure, the following procedure is applied. Group size is printed (block 1567)
. The operator then sets N-1, 2, 3 as the group size.
(block 1558). At this point, if the test is a VER test (explained above)
), the printing procedure will be entered. The system will send the message “Positioning points and their arrangement”
(block 1569). System displays cursor (1570) operator
Enter one of the following three alphabets: S, E or
or F (block 1571). If S is entered, Zaki (previously entered) will be
omitted (block 1572), then group size
A determination is made regarding (block 1573). If the group size is 1, the system will send a message
Print "Enter E level" (block 157
4). Operator writes one character (block 1
575). The system displays the filled-in label (block
Lock 1576). The system then returns to the cursor display (block 15
70) If group size is 2 or 3 (block
1573), the determination of whether the group is completed and 0 or not is
(block 1577). If a group is completed, the next group will start.
(block 1573). Then select Show cursor.
A return is made to ” (block 1570). If the operator enters [(block 1571)
, the channel information is omitted. And the next Jisenel
(block 1580), the channel is 4.
Determine whether less but equal or greater (block
1581) is performed next. If the number of channels is equal to or less than 4,
``Show sol'' is restored. On the other hand, when the channel is greater than 4, the system
Calculates by computer and displays time and speed
(Block 1582). And rSAVE? J's message
(Block 1583) The operator then enters Y (yes) or N (no).
S'Luku Glock +584). If [No-1, the system will display [Show cursor]
” and return to “Block 1570J, if the other is yes,
The system writes this record to disk (block 1
585), then return to Show Cursor (Block
(1570). 12th AFI! U's inspection program and Fig. 128
The analysis program includes various computer programs 36
(Fig. 1). Preferably one ma
control program and individual EOG and VER inspections
There is a test program for each analysis and
There is a program. To explain in more detail, the computer program shown in Figure 1
Step 36 is performed as follows in the example embodiment. 11I mask control and stored format
call the format of the program display (for
1 program 1 EOG test program 1 VER test program 1 main analysis program (for EOG test analysis)
) One main analysis program (for VER test analysis)
1 display program.Many modifications and improvements have been made to the system of this invention in this field.
Obviously possible for experts. Therefore, this issue
such modifications and improvements as are within the true spirit and scope of Ming.
What is intended by the following claims to cover
It is.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the appearance of the CE OG system of the present invention. ff12FzJ is a more detailed block diagram of the CFOG system of the present invention. FIG. 3A is a schematic diagram of the approximately one amplifier network 24 of the CEOG system of FIG. FIG. 3B shows the image quality amplifier AI, Δ2. ...This is a detailed diagram of 86 □. Figure W44A is a diagrammatic representation of the amplifier network 26 of the CE OG system of Figure 2. FIG. 4B shows amplifier A11 of amplifier network 26 of FIG. 4A.
．． A12. ... is a detailed diagram of A16. FIG. 5 shows the amplifier circuitry 26 of the CEOG system of FIG.
FIG. 4 is a schematic diagram of a bias circuit 46' included in FIG. Figure 6A shows converter stage 5 of the CEOG system of Figure 2.
FIG. 6 is an illustration of the ADC section 56' of No. FIG. 6B is a detailed diagram of one half of the converter A/'DI of FIG. 6A. Figure 6C shows converter stage 5 of the CEOG system in Figure 2.
In 6? 19 is an illustrative diagram of a logic circuit 190 with tres deco=1; FIG. Figure 6D shows converter stage 5 of the CEOG system of Figure 2.
6 is a detailed schematic diagram of still other ADC logic circuits 200 and 250 of No. 6; FIG. Figure 6E shows the parter stage 5 of the CEOG system in Figure 2.
FIG. 6 is a detailed view of the DAC section 300 of FIG. FIG. 7A is an illustrative diagram C of the Tanabata control device 52 of the CEOG system of FIG. FIG. 7B is a detailed diagram of the failsafe circuit 326 of FIG. 7A. FIG. 7C is a detailed diagram of the chair interlock circuit 328 of FIG. 7A. Figure 7D shows the dynamic brake relay 32 of Figure 7A.
FIG. 2 is a detailed diagram of No. 2. Figure 8 shows the relay panel 20 of the CEOG system in Figure 2.
This is an illustrative diagram. FIG. 9A shows the control panel 54 of the CEOG system of FIG.
FIG. 4 is an illustrative view of the operator control portion 450 of FIG. FIGS. 108-100 are detailed logic block diagrams and circuit diagrams of the logic section 62 of the CEOG system of FIG. 11A-11D and 11G are detailed logic block diagrams and circuit diagrams of interface 30 of the CEOG system of FIG. Figures 1lP111E, 11F and 11H are timing diagrams associated with write (data out, data in) and interrupt operations, respectively, performed at interface 30 of the CEOG system of FIG. Figures 12A and 12B respectively represent C of Figure 2.
3 shows a general flowchart of the inspection and analysis programs implemented by the processor 34 of the EOG system. In the figure, 24 is a forestomach amplifier bone network, 26 is an amplifier circuit network, 46' is a bias circuit, 56 is a converter stage, 56'
is the ADC part, 190 is the address decode logic circuit, 2
00 and 250 are ADC logic circuits, 52 is motor control i
1 device, 326 is a fail-safe circuit, 328 is a chair interlock circuit, 322 is a dynamic brake relay, 20 is a relay panel, 30 is an interface, and 34 is a processor. Patent applicant Ropart Steven Redli, - (1 other person) Drawing 'tT+ (no change in content) F death, X //, 7/3 Fact7C. r/Cr, 70. 4nA Tsubasa 11FA last f/tani 97
ρ fO (104 ρ5. m〆 sword r/G, 10G. 45σ r/to, nf fσ10f. -1 Rime 77 and 5-ノ/f 1/Gy24 1 [sentence -1 procedural amendment - (method) 1 , Indication of the case Patent Registration No. 37881 of 19822, Title of the invention Computerized electric eye position description system 3, Person making the amendment Relationship to the case Patent applicant address Silver, Maryland, United States of America
Spring Ragland Road, 1002 Name: Ropert Steven Ledley (and one other person) 4, Agent address: 6 Yachiyo Daiichi Building, 2-3-9 Tenjinbashi, Kita-ku, Osaka City Drawings subject to amendment: 7, Amendment As shown in the attached drawing, the drawings were drawn with content arrogance. Amendment to the above procedure - 1. Indication of the case Patent Application No. 37881 filed in 1988 2. Name of the invention Computerized electric eye position description system 3. Person making the amendment Relationship with the case Patent applicant address Maryland, United States of America state, silver
Spring Ragland Road, 1002 Name Lopert Steven Ledley (and 1 other person) 4 Agent address 2-319 Tenjinbashi, Kita-ku, Osaka Yachiyo Daiichi Pill voluntary amendment 6 Full text of specification subject to amendment 7 The full text of the detailed statement of amendments will be amended as shown in the attached sheet. Description 1. Title of the Invention Computerized Electrical Eye Position Delineation System 2. Claims (1) An integrated medical examination system for automated management of test stimuli to a patient, comprising: operator control means for providing a processor input signal corresponding to the selection in response to an operator selection of a desired stimulus to be applied to the patient; and in response to the processor input signal from the operator control means. , processor means for generating a control signal representative of the desired stimulation to be applied; and stimulation control means for automatically administering the stimulation to the patient in response to the control signal from the processor means. The system further includes a rotatable chair, and the stimulation control means is responsive to the control signal from the processor means to rotate the rotatable chair to administer the stimulation to the patient. the IIJll signal includes a rotation signal commanding rotation of the rotatable chair for any number of rotations, and the motor control device is responsive to the signal. an inspection system that rotates the rotatable chair by the arbitrary number of rotations and stops the rotation of the rotatable chair. (2) The trunk 11ai includes a stop signal commanding the stop of the rotation of the rotatable chair, and the motor control
The device responds to the stop signal 7 to stop the rotation of the rotatable chair, ¥IIrFI! The inspection system described in item 1 of the scope of demand. (3) the motor control II device rotates the chair in a first direction, and the control signal includes an automatic reversal signal commanding an automatic reversal of the direction of rotation of the rotatable chair after a number of rotations; the motor control signal is responsive to the automatic reversal signal to stop the rotation of the number of rotating bales and the rotatable chair, and for the number of rotations to be opposite to the first direction. 6. The inspection system of claim 1, wherein the rotatable chair is rotated in a second direction. 4. The test of claim 111, wherein said motor controller issues a status signal, said status signal being transmitted to said processor means, thereby informing said processor means of said status of said rotatable chair. system. (5) The status signal includes a rotation completion signal indicating completion of rotation of the rotatable chair.
Inspection system described. (6) the rotatable chair has a desired initial position;
5. The system of claim 4, wherein the status signal includes a position indicating signal that alternately indicates non-movement or movement of the rotatable chair from the desired initial position. (7) the operator control means provides a speed control signal indicative of the desired speed of rotation of the rotatable chair in response to an operator selecting a desired speed of rotation of the rotatable chair; The means is the speed 111i
a motor w4II1 for controlling and rotating the rotatable chair at the desired rotational speed in response to a signal No. 11;
8M. The system of claim 1, comprising: 8M. (8) Further comprising scanning light source means for generating scanning light, wherein the stimulation control means is characterized in that the scanning light source means generates the scanning light in response to the control signal from the processor means. A soft inspection system according to claim 1. (9) The inspection system according to claim 1, further comprising flashing means for generating flashing light, and wherein the stimulation control means controls the flashing means to generate the flashing light. (10) The invention further comprises visual motor device means for generating a visual motor test stimulus, and wherein the visual control means is characterized by the visual motor device means for generating the visual motor test stimulus. Inspection system according to paragraph 1. (11) Automated testing of patients IIJ
*An integrated medical testing system for a patient, comprising:
- operator control means for, in response to an evening selection, providing a Brosena input signal corresponding to said selection; and displaying said desired stimulus to be provided in response to said processor input signal from said Aberator control means; Control m
the system 11 further comprises means for automatically applying the stimulation to the patient in response to the control signal from the processor means; scanning light source means for generating scanning light containing said desired stimulus to be stimulated;
The stimulation control means controls the scanning light source means to generate the scanning light in response to the control signal from the processor means; An inspection system that generates status signals indicating the status of the inspection. (12) An integrated medical testing system for automated management of test stimuli to a patient, comprising a processor responsive to an operator selection of a desired stimulus to be applied to the patient; Input 1g
8; processor means for generating a control signal indicative of the desired stimulus to be delivered in response to the processor input signal from the operator control means; stimulation control means for automatically delivering the stimulation to the patient in response to the control signal from the system, the system further comprising: a flash of light for generating a flash of light containing the desired stimulation to be delivered; means, the stimulation control means controlling the flashing means to generate the flash, the flashing means including a flashlight, and the operator selection of the desired stimulus being directed to a position in front of the patient. an operator command to lower the flasher, said flash means further comprising a motor for lowering said flasher in response to said operator command (examination system); (13) for automated administration of test stimuli to a patient; an integrated medical examination system comprising: a periphery of a desired stimulus to be applied to said patient;
9 operator control means for providing a processor input signal corresponding to said selection in response to a selection; Previous! l! , processor means for generating a control signal indicative of the desired stimulus to be delivered in response to the stimulus input signal from the control means;
a stimulus 11310 means for automatically applying the stimulus to the patient in response to the control 11 from the means, the system further comprising visual motor device means for generating a visual motor test stimulus. , the stimulus control means controls the visual motor device means to generate the visual motor test stimulus, the visual motor device @1 stage includes a stripe cage and a motor, The operator selection of the examination system 7 includes an A verator command to lower the stripe cage to a position near the patient, and the motor lowers the visual motion device in response to the command. 3. DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a 21-viewerized electric eye position description system, and more particularly, to an electric eye position description test and automated management of patient response. , then automate the results obtained from such tests! It concerns an integrated system for II management. Automated management of tests is subject to the control of one test management device through an operator control unit.

[Indirect control by the test administrator]
- Programmed with Combi 1-Event automated
It is carried out according to the control. For a long time, electrical ophthalmoscope (EOG) or electronystagmus
Descriptive techniques are useful for certain patients, especially patients with balance disorders.
used by doctors to obtain useful information about
It's getting worse. Such information belongs to S people according to the Kuwa type.
Give visual and vestibular stimulation to stimulate patient's eye movements.
It is obtained by observing the Sometimes this
Observations such as these provide the only physical evidence to support the patient's complaint.
and they also help doctors understand the anatomical location of the patient's disease.
This will help determine the location. For example, watch eye movements.
By sensing, the doctor can identify peripheral vestibular and central vestibular disorders.
often identified as located within the nervous system of
It can sometimes cause strange or moderate problems in the surrounding area.
Central nervous system disorders can be further localized. In the early days, doctors could only diagnose patients by looking into their eyes.
observed eye movements. However, with this method,
It is not possible to prevent the patient from fixating their gaze.
Because of this, important signs are often overlooked and
By fixing your senses, you can effectively prevent certain types of nystagmus. Sara
However, certain brain lesions and certain drugs impair visual suppression.
This phenomenon can be ignored if visual fixation is not tolerated.
unless nystagmus is observed when and when it is ruled out.
cannot be evaluated. Numerous methods were available to overcome the weaknesses of the superiors.
However, the best method to meet the doctor's requirements is electronystagmus imaging.
there were. Electric nystagmus depictions are widely used for research in psychology and ophthalmology.
It has been used a lot. It has been widely used in research on nystagmus.
Although it was also used to record other eye movements,
It gradually became better known as the nystagmus recording device.
It was. Basically, electronystagmus depiction (ENG) shows that the eyes are actually
This is based on the fact that the cornea is
electrode, the retina is the negative electrode, and the potential difference between the two poles
is typically at least 1 millivolt. This potential is the head
In the front, there is an electric current that changes the direction of the eyeball as it rotates.
Create a world. These electrical changes are detected by electrodes on the fool's skin.
can be emitted, and the changes are amplified by the writing device
When used to drive the eye position trace
can get. Man by Barber and Stockwell
ua+ orE 16CtrO-nystaa■og
raphy (St. Louis: TheClV 0Mos
by Co5pany, 1976)
Electrodes can be placed on the skin in many ways, such as
However, standard techniques for therapeutic purposes
, two electrodes on each side to monitor horizontal eye position.
one after the other, one on the right temple and the other on the left.
Placed at the temple and for monitoring the vertical position of the eye
Place one of the second pair of electrodes above the eyes and the other at the eye level.
below the ground and serve as a grounding or reference point.
Still other electrodes are placed, usually on steel. Of course, other electrode configurations can also be used.
It is known in the technical field, even if
Occipital placement is also possible. It is possible to monitor eye movements using such an electrode arrangement.
An important problem with the prior art regarding
, any value of the electrical parameter to be measured (e.g.
the need to maintain a certain relationship between
At least it comes from a request. Typically, that
With continued use of electrode configurations and measurements @stomach,
Generates offset voltage. i.e. measurement @ gastric cap.
Because the libration changes, the center position of the eyes may vary.
Don't read the O bolt, but rather read a certain finite bolt (offset).
(shown as a voltage). This is a clear drawback regarding the accuracy of measuring eye movements.
Become. Devices with such electrode configurations usually include an amplification stage (or
It is equipped with a preamplifier (as in most cases), so the offset
Adjust the amplifier configuration to eliminate the zero voltage or
Prior art for biasing was limited to manual techniques
. Although such manual techniques are improving, two main
It has some drawbacks. First, such technology is at best
This results in a wide range (coarse) adjustment and therefore a
Achieve the necessary narrow range (mold) adjustment for maximum accuracy.
stomach. Second, such manual techniques, even if
Continuous to eliminate offset voltage even when carried out
Additional efficiency and ratio achieved through automatic zeroing
cannot be compared. As previously mentioned, placing small electrodes on the patient's head
ocular activity can be recorded by Especially water
Electric eye position representing measurement of both horizontal and vertical eye movements
The depiction is recorded with electrodes attached to the patient's head. child
The patient's eye movements and visual responses are recorded during the examination, such as
It will be done. Typically a series of 61il ocular motors, vestibular
and response checking is performed as follows. (1) Gaze test with both eyes open and closed.
1i11! ! l looks straight ahead, looks to the right, looks to the left
Eye movements are recorded when looking up and down. (2) Reaction test to sudden movement: flying light beam
Eye movements are recorded as the patient follows the pot. (3) Follow-up examination: The patient detects a light spot that moves non-uniformly.
The movements of the eyes as the object follows are recorded. (4) Visual motor test Two movements to the right and then to the left at various speeds.
Move vertical stripes to ll1l! The eyes I see
The movement of the image is recorded, and this test is performed while the image rotates.
While the patient is stationary and the image is stationary
It is performed with the patient rotating. (5)! Febrile nystagmus test: each ear is irrigated twice;
Once washed with air above body temperature, and once below body temperature
of air, and this cleaning affects the vestibular sensors.
Additionally, horizontal nystagmus occurs. (6) Visual evoked response test: visual acuity is measured, the optic nerve,
Integration of the visual pathway including the optic chiasm and the anterior visual pathway
is analyzed and treated with a series of short 8-intensity light pulses.
The cut m pole (this is positioned on each side of the eye) is stimulated by
, i.e. electrodes above the right/left eye and 11 above the right/left earlobe.
and a reference (ground) electrode (this is placed on the patient's forehead)
It is recorded in the cabinet. It is within the art to administer such tests.
However, such tests typically involve only one person or
be dismembered by further doctors or attendants.
carried out in various separate, non-integrated components.
is being operated on the client. For example, some devices test reactions to sudden movements.
The vIk is then used for the remaining tests.
An investigation will be conducted. In addition, a group of devices (optical
The vessel or optical scanning Vi111) is a reaction to sudden movement.
Used to manage testing and follow-up testing, and then
Group 2 of equipment W (visual exercise equipment combined with a rotating chair)
W) is used to perform visual motor testing. this
These various tests can be performed with various and exciting types of equipment.
availability of an integrated system for conducting
No time wasted in managing such tests.
However, depending on the statistical data obtained, I
[A necessary inaccuracy has occurred.] Furthermore, the data obtained as a result of the above-mentioned tests are
Typical electronic noises, eye blinks, random eye movements
This includes errors caused by poor electrode contact, etc. subtle
voltage change (this is a few microvolts per eye position)
(as small as a root) is amplified several thousand times.
In a typical system, the statistical distortions can be
This is the issue. For example,
The above-mentioned "
The "offset voltage" phenomenon is the main cause of statistical inaccuracy.
It is a contributing component. Finally, the electrode measurement data is recorded directly in Record@- after amplification.
Typical prior art systems such as those recorded
Improper calibration of generating or recording signals
There is always the possibility of inaccuracies resulting in errors. the result
, no matter how precisely measured and obtained, the raw data
of such extra signals and/or recording devices.
The inherent lack of calibration causes distortion and
Accurate data cannot be retrieved once it has been recorded incorrectly.
It becomes impossible to do so and is lost forever. There are several attempts in the prior art to overcome the latter drawback.
There was a difference. In particular, Robert W., Ba1oh
et al in A Igor
lthm for a nalysis
of 3accadic Eye Moveg+
ents Usinga D 1altal
Cog+puter, ' Aviat
ion. 3 pace and Envlror
v+mental M edlcine (Ma
y 1976), I) 11. 523 ff, d
A system like the one disclosed has been developed and
measurement data corresponding to vertical and vertical eye movements, as well as target
The print position is digitized and then recorded on magnetic tape.
be done. Later, when such digitized records are
against sudden movements previously recorded in fly mode movement.
Sudden movements emitted by Wa to analyze eye movements
analysis program (3accade to nalysls)
Program+: Co-equipped with SAP)
loaded into the computer. Such a system
Not only the processor and memory but also various peripheral devices f (F,
disk drives, magnetic tape drives, graphic disk drives,
play terminal, and hardcopy printer).
You can prepare. Such systems display raw data for visual inspection.
displayed and recorded and/or digitized by the user.
The data can be examined for possible errors.
However, such devices
is an “offline” system, so the data is
It is recorded by two movements and then by the time lapse between them.
The second operation (for the new device) is separated by
It is also important to pay attention to the fact that it is managed. Other types of prior art systems were issued on July 8, 1975.
United States Patent No. 3゜893.450
With the disclosure of ERTL's "Electroencephalogram Testing Method and Apparatus" in issue No.
is exemplified. This patent is for example
10 Using EEG technology, the patient's brain waves,
IIIWI (e.g. light) is applied to the patient's brain waves.
The test is performed by determining the properties of points that can be determined mathematically.
A method and apparatus for testing are disclosed. Such a decision
When performing the test, stimulate the patient, e.g.
closed-loop feedback paths (e.g.
(path between the computer and the optical stimulator)
can be changed. However, the system as represented by the latter patent
Stems can overcome most, if not all, of the problems mentioned above.
It does not provide a solution to the problem. in this way,
The winner's patented system, even if it is based on instantaneous brain wave data.
Intermediate processing and consequential control of light stimulation accordingly
Even if the operator control unit (console)
Automated various test stimuli to the patient using!
! Contains an integrated system that can perform luck
Corrects the “offset voltage” phenomenon rather than the
in a way that can be easily and also accepted.
and in a very short time, an attending physician or test administrator
The resulting test will provide important information to the
It does not involve rapid automated processing of survey data.
stomach. In summary, automatic test management (including control of test stimuli)
data recording, real-time display, and quick
Need for an EOG system that can perform fast and accurate data analysis
Gender has always been felt. There is such a system
Doctors can obtain important information in a short time and in an appropriate format.
I can do it. Therefore, according to this invention, computerized
Electric Eye Position Delineation (CEOG) system is provided and
Specifically, various electrical ocular position descriptions (EOG) and
In response to operator selection for sensory evoked response (VER) testing
Automated administration of such tests to patients
Instantly record test results (raw data) online.
and display such raw data in very short bursts.
1m to the inspection manager in an acceptable manner! important feelings
Analyze information quickly and accurately, and within the mold.
are electronic noises, eye blinks, random eye movements, and electrical
Connected to eliminate errors caused by poor contact between poles, etc.
such that continuously/automatically processes and edits data;
An integrated CEOG system with
It will be done. The CEOG system of this invention basically consists of the following components:
6, i.e., visual motor testing.
A rotating chair for management and, for example, visual exercise @
Explosive visual test stimuli such as flashlights, flashlights, and light sources @
Controlling both the stomach and the rotating chair and visual examination needle
patient system including each 118@11 for
Or inspection@M: Receive electrode inspection data and compile it.
various input PIFs (preamplifiers,
amplifiers, and digitizers): e.g.
management equipment, storage media, displays/keyboards, and hardware
computers, including copy printers, as well as each
Easily control test stimulus management and test data entry
A computer, the aforementioned control device and various
It includes an interface device for the input device FIIJl. The integrated CEOG system of this invention
By providing the ll11w part (console), the patient
enabling automated administration of test stimuli for
allows test administrators to specify the characteristics of the test being managed.
selection of one of various forms of stimuli according to a given form;
and also the desired stimulus characteristics or various
parameters can be shown. For example, inspection management
The person is a visual motor test! ! Operator to perform coral
The control unit (console) can be activated. especially,
The administrator can command the rotation of the chair, select the rotation speed, and
With a rotatable chair by selecting the number of rotations to be rotated
, driving both the visual motor apparatus in an automated manner
be able to. This visual motor device is the visual motor device.
command to lower the position to a predetermined position, and the visual movement @-
For example, it shows the rotation speed of the stripe cage. similar
Inspection Y! ! Each operator uses a flash device or optical scanner.
drive each, and control the scanning speed, scanning pattern, etc.
Automatically protect against sudden movements by specifying
C of this invention to manage response testing or follow-up testing.
The EOG system can be activated. Furthermore, in the CEOG system of this invention, the patient's
Electrode test data obtained from electrodes attached to the head is
Stored in system processor after amplification and digitization
The system uses a variety of conventional displays If (graphs).
fixed display terminal equipment, hard copy printer
Display the raw data directly via any of the
be able to. However, initially the steepness of the input voltage signal
A typical characterization of such electrode test data is
The negative effects of offset voltage are encountered only with manual techniques.
and compensated by automated technology t't*
In this respect, the CEOG system of this invention is unique.
It is something. In particular, the CEOG system of this invention is
Analog test data signal after 111a and before amplification
Provides immediate visibility to inspection managers and furthermore provides central location
Perform a zero volt readout for a non-fluctuation of the patient's eye from
By adjusting the amplifier so that it
Manually adjust the amplifier circuitry to eliminate the “cut voltage” effect.
Provide a means for the inspection administrator to adjust the M quasi-voltage of
. Furthermore, the CEOG system of this invention
The sensor detects selectable options for automatic zeroing.
Inspect! ! give to the person in charge. Finally, the CEOG system of this invention
The sensor allows for immediate online processing of input test data.
processing and therefore the immediate processing and processing of input test data.
and edits to eliminate electronic noise, patient blinks, and patient runs.
Errors caused by dumb eye movements, poor electrode contact, etc.
can be removed. Thus, the CE of this invention
The OG system typically uses a few millimeters per eye displacement.
Detecting subtle voltage changes on the order of microvolts
can be amplified several thousand times without any distortion.
data that can be processed in real time and stored in memory
Records processed data for future use.
You can also display data. Furthermore, the CE of this invention
The OG system does not accept any extraneous signals from the outside world.
(and without generating any extra signals internally)
) can achieve the purpose of ho. Thus, the CEOG system of this invention is acceptable.
Provide doctors with essential information in an efficient manner and in a very short time.
Perform quick and accurate data analysis to
be able to. The f-event given in this way is typical
Specifically, the amplitude, frequency, and frequency of the fast and slow components of nystagmus
duration and from one visual target to the other in a short period of time
The synchronized movements that the eye performs when moving to the visual cue
Maximum, minimum and average speed of sudden movements
and the amplitude and sudden movement amplitude and light jump amplitude.
Comparison and measurement of delay between light jump and eye jump
including. 411 data is the CE OG system of this invention.
results from statistical analysis performed by
followed by a graphical representation of the information resulting from it.
i) Sit down. Therefore, it is an object of this invention to
To provide an episodic position depiction (CEOG) system.
, and especially various EOG and VER tests on the patient.
automated management of audits and subsequent acceptance
to the attending physician in a very short period of time and in a formal manner.
of the resulting test data to give important information.
Provides an integrated system for automated processing
It is to be. One aspect of this invention is that various test strips included in the system
Using high-speed equipment, the results selected by the inspection manager are
Automate EOG or VER testing quickly and efficiently
provides an integrated system for
Is Rukoto. Still other aspects of the invention provide options for various test stimulus characteristics.
Not only does it respond to the pelleter specifications, it also responds to the patient.
the desired stimulus in response to operator selection of the desired stimulus to be
A method for automatically giving test stimuli with characteristics to patients.
The goal is to provide an integrated system. Yet another aspect of the invention provides an excellent test
and the operator whose property operator selection is ill
S easily carried out using controls or consoles
Integration for automated tubes of test stimuli for *
The goal is to provide a system that is Yet another aspect of the invention is that electrode test data is
recorded online and inspecting such raw data
! ! Test strips that can be displayed instantly to coral reefers.
Providing a system for highly automated management
It is. Still other aspects of the invention provide that the electrode test data is
Possible cicada-like and required by the doctor in a very short time period.
instantly and automatically to give you the important information you need
to provide an integrated inspection system that analyzes
That is. A further aspect of the invention is that the invention is typically connected to a patient.
The offset encountered when extracting the test f-ta from the N-pole
In the cut voltage ring! ! The impact is manual and automated.
Integrated CEOG system counterbalanced by adjustable ability
It is to provide the stem. The above objects and features of this invention can be understood with reference to the accompanying drawings.
It will become clearer from the detailed explanation below.
. Figure 1 shows an extensive overview of the CEOG system of this invention.
This figure shows how the CEOG system of this invention can be used for patient systems or examinations.
Electrical eye position drawing for subject 2 practicing in station 4
photo (EOG) test and visual evoked response (VER) test.
It is for use in carrying out. Typically, the electrode
A junction box 6 is placed at or near the head of the subject 2,
The electrodes 6a to 61 connected to the junction box 6 are EOG
In order to enable the test, it is attached to the scalp of subject 2,
For VER testing, 211J electrodes were used for each patient.
The right occiput/' of the head is also connected to the earlobe, while the fifth
electrode 61 is placed on the patient's forehead as a ground (or reference) electrode.
Connected. The test station 4, where the subject is located, places the subject 2
It includes a rotating chair 8 for rotating, and the rotation of this chair is
1IIJIl] by the control a device 10. Inspection station 4 also includes a light spot for generating a light spot.
The normal circle of the inspection station 4, such as the light spot source 12
Light is applied so as to generate a light spora 1 appearing on the cylindrical mold 18.
A set of X-■ running to receive and reflect Spora 1-
The x-y scanning of 1114 is performed for a specific inspection.
c×o according to the controlled pattern required by the inspection.
The light spot moves in the /' or V direction.
controllable in order to
The tunnel 4 is also projected onto the cylindrical wall 18 and onto the wall 18.
a visual sexual motor apparatus or system for
system (vertical stripe projector) 16. Lights
Pola 1-Source 12. X-y scan 1114 and visual movement
The operating device 116 is controlled by the relay panel 2o.
This is itself controlled by I[I and W11o.
I will be treated. In the particular device shown in FIG.
and 5e and 5f are the horizontal eyes of subject 2, right eye and left eye.
are connected to detect the movement of each. Similarly,
W poles 6c, 6d and 61J. 6h simulates the vertical eye movements of subject 2's right and left eyes.
are connected to each other for measurement. After m, the reference electrode 61 is connected to the temple area of subject 2.
be done. Other configurations of the electrodes 6a to 761 are also available! managed
used as required by the specific test.
I know that I can do it! ! should be understood. In fact, electrodes 6a to 61 are commonly used for controlling EOG examinations.
connected to the configuration used, but additionally other electrodes (
(not shown) is the VER test! ! For the sake of coral゛°earlobe
``Being able to connect to subject 2 in the configuration
I want you to understand. Electrodes 6a to 61 are connected to preamplifier network 24.
, the output of this image quality amplification circuitry 24 is filtered/amplified 11
Given to 26. The filter/amplifier 26 has a respective
Analog output on each channel corresponding to electrode measurement
and they are RH (right horizontal), RV (right vertical), L
H (left horizontal). LV (left vertical), RO (right III), and Ohi LO (left
Manju). A from filter/amplifier W26
The analog output is given to the digitizer 28, which
The timer 28 transforms the analog signal into a corresponding digital signal.
Substitute. The digital signal from the digitizer 28 is
Through the computer interface circuit 30, the general
given to the computer indicated by the reference numeral 32.
It will be done. In a preferred embodiment, computer 32 is a
digital input test data in response to the data program 36.
(i.e. computer interface 30)
the digital output of digitizer 28 provided through
and visually display the inspection data on the display @38.
No, the test results are hard-copied to the hard-copy printing device 40.
peripherals such as floppy disk 42.
to provide permanently recorded test data via the device.
A second processor 34 is included. Computer 32 also inspects
Operator control of administration, processing of test results, and
It includes a keyboard 44 on which output of results can be performed.
nothing. The CEOG of this invention is also connected to the processor 34.
automatic calibration or calibration (or bias
) times m46, thereby preamplifier circuitry 24
automatic (processor-controlled) biasing of
be able to. This is a manual bypass of the preamplifier network 24.
Added to asification. As explained in more detail below
, the preamplifier network 24 is manually adjusted and preferably
or automatically adjusted to ensure correct preamplifier bias
, so that the offset of electrodes 6a to 61
By compensating the voltage, the subject's eyes are centered in one direction.
Maintain zero adjustment for each electrode when directed to. In a manner described in more detail below, the processor 34
is the computer interface 30 and control-@w1
The rotation of the chair is controlled through the control unit @10 and
and the test needle to the subject 2 via the relay panel 20.
It may also be noted that controlling the intensity of
. Referring to the electrode junction box 6, in a preferred embodiment the preamplifier
Wider network 24 is physically located at electrode connection 116
That should be noted. Figure 2 shows a more detailed diagram of the CEOG system of this invention.
This is a diagram. Various elements of the CEOG system
Reference numbers used in Figure 1 to indicate
It is also used in Figure 2. The CEOG system of this invention generally refers to FIG.
patient system or examination station including the rotating chair 8.
4, and its chair 8 has VER and
Subject 2 sits during the EOG test. Chair 8 has motor 50
The motor 50 is rotated by the electric current 1 [(for example, 11
0 volts, 60H2) motor control @@52
driven by. Motor system"18@1152 is in order
Next, the control device 10 receives the information from the control panel 54'.
Controlled by input control signals. Furthermore, the motor 50
various output status signals from the
position and velocity) of the CEOG system.
Motor l1ls device l152 to distribute to other parts
to the control panel 54 (described in detail below).
(clarification). Electrodes 6a-61 (attached to subject 2 (Fig. 2)
The electrode test data extracted from Figure 1) is
converter stage via network 24 and amplifier network 26.
Analog-to-digital converter (AD
C) is given. Digital display of electrode inspection data
EOG input is extracted there and as input DATA.
is provided to the processor 34 via the interface 30.
. In a preferred embodiment, the operator is provided with a
Electrode test data signal generated by width gauge circuitry 24
If a signal monitor scope 58 is provided to display the
Always beneficial. For example, displayed on scope 58
By looking at electrode test data, the CEOG system
The operator can manually adjust the bias of the front 1 amplifier network 24.
voltage offset of the electrodes.
Extensive bandwidth of preamplifier network 24 is used to compensate for
Easing signals can be achieved easily and quickly. Furthermore, as seen in Figure 2, the CEOG system
The preferred embodiment includes a selector switch 59, which
Switch 59 allows the operator to adjust the display on the scope.
Select test data signals from a specific pair of electrodes for
and thus correspond to the selected pair of electrodes
Make individual bias adjustments for each respective preamplifier
. Additionally, the processor 34 processes the received digital test data.
As a result of processing data DATA, interface 30. Ko
The preamplifier via the inverter stage 56 and the amplifier network 26
The output BIAs are provided to the amplifier circuitry 24. Input BIAS
Continuously and automatically adjusts the electrode offset voltage in response to
The preamplifier network 24 automatically biases the
Assured. A control panel 54 is used to distribute the electrodes through the system.
It works as a power distribution junction box. In particular, the control panel 54
is powered by a 110 volt, 60 hertz power input.
, give these A, C, and power to the power source 60, and this power source 60
In response, C, the voltage (+5V,
+12V, +15V, -15V, etc.) as necessary.
to the various elements of the system. control panel 5
4 also receives various power inputs from the power supply 60.
, and such that C, power input is passed through the system.
distribute. In this way, as shown in Figure 2, the power output
The power PWR specifically includes the preamplifier circuitry 24, the amplifier circuitry
26. ] Control panel to converter stage 6 and logic section 62
54. Control panel 54 also provides various logical controls throughout the system.
Performs the function of distributing signals. As mentioned above, the chair
A motor control device 52 for controlling the rotation of the motor is a control panel.
54, and the control signal is sent to the logic section 62.
and the processor 34. In particular,
Control panel 54 provides control signals to
These control signals cause the chair 8 to start rotating according to the command,
Rotates at arbitrary (commanded) speed S, 1L or one time
A series of rotating wheels, or stopping and reversing on command
The motor 50 is controlled in such a manner that the motor 50 automatically resumes rotation.
Motor control device l to control! 52. Control panel 54 also includes motor 50 and motor controller.
Chair position indication signal provided by chair 8 via 52
and receive various status signals such as chair rotation information.
Distribute one. Such status signals are provided by logic section 62 and
is provided to interface 30. For example, motor
50 and motor control device 52 are connected to control panel 54.
On the other hand, the status signal regarding the actual speed of the rotary chair 8 is determined.
Tachometer information and chair 8 digit 1 relative to starting position
position information, and a position detection circuit (not shown in Figure 2).
Each chair detected by
Transmits rotation information related to detection of completion of child rotation. The control panel 54 is also configured as described in more detail below.
It works with relay panel 20, so the inspection
control the scanning stimulus and therefore light spot source 12 and
and ×-ν scan l114, visual motor device w16 (stripe
By controlling the camera 76) and the flash device 70,
Test for person 2! ! Control coral. To explain in more detail, the relay panel 20 is
Controls the use of the light source 12 and controls the use of this light spot.
The light source 12 provides a test stimulus consisting of a light spot.
Working with shutter 66 and x-y scanning 114
move. The light spot is
Corresponding to the desired test stimulus for e.g.
Moves according to pre-programmed patterns. Lights
Pot 1 [(or laser)'12 is preferably M13
trOIOQlc lnstrument,
Metrologic manufactured by Inc.
1aser, Mode! No, ML-600
Or ML-620. The shutter 66 is a laser
Turning the laser beam on and off, which is a disadvantage
used to block the laser beam rather than
mechanism, preferably realized by a solenoid.
It will be done. This solenoid is located in Columbia, Maryland.
Manufactured by Quardlan, P flzer
Available from Medical System-3
Model No. T6x 12-C-12V D,
C. The solenoid for shutter 66 is just a small metal
Move the metal piece to selectively block or block the laser beam.
It just doesn't stop. Eventually, the x-y run
[14] preferably located in Water, Massachusetts;
Town Qeneral Scanning,
I nc, next manufactured by @1, a 5e
rles X Y -300 Scanning
A 5sesbly,, two
G-330Ga1Van01 eters,
an X-7M mount, anda
n A-102Driver AspHfer, to
Therefore, it is realized. Furthermore, the relay panel 20 is used to move the flash device 70 up and down.
control the motor 68 used for the
J (VER) on subject 2 for the purpose of conducting the test.
A flash device 70 is placed at the position. The flash device 70 is operated by the photo station 1 emulator 72.
controlled, this photostimulator 72 sequentially
, 10 via logic section 62 and interface 30
Controlled by sensor 34. Flash device 70 is preferably
) Mato Stimulator Girlfriend, Model Ps22 (This is
Massachusetts. Kleincy's Grass tvl educational
Manufactured by ln5trusents)
It is realized by yo・]. Finally, the relay panel 20 activates the visual motion device 1116.
Control this device! 16 goes up the live cage 76 to S1.
It consists of a motor 74 used to lower it. That's it
The visual motion device 16 performs an EOG test on subject 2.
This is used, for example, when carrying out. Figure 3A shows the 61i11f amplifier circuit of the CEOG system.
2 is an illustrative diagram of a net 24. FIG. Figure 1, 21! I and 3rd
Referring to Figure A, the preamplifier network 24 described above is preferred.
Alternatively, it is placed in the electrode connection box 6 (FIG. 1). Electrode 6a
61 are connected to preamplifier network 24.
. In particular, the preamplifier network 24 of FIGS.
Basically, referring to FIG. 3A, amplifiers A1 to A8
〇, each of them has a specific connection to subject 2.
Pair electrodes 6a/6b, 6c,/5d,...
corresponds to Is the preamplifier network 24 a corresponding pair of electrodes?
for receiving and responding to input test data signals from
1 amplifier output PREMP1, PREMP2,...PR
for providing EMP6 to amplifier network 26 (FIG. 2).
Individual preamplification 11A1. A2. ..., including A6. Preamplifier AI. A2. ..., A6 is also zero-adjusted manually ZRADJ 1
. ZRADJ2.・ZRADJ6@Uke, Koreha, 5th
Processor 34 (second
manual bias adjustment by the operator under the control of
or from automatic bias adjustment. In this way, a specific eye measurement (e.g. left vertical eye measurement)
) for which the electrode test data signal is received
(e.g. preamplifier A1) and 10 ends.
given to the child. After amplification in preamplifier A1, the preamplifier
An amplifier output is provided. In particular, the preamplifier A1
The amplifier output is transmitted via its terminal A.
, 5 can be obtained as I P 1. ZRADJ corresponding to bias adjustment of preamplifier A1
1 is received and the characteristic to be adjusted.
a fixed preamplifier, in this case applied to terminal 2 of preamplifier A1.
available. ZRAOJl, ZRADJ2. -u increase I11
Circuit wJ2 a tfi raka (manual bias in case of
adjustment) or converter stage 56 and interface
1 from the processor 34 via the DAC included in the processor 30
(in this case, automatic bias adjustment).
(This is the BI zero adjustment signal in Figure 2.
(denoted as AS signal). This subject is further detailed below.
specific information. Power signal (this is shown as PWR in Figure 2),
Especially +15 volts DC, -15 volts DC1 and connections.
The ground signal GND can be used as a power input for various prefixes.
to terminals F, E and H of amplifier IAI to 86, respectively.
Given each preamplification! For IAI or A6 terminals
Grounded. Most importantly, the preferred embodiment is for preamplifier A1 only.
As shown in FIG. 3A, each preamplifier AI
- Input/output connector connected to A6 by coaxial cable
Each preamplifier A1 to
Terminal B of A6 is preferably the outer shield of the coaxial cable
commonly connected to This common ground connection configuration
It is significant in that it helps people refuse
thus eliminating a substantial amount of the system noise normally encountered.
. FIG. 3B shows the preamplifier network 24 of the third All.
Width gauge A1. A2. ... is a detailed view of A6. Basically, pre-amplifier A1. A2. ...A6 each increased
includes a width adjuster AMP1, which in the preferred embodiment is A
D522 amplifier, manufactured by A na in Massachusetts.
Manufactured by log devices
be. The amplification IAMPI is connected to the terminals and the electrodes through 10.
Receives the inspection data signal. Such electrode test data
The signals are applied to terminals 1 and 3 of amplifier AMPI, respectively.
It will be done. Diodes OR1 and CR2 are “static discharge J”
This provides protection to the amplified IAMP1. Capacitors C7 and C8 are connected to the electrode test data signal.
Connect terminals and ground to eliminate high frequencies that interfere with
and between terminal 10 and ground, respectively. terminal
and 10 and the ground, respectively.
Anti-R13 and R14° before plugging in the electrodes
5 megohms to drain leakage current from amplifier AMPI
A resistance of If this is not done, the voltage
(±15 volt magnitude) is the Conansa C7 and 08
, thereby allowing patients to receive their shots via NIi.
You will receive a lot of credit. Amplifier AMPI also has its terminal 2
and has an external IP setting resistor R8 connected to
do. The variable +1i anti-1 filter 1 at its terminals 1 and 3
When the input is short-circuited, there is a zero voltage at terminal 7 of the amplifier MPl.
The offset zero potential is adjusted to give the
Ru. Yet another supply voltage -VEE is connected to the amplifier at its terminal 5.
Given to AMP1. The amplifier 11AMPI has its output P
REMPi (, i-1, 2, ..., 6) as an amplifier circuit
network 26 (FIG. 2). As described above with respect to FIG. 3A, preamplifier network 2
4 each amplification 11A1. A2. ..., A6 is for each
Input ZRADJ i, ZRADJ 2. −. Regulated by ZRADJ6. Referring to Figure 3B
, such a belief @ZRADJI (] -1゜2,・
) corresponds to manual zero adjustment performed by the operator.
Therefore, the interface 3 of FIG.
o and by the processor 34 via the converter stage 56.
automatically generated. Sonoyo na fJ@ZRAOJI (1-1,2,-”
) is given as input to amplifier AMP2 at terminals 2 and 3.
, which is the zero adjustment input current ZRADJI(+ −1
e2. ...) to the output voltage V, ["
Works as a current-to-voltage conversion amplifier. Enter hZRADJI
It is extracted from the circuit 46' of FIG. 5, which will be described later. input]
The digital 2C9 removes the noise from the DJi to the input signal 2R.
established for the purpose of removing To amplifier A, 4P2 has a filter.
A feedback RC network is provided and this network is
sensor 010 (also removes noise) and amplification
connected in parallel between output terminal 6 and input terminal 2 of device AMP2.
It consists of a resistor R11 connected to the resistor R11. supply voltage +vc, and
-VIE are terminals 7 and 4 of amplifiers A to IP2, respectively;
bias capacitors C11 and C
12 are the respective ends 'f-7 and
and 4 and ground. amplifier AMP2 (as shown and explained above)
is zero adjustment M flow ZRADJI (i = 1°2,...
), the amplifier AMP1 (
The voltage output sent to the terminal 11) is converted into ■aEr.
Ru. The supply voltages +v, c and -VEE are each times m10
0 and 102 (Figure 3B) to amplifier AMP2.
I can't give it. Circuits 100 and 102 are from an RC network.
In the case of circuit 100, this circuit network has resistor R1 and
, and the circuit 102 consists of capacitors c1 and C3.
If the resistor R2 and capacitors C2 and c4
It will be. The user's RC circuits are -15 volts and +15 volts respectively.
supply voltages −VEE and VEE, respectively.
+Vcc and simultaneously achieve noise decoupling
Ru. FIG. 4A is a diagram of the amplifier network 26 of the CEOG system.
It is a diagram. Amplifier network 26 includes each preamplifier network shown.
@PREMP1. PREMP2. ..., PREMP6
a plurality of amplifications 11A11°A12.・・・
・, including A16. Amplifier A11. .... A16 amplifies each preamplifier output signal mentioned above.
and left vertical eye movement, right vertical eye movement, left horizontal eye movement,
It corresponds to the right horizontal eye movement, the left halo movement, and the right halo movement.
The corresponding amplifier output signals AMPO1JT1. AMP
OLIT2. ..., gives AMPOUT6. Output A
MPOUT1. ..., AMPOUT6 is the converter stage
56 (Figure W42). Input PREMP1. PREMP2. ..., PREMP
6 is also applied to the selector switch 59, and this switch
The switch 59 controls the operation of the switch as shown in FIG. 4A.
For display on the scope 58 by biasing the rotor.
select a specific front-end amplifier output. This allows the previous
@Visible indication of amplified type output and therefore to the operator
Quick visualization of the results of the bias adjustment action performed
By providing an indication to the operator, the preamplifier output
Wide range bias adjustment of the force signal is facilitated. Conventional
The cilloscope implements the signal monitor scope 58.
However, this scope 58 is preferred.
<LtB&K PRECISION oscilloscope
model number 1403A, which is located in Illinois, California.
lI by DYNASCAN Corporation in the basket
! I will be built. Figure 4B is $114A! ! Amplification of l amplifier network 26
Vessel Al 1. Al2. . . . is a detailed view of A16.
. Basically, amplifier AIJ (J-1, 2,...)
each include an amplifier AMP3, which AMP3 is preferably
An example of this is AnalOg O in Massachusetts.
AD522 amplifier manufactured by evices.
Ru. Amplification 11AIJ of amplifier circuit network 2G (4th A factor)
The basic amplifier AMP3 comprising the first amplifier circuit 11
! 24 preamplifier A+ (+ -1°2,...)
The amplifier AMPi (and A
MP2). However, amplification 11AMP
3 (Figure 4B) external connections are to amplifiers AMP1 and AM.
It is different from that of P2 (Fig. 3B). Preamplifier output signal PREMPJ (j-1,2°・
) are each end of the amplified IAMP3 (Figure 4B)
1 and 3 via input circuitry 120. Specifically, network 120 includes resistor R3 in series with capacitor C5.
and a resistor R5 directly to capacitor C6.
C circuit, such an RC network is connected to the input PREMP
It is provided for the purpose of filtering j. Input circuit network 120
The diodes CRI and CR2 of the preamplifier A+
(Functionally corresponds to similar diodes in Figure 3B. Capacitors C7 and C8 are similarly shown in Figure 3B.
Compatible with capacitors and tested.
It functions to remove high frequencies while Resistor R13 and
R14 corresponds to the ground resistance also shown in Figure 3B.
. In a preferred embodiment, the separately drawn amplifier is
Each may be provided for VER and EOG testing. Ta
For example, if AC coupling is desired, resistors R3 and R4
can be replaced with a capacitor. amplification! IAMP3 is input PREMPJ (J −1°
2,...), and gain setting resistor R8 (this is increased
connected to terminals 2 and 14 of width switch AMP3).
amplify it by a gain factor established by 3rd B
As in the case of amplifier 11AMP1 in the figure, the supply voltage +Vc
e and -VEE are connected to terminals 8 and 5 of amplifier AMP3.
Each is provided. External adjustment of amplifier AMP3 is edible
It is provided via a resistor P1. Amplification IAIJ (j-
1, 2, -...), especially its AMP3 is an amplifier at terminal A.
Give the output AMPOLITJ (J-1, 2,...)
Eh, this output A M PJ is output from the converter stage 56 (Fig.
) is given to Fifth! ! l is the bias included in the amplifier circuit M26 in FIG.
FIG. 4 is an illustrative diagram of an ass circuit 46'. FIG. 1 shows the preamplifier network in response to Brose+j34.
Automatic adjustment for adjusting the offset of individual amplifiers within 24
While the dynamic calibration circuit 46 is disclosed
, in a preferred embodiment of the present invention, such auto-carrying
The bration function is provided by the amplifier network 26 (FIG. 2).
The source is in the as circuit. Referring to FIG. 5, the bias circuit 46- has an output ZRA
Due to the occurrence of DJ 1, ..., ZRADJ6, the previous
Amplifier circuit $124 (Figure 2)
Multiple potentiometers P for manual adjustment of ears
OT 1 , . . . , including PO-R6. preamplifier times
The individual amplifiers A1 . of network 24 (FIG. 3A). ..., A
6 such manual adjustments are, in the preferred embodiment,
Switch 81. ..., bias selection consisting of S6
Whether the selection switch is AUTO or MANUAL
Occurs when there is a crab. Bias selection switch 81.・
..., when 86 is in any position, POTl-P
Operator adjustment of OT6 works to change its resistance value.
and the current flowing through the droplet resistances R31-R36 changes.
Therefore, the gap adjustment WI flow signal ZRADJI-ZR
Change ADJ6. Automation of the individual amplifiers of the pre-amplifier network 24 (FIG. 2)
Adjustment is made using interlocking switch S1. ..., S6 (Fig. 5) is
Achieved when in AUTO position. to AUTO position
At some point, the automatic adjustment input signals BIAS1-BIAS6 are
is received from converter stage 56 (FIG. 2) and
The signals BIAS1 to BIAS6 are connected to the respective resistors R.
Zero adjustment voltage via 21-R26 *ZRADJ 1-Z
Contributes to the generation of RADJ6. When the bias selection switch is in the AUTO position, the front
m width l! Automation of the individual amplifiers of the network 24 (Fig. 2)
Both manual adjustment and manual adjustment
Resistance R21-R26 and manual adjustment R31-R
36 are connected in parallel under these circumstances.
This arises from the facts. However, the switch
is in the MANLIALIQ position, 'Manual: im'
Only the related resistors R31-R36 are compatible potentiometers.
(POTI-POT6), and resistor R21
- R26 is kept open circuit under these circumstances.
In view of the fact that the preamplifier network 24 (Fig.
) can only be manually adjusted. With the above configuration, the CEOG system of the present invention can be operated.
Perator is a specific potentiometer (POTl, POT
etc.) of the preamplifier network 24 (FIG. 2).
The offset voltage of the amplifier can be manually adjusted.
Wear. With this, the CEOG system operator
is a specific amplifier, e.g. left vertical eye shift, right vertical eye shift.
Achieving a wide range of costs for amplifiers related to motion, etc.
and can therefore be attached to the subject's head.
Most of the DC offset voltages associated with the corresponding electrodes
Everything can be removed. Such manual adjustments are
The result of an inherent or periodic “line-up” of stems
This invention can be achieved as a result.
The CEOG system also includes a preamplifier network 24 (FIG. 2).
) provides automatic, narrow-range biasing of individual amplifiers.
Ru. Such automation of the individual amplifiers in the network 24
The narrow range of bias is determined by the BIAS signal processor 34 (
Figure 2).
IAS signal is connected to interface 30 and converter stage
56 to the bias circuit 46- (FIG. 5).
Ru. Then IAS input (B IASl, B IA
S2. ) is the adjustment signal ZRADJ1. ZRADJ2
．． etc., and related to the corresponding electrode.
Removal of the remaining DC offset voltage is automatically achieved.
will be accomplished. FIG. 6A shows the ADC portion 56 of the converter stage 56 of FIG.
′ is an illustrative diagram. The ADC portion of converter stage 56 (FIG. 2) is an A/DI,
Contains multiple ADCs denoted A/D2 and A/D3.
These ADCs are connected to the amplifier network 26 (FIG. 4A).
Amplifier A11. Al1. .... Analog electrode inspection data from each of A16.
input signal AMPOUTI/AMPOUT2, AMPO
UT3/AMPOUT4 and AMPOUT5/AMP
OUT6 pair and connect these analog inputs to it.
Each is converted into a digital output DATO-DAT9. Yo
To explain in detail, converter A/DI-A/D5 is
Clocked by timing clock input SAMPLE
and thereby each converter has its respective
Analog input signals (AMPOLITl, AMPOUT
2. etc.) into a 10-pit digital word.
The word is internal to the specific converter A/D1-A105.
Stored in Barraa. Then, TR0 is sent to the computer processor 34 (FIG. 2).
BX and 5TROBY occur, converter
A/D I - A/D 5 internal buffer at appropriate time
Gating the data from the
Configure output 0ATO-DAT9. Furthermore, the ADC portion 56' is a motor that drives the chair 8.
Analog signal TACH2 that reaches a speed of 50 (Fig. 2)
and the stripe pattern of visual sexual movement @1116 (Fig. 2).
analog for the speed of motor 74 driving page 76
Receives signal STRI PE5PD and converts to digital format.
It also includes another converter A/D4 for converting the data. Most
Later, the ADO portion 56' of FIG.
Analog signal posx and
and PO8Y and convert it to digital format.
Includes an additional converter A/D5. Analog signal TA
CH2 has a control panel 54 and a logic section 62 (FIG. 2).
via motor control device 52 to converter stage 56
and the analog signal STRI PE5PD is the control parameter
channel 54 directly to converter stage 56,
Analog signal @PO3Xl3 UP OS Y Ge
Control panel 54 by channel 20
and the converter stage 5 through the l & transport section 62 (Fig.
given to 6. At the top of the bale, as shown below, each converter A/D1-A
105 is input SAMPLE! The input is analog
Begin converting the data to digital format. all
When all conversions are complete, the output DATRDY is output as
generated. These two control signals are further discussed below.
discussed. Figure 6B shows details of half of converter A/D1 in Figure 6A.
It is a diagram. The other half of converter A/D1 is shown in Figure 6B.
Understand that it is structurally identical to the first half shown.
I want to be Furthermore, each converter A/D 2-A/D
5 may be formed identically to converter A/D 1.
should be understood. The converter A/DI, i.e. each half thereof,
Basically, the sample holding circuit 150. ADC device 154
and buffers 158 and 160'Jr.
Holding circuit 150LtAmplification Ill configured as shown
66 and 168, and AND gate 170.
nothing. Sample hold circuit 150 is preferably an AD582 device.
@(This is made by Analoa Devlces
is created). Furthermore, ADC@1f154 is conventionally
It is a typical analog-to-digital converter device, and it is a good choice.
Preferably AnalogQ ev (manufactured by CES)
This is an AD571 device. Best of all, buffers 158 and 160 are configured as shown.
3-state amplifiers 172 to 177 and AND
Includes gate 178. That is, the output of gate 178 is
When low, the outputs of amplifiers 172 to 177 are Oka circuits.
and when the output of gate 17 is high, amplifier 17
The output of 2,173... is the input signal from ADC154 @
It is the same as 81.82°... Preferably a buff
158 and 160 are T exas I n5tr
6-3 state buffer manufactured by us+ents
, Model Nos, 5N74LS365 also
is 5N74365. In operation, the output AMPOUTI is a sample-hold circuit.
150 from the amplifier network 26 (FIG. 2).
It will be done. Signal DATRDY is normally high and signal S
AMPLE is normally low. SAMPLE goes high
If so, the signal DATRDY is also high and the sample hold
Gate G1 of holding circuit 150 is closed, so AMPOt
JTl voltage is amplified! appears in the input to 1168
. Signal AMPOLIT1 is then applied to the output of amplifier 168.
and therefore on both sides of capacitor C1.
Ru. When SAMPLE goes low, gate G1 opens.
Both SAMPLE and DfnπTY are high.
remains open until AMPOLITI is AD
Analog-to-digital conversion is performed in C154
Even if the amount changes, the AMPOUT voltage remains at the output of the amplifier 168.
remain. Therefore, when gate G1 closes, signal AMP
When OUT1 is sampled and gate G1 is open,
The sampled input signal is held at the AIN terminal of ADC154.
held. ADC@1f154 is connected to O- as explained below.
The signal SAMPL from the ADC logic circuit 200 is
In response to receiving E, the analog input AMPOLJT
1 digital conversion is performed. For digital conversion processing, ADO @154 outputs
DATRDY is held high and therefore DAT
Pull RDY low. However, once the conversion is completed,
Then, A[)([l1154 is the low output σ5(go R]
A signal A' is generated. Output signal (1-R]Σ)' goes high
To proceed, each converter A/DI.・, A/D617) 2 ADC@lfl 54f) each
must produce a low output at terminal DATRDY.
No. This will cause the output DATRDY (later AD
C1 & 11 circuit 200 (given to Figure 16D) is
You can go high. Digital pit output B1 to B6 is hex cross 7
Three-state buffers 172 to 17 for each of the doors 158
7 and the other digital bit output 87 to B
10 to a corresponding buffer (not shown) of buffer 160
Given. Additionally, buffer 172 of buffer 158
to 177 and the corresponding buffer of buffer 160? (
(not shown) is output until it receives a clock type signal.
It is of a type that causes an open circuit. In particular, see
The processor 34 (FIG. 2) receives an address input so that
The signal is transferred to the ADC address decode logic circuit 190 (6th C
(Fig.), which is explained in detail below.
block type signal 5TROBIO. 42〒]17 ``107'']-1... is generated. Like this.
Uni, yTROBl 0 is a buffer? 158 and 16o
and it is given as output DATO or DAT9
, Buff? digital bit data. Processor 34 (FIG. 2) via interface 30
Transmit to. Finally, FIG. 6B shows a portion of converter A/D1 in FIG. 6A.
Converter A/D
2-Each of A/D5 is formed identically to converter A/D1
It should also be noted that It is clear from the above explanation
Input hsTR of each clock type so that it is clear
OB10. .... 5TROBI 6.5TROBPX (See Figure 6A)
In response to A/D1-A/[)5, the first half of them
Release the digital output DATO-DAT9 of
0tsuku-shaped human power 5TROB11. ..., 5TROBI
Converter A/DI-A in response to 7,5TROBPY
The second half of /D5 is digital data DATO-DA
Release T9. FIG. 6C shows the address decoding of converter stage 56 of FIG.
Theory I! ! FIG. In particular, the logic circuit 190 is a binary/octal decoder circuit 192.
．． Consists of 194 and 196. Main to logic circuit 190
The key inputs are address inputs ADDR1, ADDR2 and
ADDR3 and human power GRPISTB, GRP2ST
B and GRP3STB. 23! /8 play decoder 192 is signal human power GRPISTB
(which acts as the decode clock signal) and the input
8 way conversion in response to reception of force ADDR1-ADDR3
and selectively select eight decoder inputs corresponding to specific decoder inputs.
Drives one of outputs QO to Q7. like this
In addition, the above-mentioned clock generator #5TROB10-8TRO
B17 is obtained. If I recall, 5TROB 10-3
TROB17 is A of converter stage 56 (see Figure 6A).
Each converter device A/ in the DC section 56'
D1. A/D2. ...is given to... Similarly, the binary/octal decoder 194
In response to receiving STB and ADDRl-ADDR3
performs an 8-way transformation and therefore for a particular decoder input.
Accordingly, the selected output °◇−σ or σ7 is driven.
do. In this way, the clocked output 5TROB20
−8TROB27 are obtained and these clock formats are
force (discussed later) is D of converter stage 56 (FIG. 2).
Used for AC part. Finally, the binary 78-decimal decoder 196 receives the signal input signal jGRP.
3STB and ADDRl-ADDR3.
performs an octal conversion and therefore
correspondingly drives selected outputs QO or Q7.
Ru. In this way, the clocked output STROBMX and
and STROBMY are obtained, and as discussed below
These clock type outputs are connected to the DAC circuit 300 (6th E
(Figure) is used as an Otsuk type input. In addition,
Coder 196 (Figure 6C) goes to A/D5 (Figure 6A)
A clock type output 5TR which is a clock type input is provided.
OBPX OJ: 'CFSTROBPYf occurs. Any binary/octal converter circuit is the binary/octal converter circuit of Figure 6C.
To decode hex decoders 192, 194 and 196
It is used for 23! /8 way decoder 192.194
and 196 is preferably a 5N74LS42 converter
Circuit (manufactured by Texas Instruments)
It is. FIG. 6D shows still another AD of the converter stage 56 of FIG.
2 is a detailed diagram of C logic circuits 200 and 250. FIG. The logic circuit 200 is a timer 200, preferably a 1 second timer.
This timer is used for A/D and D/A systems.
Inverter output R8T used for resetting
204.
respond to on. In particular, the output R3T is DAC times 11 as discussed below.
A certain latch circuit 302 included in 300 (Figure 6E)
- Used to reset 305. The logic 11 circuit 250 (Figure 6D) is basically a NANO game.
252 and one-shot mounting 254 and 256
Consisting of NAND gate 252 has input CMPSAMP
(1 bit from interface 30 in FIG.
bit number 14)) or 5MSSAM (
Detects the occurrence of any one of the inputs from the logic section 62 in FIG.
and trigger the one-shot device 254 (control
Verta A/DI-A/D5 (Figures 6A and 6B)
) output SAMPLE transmitted to the ADO device 154 of
give. As will be recalled, the slow green of the signal SAMPLE
Each ADC@1f 154 starts the conversion process by
. As further reminded, all ADC@1115
When the conversion process in step 4 is completed, output hDATRDY becomes
You can go high. This allows one-shot
device 256 (FIG. 6D) is triggered, and this device w256
, sequentially through the interface 30 (FIG. 2).
generates an output 5NDDAI- which is transmitted to sensor 34; tJ8NODAT), the processor 34 is now
Digital data converted from log format is
This means that the data is ready to be transmitted to the data processor 34.
You will know. Therefore, processor 34
- Appropriate decoder manual GRPIS via Face 30
TB (or GRP2STB. or GRP3STB) and ADDRl -ADDR
3, resulting in address decode logic circuit 190
(Fig. 6C) indicates that the incorrect converter A/D1. ...,
transmitted to processor 34 by A/D5 (Figure 6A).
raw digital data (any of BPY) to be
put out. FIG. 6E shows the DAC portion 30 of converter stage 56 of FIG.
0 is a detailed diagram of 0. Basically, the DAC section 300 includes latch circuits 302 and 3.
03. DAC device 306 and associated amplifier 308
include. In operation, latch circuits 302 and 303
Reset by input R8T given to each R terminal
be done. Next, the clock type given to that CK terminal
In response to human power 5TRO1'N-, latch circuit 302
and 303 each have a processor 34 (the
2), respectively, the digital data DTOA6-D
Accepts TOA9 and DTOAO-DTOA5 and
Chi. Any conventional latch circuit may be the latch circuit 302 of FIG. 6E.
and 303 may be used to realize
The switch circuits 302 and 303 are preferably Texas
74LS174 latch manufactured by Sturments
The device is good. DAC@11306 is connected to latch circuits 302 and 303.
The latch output Q from the latch circuit 302 operates together.
1-04 and latch output Q1 from latch circuit 303
-06 received. DAC 306 then digitally
Perform analog conversion to generate analog output signal ANALOL
JT, which is provided to amplifier 308. amplification
The DAC device 308 outputs the ANALOtJT output of the DAC device 306.
Performs current-voltage conversion to obtain output voltage signal BIASN(N
-1,2,...,6)! Occurrence, ta1! Ic Figure 5
As described above, the voltage is applied to the bias circuit 46' of
It is. Any conventional digital-to-analog converter is a DAC@
11306, but DA
C@Hitomi 306 is preferably an analog from Massachusetts.
AD561J converter manufactured by Google Devices
@Xi is good. Therefore, the DAC 306 has a supply voltage V
CC and ■εE are provided, +5 and -1 respectively.
It is 5 volts. Gain of output of DAC@device 3 and device 6
Bias is applied to potentiometers P1 and P4 respectively.
Therefore, it is set from outside. Finally, any conventional operational amplifier is amplifier 3 of FIG. 6E.
08, the amplifier 30
8 is preferably a Massachusetts analog device
A good choice is the UA741 amplifier manufactured by. Therefore
Thus, amplifier 308 supplies +15 volts and -15 volts.
Supply voltage is applied. Analog output ANALOUT is
is applied to terminal 2 of amplifier 308, but its terminal 3 is connected.
It is connected to ground via earth resistor R1. Furthermore, Poten
A signal to the DAC device 1306 via the meter P1.
Apart from being connected to a feedback configuration, the amplifier 13
The output of 08 is also connected via feedback capacitor C5.
A feedback connection is made to that terminal 2 input. At the top of the bale
,amplification! 1308 has bypass capacitors C6 and C
7 is provided. FIG. 6E and related descriptions show a pair of latch circuits 302 and
and 303.1 DAC@ll! 306 and 11
DAC circuit 300 as consisting of an amplifier 3308 of 1
As explained above, DAC times 1!1300 is preferably added
pair of latching circuits, additional AC equipment, and
May include additional amplifiers, so dual channel
gives the file output. In the preferred configuration, the output B IASN (N-1,3°
5) is the odd numbered part of ttJW1 amplifier-network 24.
Perform the bias adjustment of the preamplifier and the other DAC circuit 1.
The output of the second part of 300 B iAsM (M-2,4
, 6> are the even numbered preamps of the preamplifier network 24.
Service the amplifier. In summary, the processor 34 (FIG. 2) uses the latch circuit 30
2 and 303 to DAC device 1306.
Give the message @DTOAO・-DTOA9 (Figure 6F)
, the DAC device 306 performs analog conversion.
be exposed. The resulting analog output ANALOUT is amplified!
After current-to-voltage conversion at 30B, the output voltage signal BIA
Give SN. As explained above, in the preferred embodiment, the output BIA
SN (N-1, 3, 5) is the preamplifier network 24 (N-1, 3, 5)
Bias of odd numbered preamplifiers in Figure 2)
while adjusting the additional output signal BIASM(M-2,
4, 6) adjust the bias of the even numbered front 1 amplifier.
Arrange. FIG. 7A shows an overview of the motor control device 52 of the CEOG system.
This is a schematic diagram. The motor control 61181F52 is basically a linear motor.
control device 3201 dynamic braking relay 3221 rotation speed (
motor speed) buffer 324. Brake command manual
Ilsafe) circuit 32615 and chair interlock circuit
328. In operation, linear servo control [1@1f320 is controlled
provided by panel 54 (FIG. 2), the operator
control signal sourced to logic section 62 as a result of data selection.
Receive MTR8PD. Linear servo @11320
Also, there is a good luck tachometer 51 on the motor 50 (Figure 2).
It receives the tachometer input signal TACHIN from the
It shows the actual speed of the motor 50. Then,
The near servo controller 320 is connected to the actual motor in a conventional manner.
motor speed (TACHIN) and desired motor speed It (MT
R3PD) and the result of the comparison.
As, the control l@w320 sets the appropriate motor control current (L
Generates OADLO/LOAOH signal. Motor II
JIII* is the speed of the motor 50 and therefore the chair
Increasing or decreasing the rotational speed of 8 (Figure 2)
Therefore, the dynamic braking relay is operated so that its operating speed is controlled by IQ.
322 to the motor 50. Tachometer input to linear servo control device 320
Power signal @TACHI N also goes to the rotation speed buffer 324
The analog signal TACH2 is given from this buffer.
, subsequent digital conversion and interface 30
converter stage 56 (
2 and 6A) to the ADC section 56'.
. In this way, the processor 34
remain informed of the actual speed of. rotation speed buff
The driver 324 is a conventional
It may also be a breadth amplifier. Linear servo IIJ Goso w320 also has its terminal 4 and
and 6, the respective brake command signals BRK6 and B
After receiving RK8, these brake command signals are sent to fail control.
326. linear servo
Control 1@l1f320 is the brake operation amount control device 32
The conventional method that forces the motor control current from 0 to 0
According to the brake command input signals BRK6 and BRK8,
answer. In the preferred embodiment, input signals BRK6 and BR
K8 is the output of fail-safe circuit 326, and this circuit
The line 326 is the input BRK from the control panel 54 (FIG. 2).
I and RELBRK. Figure 7B is a detail of the 7-way il-safe circuit 326 in Figure 7A.
It is a diagram. The input signal BRK1 is input via the control panel 54.
received from the logic section 62 (Fig. 2) and is always at a high level.
voltage (e.g. +5 volts), so
Lenoid 362 is not energized and switch 364 is normally
is closed to. This allows the control device 320 (the
7A) is zero at its LOADLO/LOADH output.
unpaired. However, if RELBRK goes low, the solenoid
The door 362 is energized, the normally closed switch 364 opens, and the linear
For Aservo IIJIIl system ■32o (Fig. 7A)
Linear sensor by Oka circuit human power BRK6 and BRK8
The motor controller f320 determines the actual motor speed (TACHI
N) to the set that matches the desired motor speed (MTR8PD).
Adjust the speed of the motor 5°. FIG. 7C shows the 7AK chair interlock circuit 328.
It is a detailed view. Basically, chair interlock circuit 3
28 is a resistor 330. Transient diode 332 and soleno
1 in the id, and these are configured as shown in Figure 7C.
AC power switch 338 and
and 340 (FIG. 7A), and the chair 8
(Fig. 2)
ing. In operation, energization of switch S2 (control panel in FIG.
Regarding the operator control selection of 54, as shown below.
The chair motor is placed on the "on" switch (by the switch)
A positive DC voltage is applied to the solenoid 1 through resistor 330.
The AC power switch 3 is turned on and the solenoid 1 is set to the closed position 1.
38 and 340 and therefore ACIII
to the servo control unit 320 (Figure 7A). but
However, as noted, chair interlock circuit 3
As a result of the operation 28, the system placed on the chair 8 in FIG.
solenoid K 1 unless seat belt 334 is connected.
' is not energized and therefore between the positive electronic voltage and ground
The circuit is closed. In this way, chair 8 has safety characteristics.
Equipped with servo control @113
20 and therefore ACIIIN to motor 50
Unless the subject sitting in child 8 fastens the seat belt 334.
will be prevented. The motor control device 152 further detects position 1 11336.
This circuit 336 includes, in the actual example, chair 8 (seventh
Figure A). In particular, chair 8 has voltage + PO3L
Reflects the light received from the lamp 352 driven by the IT.
A reflective plate 350 is provided which emits light.
The reflected light generates 1 information PO8DET about the chair.
This information is sent to the photodetector 354
through the controller 52 and control panel 54 (FIG. 2).
Then, the logic section 62 is reached. Signal PO3DET indicates that chair 8
be at a 90 degree angle to the right of its normal position
shows. The motor controller 52 (FIG. 7A) also has a start limit.
switch 356 (normally open);
is placed on chair 8 (Figure 7A) in the actual example.
Ru. When the start limit switch 356 is opened, the signal
Allow STRLIM to go high. however
, line STRC0M indicates a ground connection, so
When the tar limit switch 356 closes, STRLI
M becomes O-, and this low state causes I control panel 54
(FIG. 2) to the logic section 62. Operator reset the system as seen below
When the start limit switch 356 opens, the
chair 8, as indicated by the STRLIM signal of
automatically moves to its normal position under the system.
and the limit switch 356 closes in that position.
reach when. Figure 7D is a detailed diagram of the dynamic braking relay 322 in Figure 7A.
be. The dynamic braking relay circuit 322 is basically a relay.
switches 370 and 372. Resistor 374 connected in series
, drive solenoid 376 and transient diode 378.
include. In operation, relay switches 370t3 and 372
Control @W320 (7) LOADLO/LOADHII4
1111m! Signal to t-50 (IFI7A diagram)
Usually in a downward position to allow passage. Input + BRAK
E is maintained at a positive voltage (high) level and the relay is switched on.
Switches 370 and 372 normally remain in the lower position. deer
However, once BRAKE goes low, the solenoid
376 is activated, causing switches 370 and 372 to move upward.
Force into position. This causes the control current signal LOADLO/LOADH
Not only is the application of I to the motor 50 prevented, but the
via the short connection established at switches 370 and 372.
By doing so, the input terminal is shorted to the motor 50.
A dynamic braking effect is achieved. Figure 8 is an illustration of the relay panel 20 of the CEOG system.
It is. Generally, relay panel 20 includes control panel 54 and logic
The various input l1IIll signals from section 62 (FIG. 2) are
the light source 12.1114, and in response the light source 12.1114, the shutter
motor 66, visual motion device w16 (this includes motor 74 and
74' and stripe cage 76), flashing light
The operation of the flasher motor 68 and the flasher 70 is controlled. Sara
, the relay panel 20 receives the feedback signal from the mirror 14.
(XBACK and YBACK) and
A feedback signal is sent to the logic section via the control panel 54.
62, and in this logic section 62,
, the cylindrical shape of inspection station 4! ! 18 (Fig. 1)
Compensation for distortion of the light source projection is provided. The relay panel 20 accepts various DC voltage inputs (+12 volts).
+15 volts) and AC input (110 volts)
). The AC input to the relay panel 20 is a laser
12 (Figure 2) to give ACIII.
Just do it. 12 volt DC input is striped
Input to lamp 400 illuminating cage 76 (FIG. 2)
(LITEl and LITE2), the relay switch
through channels 402 and 404 and resistor 406.
It will be done. In particular, relay switches 4.02 and 404
Normally located at position 1, LITEON (received from logic section 62)
) is low, solenoid 408 closes the
Driven to prostitution. On the other hand, in response to LITEON going high
In response, solenoid 408 turns off and the switch
402 and 404 return to the normally open position and the DC power is turned on.
is prevented from being supplied to the pool 400. relay panel 20
is a connector with a positive terminal connected to the power input +RELAY.
Note that a capacitor 412 is included. Capacitor 412 is connected to the +RELAY input, e.g.
Acts as a noise prevention filter for the positive voltage of the current. Further referring to FIG. 8, the relay panel 20
Input TRMTRO4 from logic section 62 in the figure is high.
Switches 422 and 424 remain in the normally open position for as long as
include. However, the signal going low and therefore
Turn on the tripe cage motor 74.
The switch is activated by solenoid 420 in response to a command signal.
switches 422 and 424 are closed, thus +12
Determine the path for the bolt input and its return path, respectively.
shall be stipulated. As long as TRMTRDN from logic 62 remains high
switches 416 and 418, which are always in the upper position.
Includes the power input path previously described, so +12 volts and
and its ll511 are input terminals A of the motor 74, respectively.
and given to B. This power input to motor 74 is
Raising the stripe cage 76 of the visual motor device 16
, or maintain it in an elevated position. However, lowering the stripe cage 76 is the first step.
Operate as described below with reference to Figure 9A.
When commanded by the
goes low and switches 416 and 418 close the solenoids.
414 in the upward direction 1. This is DC input
reverses the polarity of +12 volts and its return.
are applied to terminals B and A of motor 74, respectively.
. Therefore, the motor 74 is the stimulator of the visual motion @1116.
It operates in the opposite direction to lower the lie cage 76. Further, the motor 74 has a stripe cage 76 thereon.
When raised to its lower limit or lowered to its lower limit, it
Status output signal @L IMLJPOK or LIMDN
Generate OK. The relay panel 20 is also flashed by the motor 68! 17
Switches and solenos for controlling 0 up and down
Contains the configuration of the id. In particular, switches 428 and 430
is the input signal FLM-R applied to the solenoid 432.
As long as ON remains high, it remains at the normal upward position of 1,
[Operator to maintain motor 68 in off-J condition.]
Show your side's wishes. In fact, switches 428 and 430
, when in the upward position, the power input terminal of Mo968
However, the operator for turning on motor 68 creates a short circuit.
In response to the data command, FLVTRON goes low and then
As a result, switches 428 and 432 are placed in the downward position.
energizing the motor 68 to terminals A, B and C.
Establish the power input terminal. The motor 68 is then switched on.
Raise or lower the flash 1170 according to the position of the switch 432
The upper position causes the end of the motor 68 to
A positive voltage is applied to child A, thus lowering the flasher 70.
and by the lowest position of switch 432,
A positive voltage is applied to terminal B of the motor 68, and a flash! I70
to rise. In particular, the input FLSHDWN is
Stays high for as long as 0 rise is desired and switches
434 is therefore at the lowest position. On the contrary, F.L.
When SHDWN goes to 0-, solenoid 436 goes to the top.
the switch 434 to the position and the motor 68
flash device 70 is lowered (of course, relay 432
is also driven). The relay panel 20 in FIG. 8 is the control panel 54 (FIG. 2).
People from receive signals -CGMTR and +00MTR.
, and they are connected to the stripe cable by motor 74'.
For the purpose of controlling the rotational speed of the motor 74-
supply to Relay panel 20 also receives input -5H from control panel 54.
UT and +5HLIT, and
For the purpose of opening and closing the shutter 66 in response to
66 (FIG. 2). Additionally, relay panel 20 provides DC power to mirror 14.
along with an eye driving the mirror in the respective X and Y directions.
received from the logic section 62 via the control panel 54.
output signal XDRIVE[:(7YDRIVEf,
Give to a114. The relay panel 20 is also connected to the gorge 14.
, receives X and Y positions, signals XBACK, YBACK.
These position signals are transmitted via the interface 30.
Generates posx and PO8Y status inputs to processor 34
is provided via the control panel 54 to the logic section 62 in order to
It will be done. Regarding the control panel 54 of FIG. 2, FIGS. 98 to 9E
This will be explained in more detail with reference to the drawings. The control panel 54 (FIG. 2) basically serves two purposes.
Now. First, as a junction box, it connects power through the system.
Controls and states that are distributed and passed through the CEOG system
used to act as a common distribution point for most of the signal.
I can stay. Second, it performs the normal functions of the control panel.
not visible, the operator can use the switches and display
indicators allow you to interact with the system.
Ru. In a preferred embodiment, the former function is that of a junction box.
Functionality is the function of complex components that pass through systems between various functional units.
For those with multiple cables, each functional unit
1 (e.g. seen in Figure 2) to the control panel.
This is done by having several cables. Figure 9A shows the A-bench of the control panel 54 of the CEOG system.
FIG. Generally, operator controls 450 of control panel 54 include multiple
Several display indicators (O8) and a switch (S)
, and an adjustment knob connected to the potentiometer (P).
nothing. In addition, various display indicators, switches and
The adjustment knobs are for power, chair side L stripe cage movement, and flash.
WI for optical device operation, light source (laser) and mirror operation
It can be divided into N different categories. The operator control unit 450 switches the ACII moat switch S,
This switch turns on the system.
And AC! II is fed there. Application of AC power is
Indicated by the display indicator DSI. I mentioned earlier
Regarding Figure 2, Acmh is transferred to the CEOG system.
to apply, and especially to the electric current 1 [60
Various DC supply voltages are generated. In Figure 9A
Upon returning, operator control 450 displays various display indicators.
Data DS2.053. Including DS4 and DS5, various
DCwm! Supply 11 pressure, +5 pol, -15 volts, +
15 volt and +12 volt availability
shows. Operator control 450 also provides power to chair 8
A step for turning on motor 50 (FIG. 2) for
switch S2. Display indicator DS6 is motor 50
Indicates when is turned on. Furthermore, the desired speed of the motor 50 and therefore the chair
The desired rotational speed of 8 is set by the operator by adjusting knob P.
This knob P is selected by the motor control section W52.
(Fig. 2), and especially the near servo control section 320 (
Generates the signal MTR8PD given to FIG. 7A).
connected to a potentiometer (not shown). Operator control 450 in the IFIQA diagram also includes chair 8 (
(Fig. 2) for instantaneous stopping and starting, respectively.
switch S, and 84, and rcHAIRR
Display indicator 08 that indicates when there is an EADYJ state
Contains 7. Further, the operator control unit 450 is configured to use a reset switch S.
, this switch S is preferably manually reset
It is a momentary switch that includes a button. This reset button visually indicates that (1) the rotatable chair
8 (Figure 2) is rotated to its normal (reset) position.
and (2) SCAN (indicating I scan) and
and RE, C0RDING ON DISK (described later)
Clear a large number of computer picks such as
It is used for multiple purposes. The operator 111w section 450 also includes the stripe cage 7
6 (Figure 2) are raised and lowered respectively.
includes switches S and S8 for. Preferably, switches S7 and S8 are
In response to one press of buttons S and S8, respectively
To raise and lower the tripe cage 76
It is a one-shot flush button switch. Furthermore, A operator ill 111 part 450 is a striker.
A port for adjusting the rotation speed of the book cage 76 (Fig. 2).
Tensionometer (not shown), preferably 10 turns
It includes an adjustment knob P2 connected to a button thometer. The operator control 450 also controls the strike cage 76 (
Attach the linear light bulb 400 (Fig. 8) inside the
Includes an on-off switch S++ for energizing and de-energizing. The left direction and each of the rotations of the stripe cage 76
Position for specifying the right direction [iJ and “right” and rotation
``Off'' for turning off the rotatable strike cage 76.
A three-position switch S, 4 is provided having a "F" position.
. Operator control 450 is also in a "stripe ready" state.
Display indicator DS8 to indicate that the computer is
An indicator that flashes when data is being transferred to the disk.
Display indicator DS9 (RECORDI)
NG ON DISK) (thereby causing the system
An operator cannot accidentally fill a disk to full capacity.
) and flash device 70 (Fig. 2).
pushbutton switch SsS for raising and lowering;
Contains 0. Further, the operator control unit 450 controls the light source (laser) 1
2 (Fig. 12) and the forward horizontal velocity generated by
an adjustment knob P for controlling the vertical position, respectively; and
Contains P4. In particular, the adjustment knob P,
) to control the horizontal velocity of the light spot seen by
a potentiometer (not shown), preferably a 10-tap
connected to the potentiometer of the switch. Such a light source
The pot reflects the light from the laser 12 due to the movement of the laser 14.
As a result, the movement of the lock 14 is controlled by adjusting the knob P,
Potentiometer set by operator via
(not shown). Light seen by test subject 12
The vertical position of the spot is set by the adjustment knob P,
the laser 12 via a potentiometer (not shown).
Controlled by adjusting. Preferably, operator control 450 also includes a manual function switch.
This switch S includes a switch 812. 2 and lasers 12 and 114 (FIG. 2).
The position of the light spot generated by
AC square wave function, AC slope function, and AC sine wave function
can be controlled according to Operator control unit 450 controls light source 12 and l114 (first
``Set-up'' or ``Auto'' mode of operation (Figure 2)
Toggle switch for operator selection of SKI
include. i.e., specifying a "setup" mode of operation.
By doing so, the subject 2 controls the operator control section 45.
0. The previously described control means allow the physician to
According to the pattern selected by conducting the inspection
, receives light source stimulation. Conversely, you can specify an "auto" mode of operation.
By determining the
Optical stimulation controlled by computer (processor) 34
receive. The operator control unit 450 has an inspection warning indicator DS1.
0, and this indicator 0810 indicates that the system is
The inspection or adjustment to the system is carried out by the controller 62 (see Fig. 2).
) located in one of the parts L3' (Fig. 10G)
The switch allows the chair 8 (Figure 2) to be manually driven.
It is driven when it is carried out. as seen below
, other [inspection warning] states are due to the electromagnetic vibration of chair 8 (Figure 2).
chair 8 is normal (reset).
(g) Can be manually rotated away from position 1. Operator control 450 also controls the operation of the CEOG system.
Display indicator DS1 for indicating the "scanning Jt-code"
1 and the number of rotations at which chair 8 (Fig. 2) should be rotated is CE.
Automatically by the computer processor 34 of the OG system
switch S to indicate that
Contains 6. Figures 9B to 9E are the CEOG system control panel.
FIG. More specifically, FIG. 9B shows the control panel 54
On-off AC power source controlled by the operator control section 450
switch (S,) and various display indicators (DSI
, DS2. etc.), as well as a detailed diagram of the second
The power distribution functions performed by control panel 54 in the figure
FIG. As seen in Figure 9B,
By energizing switch S1, the input AC power
However, via the terminal board TBI, the connector terminal J103,
CE via Jllo (its terminals E, F and G) etc.
distributed to various parts of the OG system. As mentioned above
1!60 (Figure 2) is the AC power of the system.
In response to energization, the DC supply voltage, e.g.
, generates +5 volts, +12 volts, +15 volts, etc.
do. Further examination of Figure 9B shows that the condition 1rAc power on is
It is indicated by the display indicator DS1. Similarly, above
The generation of the DC supply voltage mentioned is indicated by the respective display indicator.
DS2 to DS5. Most importantly, what are the operating or status modes of the CEOG system?
What is displayed is indicated by the display indicator DS7 or DSlo.
is shown. In particular, according to the configuration shown in FIG. 9B,
The occurrence of the “Chair Ready” condition causes the display indicator to
One terminal of the CHA IRREADY
goes low and the display indicator
+15 volts DC by grounding one side of the DS7
Apply voltage to display indicator DS7, “Chair ready”
A visual indication of the status is provided. In a similar way, display
Each of the indicators DS8 to DSIO is
Ready, Record, and Inspection Alert operating status.
mode. Referring to FIG. 9C, circuit 456 includes logic section L3 (10th
(Fig. F) receives the input VTR3PD1 given by
This is the digital signal RLINFWD, RtJNBKD
and RIJNSLOW to an analog signal. times
Path 456 (Figure 9C) connects resistor 458 and potentiometer.
The resistance value of the meter 460 (this is the adjustment knob P, (Fig. 9A)
) by a voltage divider consisting of
, generates the output MTR8PD, and this output is as described above.
Operation of potentiometer 460 (Figure 9C)
The chair 8
In order to control the rotational speed of (Fig. 2),
52, especially its linear servo control button 320.
It is an analog signal. Circuit 462 shows switch S2, which has a
Therefore, the motor power for operating chair 8 (Fig. 2) is turned on.
is turned on. Display indicator DS6 is chair motor
When the motor is powered on, [indicates motor power on J]
Two output signals @MTRPWR and MTR3WON (Enoki description)
) is generated in the process. Circuit 464 of FIG. 9C includes switch S8, which
The switch S is a momentary switch, and when energized, the momentary
is moved from the "up" position to the "down" position,
Therefore, the grounding condition is changed from terminal 8TO opsw to terminal 5TO.
Transfer to PSW. With reference to section 12' of Figure 10D.
As shown below, terminals 5TOPSW and r
Set and reset the no-rebound switch 750, respectively.
Used to cut. Circuit 464 is selective at terminals 5TR3W and 5TR3W.
constructed in the same manner as switch SL to create a ground condition in
It includes a switch S4 that operates. Furthermore, in a similar manner,
Route 468 is selectively grounded at R3TSW and R3TSW.
bring about a condition. Circuit 470 includes a switch SG (toggle switch)
, this switch S6 is in its upward or closed position 1.
At the steep slope, there are some things to take before chair 8 (Fig. 2) is stopped.
This indicates that local control of the rotational speed is being performed. rotate
The number locally corresponds to the logic part L in FIG. 10B, which will be explained below.
Decoded thumbwheel switch located at l-
S2. -324 can be used by the operator to
specified. When not in the upward or open position, the switch
The switch S5 is connected to the computer for automatic control.
The control of the rotation speed of the child 8 (Fig. 2) is switched. Circuit 472 connects the pots associated with adjustment knob P2 (Figure 9A).
474, thereby determining the stripe speed.
+ between resistor 476 and potentiometer 474
Specified as a result of voltage division of a 15 volt input,
Analyzer for specifying the rotation speed of the leip cage 76 (Fig. 2)
Gives log output 5TRI PE5PD. Circuits 478 and 480 respectively switch S and
S6, which in response to energizing the cage 7
6 (FIG. 2) upper and lower circuits 482 are switches.
S+s, and this switch S, s is in its upper position.
When in position, manual function switch S, 2 (see Figure 9A)
according to the settings in the operator control section 450).
output 5ETU7 which requests 114 (Figure 2) to
give. Switch S's, in its lower position, automatically controls
1 for the computer processor 34 (FIG. 2)
14 -111 is switched. Circuit 484 is responsive to terminal 5CNLIT going low.
Display indicator D driven by 15 volt input
Includes S11. Terminal 5CNLIT is set up (1)
switch S's is "on" and (2) the computer
is scanning in the X direction, and (3) the computer is scanning in the Y direction.
When scanning in the direction 1, as explained in more detail below.
, the logic performed in part L9 (Figure 10L)
goes low as a result of the action. Circuits 486 and 488 respectively connect switches S9 and
These switches include circuits 464 and 4
It operates in the same manner as described above with respect to 66. circuit 48
Terminals UPFLSW, DWNFL at 6 and 488
SWf7) The output state is included in part L4' (Figure 101).
To set/reset the no-rebound switch
used. Circuit 490 includes a switch Sl+, which switch S
z in response to the bias, the stripe cage 76 (the
Figure 2) shows the "turn-on" of the light 400 (Figure 8).
Outputs the output signal 5TRPSW. Circuit 492 includes switch S+2, which allows
The scanning of the light source 12 (FIG. 2) is controlled by the mirror 14.
Three scanning functions may be selected for. In particular, the output signal
No. 5QLJAR, TRNGL and 5INE are square wave
, trigonometric (or slope function) and sinusoidal function.
Each is provided corresponding to a desired scan. [494 is the adjustment knob P, the pot corresponding to (Fig. 9A)
including a measurement meter 496, which allows the second sister 14 (second
The horizontal velocity shown in Figure) is selected. Circuit 494 output signal @03
REF, this signal is connected to voltage divider resistor 498 and
and 500, respectively.
l114 desired water in terms of degree and highest reference speed
Specify the flat scan speed. The circuit 502 is connected to a pot corresponding to the adjustment knob P (FIG. 9A).
A light source 504 is disclosed, which allows the light source to be
The vertical positioning of the beam from 12 is adjusted. That's it
As a result of such adjustment, the desired vertical position of the ray from light I[12
port so as to give an output signal VERTPO8 indicating the positioning.
Voltage division is performed by a tension meter 504. attention
What should be done later is the discussion of part L10 (Figure 10M).
As shown in , the potentiometer 504 is
Summation amplification of part L10 in parallel with the MOVY input from
acting in parallel with any other signal that is summed in the
, generates an output YDRIVE, thereby causing the light source 12 to
The desired vertical positioning of the rays is achieved. Returning to FIG. 9D, circuit 506 connects switch S14 (the
9A), and this switch allows you to
Leftward or rightward movement of the cage 76 (Fig. 2)
Or a stop occurs. Left side of Strive Cage 76
The direction motion corresponds to the output −〇GVTR, while the Strive
The rightward movement of the cage 76 corresponds to the output terminal 〇GMTR,
These two output signals are connected to the relay panel 20 (Figure 8).
and therefore to the motor 74';
As a result, under the control of motor 74'', the strike cage
76 (Fig. 2) leftward or rightward movement, respectively.
Let's do it. As seen from circuit 506 in FIG. 9D, switch Sr
< has [off 1st place -, which makes the strike case
Neither left nor right movement of the wheel 76 is specified. moreover
, as shown in FIG. 9D, the circuit 506 further includes a switch
S1. ', and this switch is connected to switch 814.
and to the “left” and “right” positions respectively.
In response to energizing switch SI4, the output LFTS
Generate W and RHTSW. Output LFTSW and
The RHTSW outputs the S signal to the logic section 62 (FIG. 2).
It is given as follows. Referring to FIG. 9E, further circuits 530 to 53
3 are shown, and these circuits provide various control l signals.
Used to convert to driver signal. In particular, the circuit
530 is signal line WLON (inspection warning light on) and CH
RDYON (chair ready on), display indicator DS
Signals that can flash to 10 and DS7 respectively
Convert to Circuit 531 is an adjustment called +RELAY.
This signal is shown in Figure 8.
As you may recall, the solenoid/liber mentioned earlier
relay panel to supply power to the relay switch combination.
20. The circuit 532 is an input signal RELBRK (release brake)
, LITEON <light on), FLYTPON (flash device mode)
>, FLSHDWN (flash down), T
RMTRON (stripe cage motor on), and
and TRMTRDN (stripe cage down).
into corresponding driver signals. Finally, the circuit 533 controls the adjustment knob Pz (Fig. 9A).
of potentiometer 474 (Figure 9C) associated with
Relay the input signal @S rRI PE5PD from “Wiper”.
- Output signal given to panel 20 (Fig. 8) + CGM
TR and −CGMTR, and therefore any
Rotate the stripe cage 76 (Fig. 2) at a speed of
The motor 74' is converted for this purpose. The latter is transistor 5
35 through a resistor 536 to the base of 35.
By input TRNCG (rotate cage) circuit 53
Achieved by 3, Arrogant μ Stripe Cage Motor 7
4' (Figure 8) to the ground to turn on 100V
Pull the TR. In this regard, reference is made to various other Figures 9B-9E.
The operation of the operator control section 45o (9th A@I)
A brief explanation of the use of the data is appropriate. In particular, operator system
A brief explanation of the use of Gobe 450 is EOG and VER inspection
given for both. To perform EOG and VER inspections, the operator must
You can take the following actions: (1) Switch of operator control unit 450 (Figure 9A)
Power the CEOG system by driving the
, and thus as discussed above with respect to Figure 9B.
, AC power and seeds to various parts of the CE OG system.
DC supply voltage for each. (2) The operator then presses switch S, 8 (Fig. 9A)
), thereby driving circuit 482 (Figure 9C).
generates a signal SETLIP. In this respect,
Shutter 66 (FIG. 2) is opened and light is emitted with respect to mirror 14.
Subject 2 to a light stimulus generated by a source (laser) 12
to face. In the "Set-up" mode of operation, the stirrup
14 is an A verator control unit 450 (FIG. 9A, and
(See also circuit 492 in Figure C)
The specific manual that the operator previously specified by using
Scan in the X direction according to the function. Furthermore, the Y position of the iron is
Adjustment knob P, (and
and potentiometer circuit 502) and a computer programmer.
In combination with the MOVY command from sensor 34 (Fig. 2),
It is determined that The scanning speed of the mirror 14 (Fig. 2) is controlled by the adjustment knob.
P, is set with respect to the potentiometer circuit 494.
and preferably from 0.8 seconds to
Give a scan cycle unit of 10 seconds. "scan" mode
During operation, this operating mode is indicated by the display indicator DS1
1 (see circuit 484 in Figure 9C). (3) As mentioned above, switch S's is]
switch and therefore the subsequent toggle of switch S's
will result in an "auto" scanning mode. As a result of entering this mode of operation, scanning is controlled by the computer.
It is carried out according to the following. Furthermore, computer processor 3
4 completely determines the scanning pattern, speed, etc. that subject 2 receives.
and can be programmed to exclusively control
Wear. Alternatively, what scanning function can be manually switched on?
The scan changes to a scan pattern depending on whether it is selected with
horizontal movement.
The horizontal speed is adjusted by operator control 450.
As set manually with knob P,
Proceed your computer so that it can be trained
gram (can be used as a further example)
P6 is normally used to simply indicate horizontal scanning speed.
However, which speed is set with adjustment knob P6?
Vertical scanning is done according to the
computer processor 34 can be programmed
. (4) The operator operates switch S.
One can reset the system with this switch
S, generates a signal R8TSW with reference to FIG. 9C, and this
The signal is received by the logic section 62 (Fig. 2) as shown below.
be rejected and processed. The CEOG system also performs other EOG tests.
For example, as follows:
An operator is required to control the rotatable chair 3 (Fig. flN1).
Tests can be performed using the data controller 450.
can. (1) Regarding EOG inspection-C As mentioned above,
The switch 81 supplies power to the system I\. (2) The chair motor drives switch S2.
Therefore, it is activated by the display indicator DS6.
will be displayed. As previously discussed, this causes circuit 46
2 (FIG. 9C) generates the signal MTRPWR. (3) The operator activates switch S.
to reset the system, which results in the system shown in Figure 9C.
via circuit 468 to logic section 62 (FIG. 2).
Generates R3TSW. At this point, the chair has its normal (reset) ready for rotation.
(cut) position and the “Chair Ready” status is displayed on the display.
DS7. (4) The operator uses terminal 44 (Fig. 2) to
For example, 1lll to the number of rotations to be performed by a chair!
This is explained below.
This will be explained in detail below. (5) By pressing switch S, the operator
This allows the chair to rotate at the specified number of rotations. (6) By pressing S, the operator
The chair can be stopped before reaching the rotation speed of
The CHAIRREADY light that blinks when the number of rotations is displayed is
This can be seen in indicator 087. (7) The operator activates switch S4.
to start the chair rotation again, and
The predetermined number of revolutions is completed. When the specified number of revolutions is completed,
CHAIRREA automatically stops and blinks
DY indicator can be seen in display indicator DS7
. (8) As explained in the arrogant CEOG system,
In response to further energizing switch S4,
If the direction of rotation is clockwise, then rotate counterclockwise.
It can be programmed to continue. 〈9) The dark side of operation, as mentioned above, the operator must inspect
A computer that requests a hard copy printout of the results.
Press the computer control button or
Typing a given character such as the character rRJ on the console of
memory IAw, and therefore more permanent.
For example, the test results are recorded on the disk 42 (Fig. 2).
be able to. (10) As explained in more detail below, the system
can be activated in the automatic reset J mode of operation.
, which allows the chair to rotate backwards in "slow mode"
The CEOG system is a limit switch.
”, which will return to its normal (reset) position.
The rotation of the chair is stopped at this time.
Ru. This will be explained in more detail below. (11) Finally, as further seen below, the
switch S6 before the chair 8 (Fig. 2) is automatically stopped.
``Local'' control of the number of revolutions passing through the engine.
giving the operator the choice of either 'control'. As you will recall from the previous discussion, a rotating chair
The number of revolutions through which
' (Figure 10B)
tch S2. -82. Locally by applying force to the finger
When conducting the test on subject 2, the operator's
The strip section 450 (FIG. 9A) is connected to the strip cage 76 (FIG. 9A).
(Fig. 2) can be used to control w i. Therefore, the one-shot button switch S8
Depending on the force, there is a striped Kusif 6! Ima
C is lowered. In this forest, if switch S++ is set to 4
If the switch 314 is energized to the “on” mode,
is set to the "left" or "right" position, the
In other words, if it is not set to the "O" position, the linear
Light bulb 400 (Figure 8) is on and striped.
Large 76 rotates as soon as it reaches its lowest position
Begin to. At any time in this inspection cabinet, switch S?
The light bulb 400 is turned off by energizing the
Not only that, the rotation of the strike cage 76 automatically stops.
, and the stripe cage 76 is 1 to its uppermost position.
Culmmed. As mentioned above, the rotational speed l of the stripe cage 76
l1IIll is the adjustment knob P and the circuit 472 (9th C
This is achieved by the potency potentiometer 474 in Figure).
. The display indicator DS8 indicates the “stripe ready” state.
show. Display indicator DS9 is RECORDING
This is the ON DISK indicator.
The test data of the subject 2 is stored on the disk 42 (No.
(Figure 2).
Let it come out. Figures 10A to 10M are the logic of the CEOG system.
6 is a detailed logic block diagram and circuit diagram of the unit 62. FIG. Logic section 62 (FIG. 2) is the source of 3w, namely EOG.
Computer via interface 30 (FIG. 2)
processor 34, control panel (Fig. 9A) and related
The switch of the circuit (Figures 9B to 9E) and the CE
Other @learning or elements of the OG system (described below)
Receives electronic signals from. The logic section 62
processing all of the signals and the rest of the CEOG system.
Generates control and indicator signals that are distributed to
do. Logic section 62 includes a logic section 62 for purposes discussed below.
divided into parts L1 to L5 and L8 to Lll,
Each of them will now be considered in detail. FIGS. 10A and 10B show the logic section 62 (FIG. 2).
Detailed logic diagram of each of parts L1 and Ll-/II omitted
It is a diagram. Parts L1 and Ll- of logic section 62 are basically
The following four Noh performances are performed. (1) automatic system initialization for power-on 1; (2) system reset;
Counter and comparator operation for. Referring to Figures 9A and 10A, if the system
When turned on by the energization of switch S, various D
C and AC voltages are allowed to flow through the system.
Ru. In response to receiving the DC input, portion L1 (FIG. 10A)
) is triggered to output INIT.
It will be done. The latter output R8T and (inverter 612
performs an OR operation to produce an output R3T
Provided to AND gate 608. NAND gate 60
The output of 8 is given to a one-shot device 616, which
The w616 uses NAN as its Q output as an enable input.
Since it is given to D gate 60B, R3T (R8T)
The output is a square wave pulse with a duration of only 0.1 seconds.
ensure that In other words, for example, N, ZARR8
If T or ZERO goes low, NAND gate 626
Like, one by receiving high signal from
The shot device 1616 allows the RST output to turn on immediately.
Avoid being exposed. This can be seen from the discussion below.
be clearly understood. Additionally, NAND gate 608 has a high R8TSW input.
No-rebound switch 600 (connected as shown)
set the NAND gates 602 and 604)
The output R8T is output when the high level R3
The TSW input is the switch of operator control section 450 (Figure 9A).
(
circuit 46B (see diagram IFj9C). At the very end, both NAND gates 608 are "high".
Inputs ZERO and NEARR3T that are “on”
(received by NAND gate 626) and
and outputs an R8T output. Input ZERO is
given by decoder 664 of division 1' (Figure 10B).
This is the output that is previously set as
The chair was rotated in the opposite direction by a set number of rotations.
Show that. In a related way, the input NEARR8T is partially
2' (Figure 10D), which can be seen below.
The chair is in the “reverse rotation” mode of movement so that
This is a control signal indicating that. Konoyouni, NAND game 1-608 OJ: (F626
As a result of the operation (Figure 10A), the CEOG system
The R8T output, which indicates a reset, will count down to zero.
The chair rotates in the opposite direction for a predetermined number of rotations so that the
will be output whenever it is done. Still referring to FIG. 10A, circuit 632 is a "blink"
Various selected display indicators to achieve the effect
The oscillator output BLINK applied to the
timer 634. For example, inspection warning indicator DS10 (Figure 9A)
connects the output BLINK of circuit 632 (Figure 10A) to it.
Can be made to flicker by giving
. Additionally, circuit 632 has inputs TEST1J5 and TOo
NAND gate 638 with TOR type operation on HI
including the output TWLON (Test warning light on)
is either input TEST1 or TOOHl, input B
Issued when LINK exists. as shown below
, TESTI shall be used whenever specific test functions are performed.
For example, if the chair is on the switch in section L3 (Figure 10F).
Rotate by energizing CH SA and 3B.
Goes "high" when it should be manually controlled. Sara
Input TOOHI is set by the operator.
when the number of rotations the chair should rotate exceeds the permissible value.
is always generated by the part 1' (Fig. 10B).
Ru. Referring to part Ll' of FIG. 10B, the chair 8 is rotated.
The number of revolutions to be determined is the computer console or terminal 44.
(Fig. 2) After the computer control,
or from switch 821 to S24 (Fig. 108)
By presetting the thumbwheel switch
This means that it can be specified by local control.
Let us remember that. In this way, the multiplexer (M
UX) 650 is bit 1 from processor 34 (Figure 2)
- generated by a computer as 4, or
Locally designated circuits via switches 821 324
Receive and multi-layer transfer information. The multilayered output of multiplexer 650 is connected to latch circuit 652.
, and the latch circuit 652 outputs the latched output.
It is applied to the comparator circuit 654 AO-A3. The circuit 656 in portion L1- of FIG. 10B provides chair position information.
in response to input PO3DET representing
Via the parator 658 and NAND gate t-660
, a reflective strip 350 (FIG. 7A) on the chair
When is Lp detected by photodetector 354?
also generates an output poscLK. Output PO8CLK is
Apply an O input to the GK terminal of the counter 662, and
The counter 662 is, for example, the number of rotations of the chair during clockwise rotation.
and for example counterclockwise of the chair.
To count down the number of revolutions of the chair during rotation.
It is a 7-up down counter. The output QA-Qo of the counter 662 controls the human power of BO-83.
to the comparator 654. In this way, the digital comparator 654 is
Compare the desired number of rotations with the actual number of rotations of the chair, and
If they match, comparator 654 outputs MATCH.
Occur. Counter 662 is part L of FIG. 10D, discussed below.
The argument given by Go flip 7D tube 752 of 2
Activated for counting by physical input GO
. The counter 662 indicates a system reset.
will be reset when this occurs. counter 662
The up or down run 1- is part L2 of FIG.
Up/down flip 70 given by 772
is determined by the logical input DOWN. counter
The output Q-Qo of 662 is given to decoder 664, and the complete
Complete chair cycle, i.e. clockwise followed by counterclockwise
When rotating in the direction, a ZERO output is output. ZERO output
has already been discussed with respect to circuit 618 (Figure 10A). Returning to circuit 656 (Figure 10B), comparator 65
The output of 8 is monostable! 1666 and this device f
! 666 produces a 1 output to NAND gate 660;
Therefore, the output PO8CLK is the output from the comparator rotor 58.
Either the force and/or the output from the monostable wheel load 666
response has a minimum duration of time. The circuit 668 of part L1- is a NAND gate 670.67
2 and 674, and inverters 676 and 67
8, and they are subject to one of the following two states:
and provides a clock input to the rarity circuit 652. (1) The rotation speed of the chair is
locally controlled as specified by closing
Latching of data by the latch circuit 652 when the data should be
is controlled by the R8T (reset) signal. this
R8Ta! The number is connected to switch s6 via inverter 676.
to the AND gate 674 which is activated by the input of
Therefore, the OR gate 672 and the inverter
678 to the CLK input of latch 652.
It will be done. (2) The rotation speed of the chair can be changed by opening switch s6.
When to be computer controlled as specified by
The data is latched by the latch circuit 652 using the switch.
AN enabled by enable input from switch s6
D gate 670. OR gate 672 and inverter 6
5TROBX (computer
IIIJ by the strobe signal generated by
Be @ed. Switch SG is connected to operator l1IIp section 45o (9th A
It is a toggle switch specified correspondingly to
Let's be remembered. Ground by closing the switch
A connection is made thereby to AND gate 670.
produces a low input, disabling the button-controlled latch.
Enabled and data reset l1lIllll
high input to enable AND gate 674 for
Force arises. Conversely, by opening switch Ss,
Computer controlled by giving +5 volts (high) input
Activate AND gate 670 to latch the
Disable ND gate 674 and reset l1illll
Release the latch that was applied. The series described above with reference to circuit 656 of FIG.
Input PO-3DET indicates that the light is reflected from chair 8 (Figure 7A).
The alarm generated when detected from the sexual strip 350
It is an analog signal. Such light is detected by comparator 658
(10th BI!l) and its negative input is detected by
Adjusted by bell detection potentiometer P2. light
When ? is detected, the output of comparator 658 is ? I reflected
The output PO8CLK from the NAND gate 660
The comparator 658 is mounted as a one-piece so that it can be held in place.
f1666 (preferably 0.25 second one shot hold)
(with a duration period). In other words, NANO game
The output 660 is a comparator 658 and a one-shot device 6.
An OR operation is performed at the output section with 66. In this way, the circuit
656 is the maximum that the output poscLK can accept.
of short duration and the output PO8CLK is
A counter for counting chair rotations as a lock input.
662 and as further inputs:
The part to be discussed is given to 2' (1st OD diagram).
Assure. Figure 10C, Figure 10D(1) and Figure 10E are
Still other parts 12°L2- and L of the logic section 62 in the figure.
Figure 1100(2) is a detailed view of each of Figure 1100(1) and the movement of 2'.
FIG. Basically, portions L2.12' and L2'' are the input signal
5TR3W (start switch), 5TOPSW <
Stop switch>, R8T (Risechi), and MAT
CI-1 (If the count of chair rotations matches a predetermined value)
). Portions 12.12' and L2'' are in the appropriate sequence.
To perform various logic functions such as providing the following signals:
Give the logic circuit of Such a signal is CHRDYO
N (chair preparation on), RUNIB (motor drive>, R
ELBRK (brake release), FWD (front*”), R3
LOW (low speed drive), and DOWN < countdown
). Other inputs, ′output signals as shown below.
signals are also received/given. With particular reference to portion L2 of FIG.
The flop W (cross-coupled NAND gate) is as follows.
Sea urchins are provided. (1) When the chair motor is driving, the inverter 7
Runflip 70 provides output RUNIB via 01
Tsubu (NAND gate 700). Such output is given to part L3' (10th G!!!>
It will be done. Output of flip 70 tube 700 tJN is
When the motor is driving (indicated by RUNIB)
) or when manual rotation of the chair is indicated in the first
Input to give bRELBRK (brake release)
-M A N B K RL, NAND gate 702
is OR-processed. (2) “High” when the chair is being driven in the forward direction
or r when the chair is being driven in the opposite direction.
Order of medium force FWD that is o-J/Reverse flip 70 Tsubu
(NAND gate 7o4). (3) “Low” when the chair is moving at low speed
Low-speed drive flip-flop that outputs R3LOW<NA
NO gate 706). Output from NAND gate 704
The power FWD is connected to the M706 through the inverter 708.
is shown by giving it to the most NAND gate of
The chair is only driven slowly in the opposite direction, as shown
That should be noted. Furthermore, the device 17
Note also that 06 is set by input R3T.
system should be
The set causes the chair to rotate slowly in the opposite direction, which
Eyes to center the chair in its normal (reset) position
done at the target. Signal R3T is generated by CEOG system Noricera 1~
Let us remember that. Refer to Figure 10C.
Input R3T is connected to flip 7 via inverter 710.
It is given to the 0 knob 712 and resets the 0 knob 712.
set. As a result, - limit switch 356
When found, it goes low and the NAND gate 714 goes out.
Gives power CHRDYON. CHRDYON is also a signal
HLDBLNK (This is related to Figure 100(1) below)
Discuss the held flip-flop generated by
signal) goes low.
I want to be noticed. Furthermore, the signal CHRDYON <chair
READY ON> is applied to circuit 530 (FIG. 9E).
will be remembered. In that circuit, it is the output CH
It is converted to RD Y ON and its appearance! ] will be displayed sequentially.
In response to energizing indicator 087 (Figure 9B),
The indicator indicates the "chair ready" condition. With further reference to Figure 10C, resetting the system
By doing so, the three MRs are connected via the inverter 710.
Check mechanism ready 7 lip-flop as clock input
716 and from there to NAND gate 718
give the output. Start limit for chair 8 (Figure 7A)
When switch 356 opens (this means the chair returns to its normal (
(reset) position), signal STRLIM
is high (+5 volts), and the voltage of inverter 720 is high (+5 volts).
Output STRLIM is low, resulting in
722 (this is the Q output and S output of the flip 70 tube 716)
Performs an open AND operation with TRLIM) output is high
become. At the same time, the output of NANO gate 718 is a high input.
Power (ST'RLIM and Noritubu Norotubu 716's Q
) there, as a result, the driving flip-flop 700
``Low'' output applied to ``1 set'' terminal ST A
I have RTLOOK in my possession. This is chair 8 (Figure 7A)
indicates that is searching for its normal (reset) position
. In fact, R8T can perform forward/reverse flip as input
70 to the knob 704, and therefore its output FWD
becomes “low” indicating reverse rotation mode. At the same time, signal R
3T to set input of low speed drive flip 70 knob 706
is given, which causes output R8LOW to go low and the chair
Indicates slow rotation of the child. Thus, in summary, depending on the reset operating mode (
Chair 8 (7th)
Figure A) rotates at low speed in the opposite direction. When the normal (reset) position is reached, the start limit switch
The switch hits 356, STRLIM goes low and ST
RLIM goes high. As a result, NAND gate 71
8 is turned off, the NAND game 722 goes low, and
Therefore, the drive flip 70 knob 700 is reset. Therefore, the output πn of the flipflora 1700 is high.
and output RLINIB is 0- (this is motor 8
(Figure 7B) is turned off), and the other ratio hRELB
RK becomes low and "C brake operation is performed for 7-50"
and therefore stop the rotation of the chair 8.
As shown, fail-safe circuit 326 (FIGS. 7A and 1
178), linear servo control device 320 and power generation @
The recommended relay 322 is energized. Furthermore, SchoRL IM from inverter 720 and
When the Q output of the flip 70 knob 716 goes low, the NA
The resulting high output of ND gate 722 flips
Set flop 712 and MECRDY turns on
. Due to its arrogance, it is necessary to reset the flip-flop 712.
When necessary, this starts the rotation of chair 8 (Fig. 1).
signal GOB (from Figure 10D)
, this signal GOB is at the bottom of Noritsubu 70 and Tsubu 700.
ANDed with RUN from the NAND gate,
Therefore, the driving flip-flop 700 is a mechanism preparatory flip-flop.
flop 712 is turned on before being turned off
ensure that This means that the MECRDYXNAND game
via port 752 (to help generate the first GOB)
(See Figure 10D(1)). Resetting the check mechanism preparation flip-flop 716 (
R) input to NAND gate 728 via resistor 730
The fact that they are connected is attracting even more attention (11 people)
is grounded by grounding capacitor 732). child
, the NAND gates 728 are
Then perform an AND operation. Especially when RLJN goes high
and the output of the inverter 732 is NA
When going high as a result of ND gate 722, Katsura
In addition, the Q output MECRDY of the flip 70 knob 712 is
When going high, check mechanism rate -7 lip 7 O knob 7
16 is reset, resulting in NAND gate 718 and
and 722 are removed, respectively. I reset the system as explained above like this
As a result, the normal (reset) position is reached and chair 8 (Fig. 7A) is reached.
) is detected by energizing the start limit switch 356.
The chair rotates slowly in reverse until it is ejected. Referring now to Figure 10D<1), start the rotation of the chair.
Explain the operation. Start switch S4 (Fig. 9A
and FIG. 9C) to energize signal 5TR3W (described above).
) occurred and according to part L2- of Figure 10D(1).
This signal received by the flip switch has no bounce.
70 knob device) Set 750. NAND gate 7
52 is the input from the flip 70 knob 712 (Fig. 10C).
AND operation on the force MECRDY (mechanism chair preparation)
and forward/reverse flip-flop 704 (Fig. 100).
) emits an output XYZ that is given as a “reset” input to
live. This shows that the flip 70 knob 704 is in the direction of the chair.
Ensure that the output FWD corresponding to the direction operation is generated.
. Furthermore, NANO games 1 to 754 are XYZ and NAND
Yet another (7) input (
0RII between S rR3W-HOLD) and (7)! 1
This output generates the C output GO8 which performs the clock operation.
Turn on GO flip 70 knob 758 as an input. The generation of output GO8 drives flip-flop 700.
(Figure 10C) is also turned on. When chair 8 (Figure 2) starts rotating, the number of rotations reaches 108.
It is counted by the device shown in the figure, and the predetermined number of revolutions is counted.
When the output MATC)-4 is
generated by comparator 654 (Figure 10B). In that respect, NAND gate 762 performs an AND1 operation.
, input FWD, G. and revealed the existence of M8-VCH,
764 is set. Therefore, flip 70 tubes
Device 766 loads w76 on the next PO8CLK pulse.
Set by 4. To explain in more detail, the timing of FIG. 10D(2)
Referring to the figure, pulse PO3CLK is the first clock pulse.
The rotation of the chair is based on the 0tsuku pulse.
number is counted. In a preferred embodiment, the chair is
1/4 revolution before receiving the PO8CLK pulse.
It should be noted that the 10D(2)
In the figure, it is assumed that the rotation speed is preset to 3.
. After completing two and a quarter turns, i.e. the third
When full rotation begins, comparator output MATCH is generated.
Similarly, Noritub 70 and Tube 766 are the next PO8CLK pulse.
It is set upon reception of . 10D (1) See Figure 10D (2) of WJ13
Referring also to the Q output of the flip 70 knob 766 is
WAPO8CLK of a time period of, preferably 0.1 seconds.
The one-shot device 176 is configured to generate η output at the edge of the sliding door.
Activate 8. This output is specified as signal REVR3.
be done. The winner resets flip-flop 704
For 1llll/reverse flip-flop 704 (10th C
negative applied to the figure). pulse, which causes FWD to go low and further
A rotation of the chair 8 (FIG. 2) in the opposite direction occurs. Most commonly seen in the timing diagram in Figure 100(2).
uni, the positive edge of pulse REVR3 is flip 70.
Clock knob 770 to the “on” state, thereby
Generates force GOC. Accordingly, the output GOC goes low
, and this causes NAND gate 772 and inverter
The knob 70 knob 776 is set via the tab 774.
(see waveform NEARR8T in Figure 10D(2)).
(I want to be). The output NEARR8T is "
Indicates "reverse" operating mode. In this way, with reference to Figure 100(2), the chair is
When it rotates a little bit, it stops, and then it reverses to (mo) and starts rotating in the opposite direction. Therefore, the counter
662 (Figure 10B) is 3's pleasure (predetermined rotation)
value), the output MATCH is issued, but
However, at this time, the output FWD is low and the NAND gate
The output 762 therefore provides a low output. The reset input of flip-flop 766 is a NAND gate.
connected to the series connection of inverter 778 and inverter 780.
This NAND gate 778 has input REVR8 and
performs a dark OR operation of ``and input R''. This - formation
Accordingly, the flip 70 knob 766 is between the two stakes,
Straw (1) Generation of negative pulse ``REVR8'' or 2
) Reset by any of the occurrences of human power R8T.
will be played. The up/down flip flop 782 is
When the flip 70 knob 766 is first turned on, the flip
Set by the d- output of flip-flop 766,
Apply the power DOWN and turn down the counter 662 (Figure 10B).
Indicates the count operation mode. With reference to FIGS. 10A and 108, the counter 66
2 reaches zero count, decoder 664 outputs Z
ERO! put out. Q and others, NANO gate 626〈10th
Figure A) is A for input ZERO and NEARR8T.
ND operation and OR operation of NAND gate 608
As a result of the operation, the output R8T is changed according to the configuration of the lloA diagram.
Served. 10D (see timing diagram in Figure 2)
I want to be. As mentioned above, with respect to Figure 10A, this output
The force R3T is as a result of the operation of the one-shot device W616.
0.1 seconds! Continuing, this is the NA after the Nllff period.
NO gate 608 is deenergized. When R2H occurs, flip-flop 776 (10th
D (1) figure) is reset and the output NEARR3T is locked.
-becomes. In this way, the rotatable chair 8 (Fig. 2)
r Reverse J mode of operation is shown. Open signal REVR with reversed rotation of chair 8 (Fig. 2)
As a result of 3 going low, a "power stop" operation can be achieved.
. In particular, with reference to Figure 10D(1), the automatic stop switch
When closing the switch 784, ■■ When VR8 goes low, Yes.
At any time, 5TOP2 is connected to NAND gate 786 and
788. Output 5TOP2 is driven
Turn off flip-flop 700 and hold flip
Set 70 knob 790. Output HOLD is NAND
ANDed with BLINK at gate 792 and H
LDBLNK, which, as mentioned above, is CHR
To generate the DYON (chair ready on) indicator.
is applied to NAND gate 714 in FIG. 10C. Additionally, the HOLD output is provided to NAND gate 756.
The other input is the set output of flip-flop 750.
Upon receiving the force, this flip 7O knob 750 switches to the start switch.
It is set by the bias of the switch. In this way, the star
The reverse rotation of chair 8 (Fig. 2) is caused by the activation of the switch.
It is done. In addition to being stopped automatically, the chair 8 is of course also stopped at the traffic light 5.
Manually by energizing the stop switch that generates TOPSW
It can also be stopped automatically. This 5TOP8W signal
is the set input to flip-flop 794,
An output STb〒 is thereby generated. This output 5T
OP turns off the drive flip 70 knob 700 and turns off the chair.
Stop rotation. Finally, as mentioned above, manually rotate chair 8 for the purpose of reverse rotation.
When restarted, the drive knob 700
When turned on and immediately after, retaining flip 70 knob 79
0 (Result of automatic stop via 810P2)
) is now reset via the ffN input.
. Now referring to diagram lR10E, part L2'-1 is the operator
Switch S2 of the controller 450 (Fig. 9Δ) is energized.
As a result, the input MTR3WON is received from the circuit 462, and the
Receives input hRELBRK from circuit 532 (Figure 9E).
Pull. The brakes associated with chair 8 (Figure 1) are released.
MTR8WON and RELBRK
both must be high, which causes invert
The output of transistor Q1 goes high and it
and thus turns on transistor Q2.
Turn off. As a result, BRAKE becomes high and power generation is restricted.
The dynamic relay 322 (FIG. 9A) is released (deenergized). However, either MTR8WN or RELBRK
When either goes low, the output of NANO gate 800 goes high.
The output of the inverter 802 becomes low, and the output of the inverter 802 becomes low.
transistor Q1 is turned off and transistor Q2
is turned on. As a result, BRAKE becomes 〇-, and therefore the power generation is restricted.
Logic section 12''' (Figure 10E) also activates the manual brake circuit 322 (Figure 7A).
/off switch 804, this switch 804 is
In the downward position, the part L2''- is manually moved as described above.
to function properly. Conversely, switch 804
When in the up position, the brakes will not move the chair for manual positioning.
removed from child 8. In this case, the operator control section 45
0 (FIG. 9A), the inspection warning indicator DS10 is T
As a result of ES D1 going low (connected to ground), it turns on and
Become. 10F and 10G are the parts of the logic section 62 in FIG.
Detailed views of divider 3 and L3- are shown, respectively. Referring first to Figure 10G, part 3' is the input RUNI.
B (of the drive knob 70 knob 700 in Fig. 10D(1))
output) and TJF-WD (forward/reverse flow in Figure 10D(1))
The output h) of the flip-flop 704 is received. Part L3-
Switch SC manually rotates chair 8 (Figure 2).
Button switch driven by operator
It is. NAND gates 870 and 878 are
AND operation on the inputs to NAN
D gate 872 connects the outputs of gates 870 and 878 to
Perform R processing. In this way, there are two NAND gates 872.
(1) Manual mode of operation (MANMO)
Activation of switch SC in DE) or (2) operation
In the non-manual mode of l' dynamic flip-flop output R
Output is generated by either receiving tJNIB. NAND gates 880, 882 and 884 are similar
Therefore, NANO gate 882 has two stakes.
(1) in a non-manual mode of operation;
After receiving the JLL/reverse flip 7D knob output FWD,
or (2) specifying reverse rotation in manual mode of operation.
output based on driving switch SD to
issue. in two states: (1) manually or automatically;
(2) The state in which the chair is commanded to be driven, and (2) the reverse state of the chair.
Rotation is specified manually or forward rotation of the chair is non-manual
If both of the specified states exist, the NAND
Output 876 (given in section L3 of Figure 10F)
Issue power RLINFWD. Finally, NAND gate 886 and inverter 884
The following pile pipes are: (1) manually or automatically driven;
(2) Manual reverse rotation is also automatic.
RUNBKD (
This is given in part L3 of Figure 10F).
join to. Referring to the younger brother 10F diagram, basically input RLINFW
D causes current to flow to the operational amplifier 8220 negative input;
However, this current flows through resistor 830 and capacitor 832.
It is not applied instantaneously because of the associated RC time constant. Calculation
The current to amplifier 822 drains operational amplifier 822.
Pressure force is generated. Preferably, this voltage output is the voltage output associated with operational amplifier 822.
+5 buttons as adjusted by potentiometer Pf
Ruto. As shown by the logic in Figure 10G, RUNF
Manually exclusive input from WD to RU7NBKD
This results in an interesting output of operational amplifier 822. Also,
As mentioned above, this voltage output of operational amplifier 822 is
Preferably 15 volts. The magnitude of the BKD output is reduced. Preferably 15 volts
to -2.5 volts. R8LOW is based on the above-mentioned belief.
System reset cabinet as indicated by No. R8T.
is on only. Each of the above input signals processed by part L3 is
The foregoing in Figures 10C, 100(1) and 10E
The source mainly originates from parts L2, 12' and L2-'.
It is q. Portion L3 (Fig. 10F) is connected to switch SA and
These switches include, for example,
For the purpose of inspecting the chair motor 50 (FIG. 2),
Gives you the ability to choose your movements. Inputs RUNBKD and RLJNFWD are
plastic devices 810 and 824. When input bRUNBKO goes low, current flows through resistor 812.
current, turning off NPNt-transistor 814 and turning off the resistor.
The negative current is routed through resistors 816 and 820 to operational amplifier 82.
Give to 2. As a result, the computational amplifier 1822 outputs a negative output.
give. Conversely, when RUNFWD goes low, the optical coupler w82
4 causes current to flow through resistor 826 and transistor 8
28 turns off, providing a negative voltage to operational amplifier 822.
Causes an inflow force. As a result, operational amplifier 822 is positive (+
15 volts) output. Input R3LOW is the non-manual operating mode of chair 8 (Figure 2)
When the input goes low, the low input is output to the optocoupler device 1826.
is detected. Non-manual operation goes to NAND gate 829
By MANRLIN going high as given
It should be noted that the input is shown as
R8LOW is provided, which is inverter 836
is inverted to R8LOW. Hikari Kabra @1I82
6 is a PNP transistor in response to the detection of low power.
832 is turned off and the negative voltage is applied to the negative input of operational amplifier 822.
given to. However, resistors 834 and 838
are the corresponding resistances (mentioned above) 816°831 and 820
．． 839, respectively. Therefore, how large is the negative current at the input of operational amplifier W822?
Not much, but half of that. As a result, operational amplifier 822
produces an output that is half the magnitude of the output described above. When switches SA and SB are in the "normal" position,
The output of operational amplifier 822 is connected through resistors 848 and 850.
and is applied to the output terminal MTR8PDI. This output
456 (Fig. 9c);
Circuit 456 beam 2 servo control @12320 (7th A
This is the speed display input for the
Further analogs determine the operating speed of motor 50.
Generates output MTR8PD. Therefore, RUNFW
Positive and
and negative voltage output VTR8PD1, which are at full speed.
Supports forward and reverse rotation of the chair. Furthermore, the negative voltage output VT is caused by the low power R8LOW.
R8PD1 is generated, which rotates in the opposite direction at half speed.
The value has been reduced by half. Portion L3 includes switches SA and energizable to "manual" position 1.
and SB. In such a position, the output MTR8
PDI is the potentiometer 8 to the output of the operational amplifier 822.
52, resulting in motor speed MTR3P
Manual adjustment of D1 can be accomplished. In addition,
When switch 8B is moved to the "manual" position, the output MAN
RUN goes low indicating “manual drive” operating mode, etc.
The output MANMODE goes high and displays the same
. Furthermore, output TEST1 (explained with reference to Figure 10A)
) goes low, which causes the inspection warning indicator to go low.
DS10 (Figure 9A) outputs TWLON (10th
As a result of Fig. A), the light is made to flicker. Finally, a potentiometer 844 is provided in portion L3.
This potentiometer 844 is a zero bias potentiometer.
The output of the operational amplifier 822 is RLJN.
Both FWD and RUNBKWD are high (i.e.
RUNFWD and RUNBKWD are both off)
used to ensure zero volts.
It will be done. 10H and 101 are the logic section 62 of FIG.
FIG. 4 is a detailed view of each of minutes L4 and L4'; Part L
4 and L4= logic circuit is operated by operator control unit 450 (
Fig. 9A) When receiving signals from various switches on
, a flash device 70 and a strike cage 76 are installed, respectively.
Motors 68 and 74 for raising and lowering (Fig. 2)
Receives the signal from the upper limit switch. like that
As a result of receiving the signal, the logic circuits of portions L4 and 14'
Generally, the flasher 70 and stripe cage 76 are raised.
and lowering, and also striped cage 7
The relay panel 20 (second
8). Finally, logic portions L4 and 14' provide status output signals.
, these signals are sent to the processor 34 (FIG. 2) to
Two devices, a flashlight 70 and a stripe case.
76 shows the state of page 76. Referring to part L4 of Figure 10H, INIT goes high.
Then, flip 70 knob 900 is turned on. The result
As a result, the -〇- specific output is low. Limit switches 902 and 904 are visual motor devices
[Limit Up J and “Limit Down” related to 16]
switch. In particular, with reference to FIG.
The motor 74 that raises and lowers the cage 76 is
In a preferred embodiment, switches 902 and 904
(Figure 10H). Switches 902 and 904 are
Although normally closed, the stripe cage 76 is operated by the motor 74.
are raised to their upper and lower limits, respectively.
Open selectively. During initial system setup, the stripe cage 76 is
It is always in the top position, so switch 902 is
open and switch 904 is closed. Furthermore, it is open
upper limit switch 902 and (lower stripe cage)
Operation of switch S8 (DNCGSW) to
In combination with controller energization, the system can be reset (R3T
), the up-flip signal is output via NAND gate 910.
Up flop 906 and down flip flop 90
TRMTRON causes the operation of 8 to turn on the motor.
) and TRMTRDN goes low.
Therefore, the stripe cage 76 is specified to be lowered.
Ru. Turn-on of motor 74 and stripe cage 7
6 is lowered in the manner described above with reference to FIG.
Performed by signal TRMTR and TπVT1■X.
be exposed. When the lower limit of the stripe cage 78 is reached, the switch 90
4 open and "strive ready" cape (STRPRD)
Y) is the switch of the operator control section 450 in FIG. 9A.
S, I are stripe cage light 400 and stripe cage light 400
Boogu, to energize the upper rotation motor 74' (Fig. 8).
NAND goo) 912
．． Inverter 914 and NPN transistor 916
displayed through. NAND gate 912 outputs via inverter 918
While outputting LITEON, through the inverter 920
TRNCG, which connects circuits 532 and 533-t
(Figure 9E) respectively, so that further
Output KITE ball and +〇GVTR, ”-CGVTR
is applied to relay panel 20 and motor 74' (Fig. 8).
I can do it. Referring to Figure 8, LITEON can go low.
This gives power to the striped cage light 400.
On the other hand, the input to motor 74-CGMTR and
and +CGMTR are activated by motor 74'.
76, respectively. The direction of rotation of the striker 76 (Fig. 8) is determined by the operator.
By switches S and 4 of the data controller 45o (FIG. 9A)
shown. With this, NAND game t・922#
tF924kJJ input fT7FT'51 and RHT
SW is selectively generated, and these gates are connected to the inverter.
Output DATIN13 and
DATIN 14 to computer processor 34 (Figure 2)
give to DATIN13 indicates "stripe right" rotation status, and other
On the other hand, DATIN14 indicates a "stripe on" state. Attach the striped cage light 400 (Fig. 8) to the top of the bale.
The ITEON receives the aforementioned signal commanding it to turn on.
, upflip 70 knob 9o6゜NANO gate 91
2 and inverter 918 to switch S, (UP
CGSW). prohibited when the striped cage is commanded to rise.
It will be done. In a similar manner, the output TRNCG (cage rotation finger
) also includes a NAND gate 912 and an inverter 92.
Forbidden via 0. Referring to FIG. 101, portion L4- is the
includes a flip-flop 950 set by the
, at this time, the Q output of Noritsubu 70 and Tsubu 950 is NAN.
One shot device via D gates 952 and 954
956, which is short (preferably 0.15
second) generates a pulse σ. NAND gate 952 is that
performs an OR operation on the inputs to the other NANO
Gate 954 causes the output of NAND gate 952 to become T.
blocked by RMTRON and L IMDNOF
(the latter two signals are the 10th
One-shot device 95 (received from part L4 in Figure H)
The 10- output of 6 causes the output by NAND gate 958 to
Generates a force FLMTRON (flash motor on) and
The output of is the high input to circuit 532 (Figure 19E).
and provides power to a flash motor 68 (FIG. 8). difference
Additionally, the output of the one-shot device 956 is equal to the output of the flip 70.
Reset the knob 950. Section 1-4' is also shown in Figure 9A for the purpose of raising the flashlight.
Operation of switch S9 in operator control section 450 of
Receives input LIPFLSW as a controller driven bundle. Input tJPFLSW sets flip 70 knob 960
and its “set” output (if it is a NAND game)
RM T RON and L I given to 954
NAND gate (unless blocked by MDNOF)
952 and 954. the result,"
Operation of “Flash Up” switch $9 (Figure 9A)
The flash motor (FLMTRON) is automatically activated by the motor drive.
turn on. In a similar manner, the operator control 450
D by activation of switch SP by the operator.
Flip 70 knob 962 is set via WNFLSW
and its set output is connected to NAND gates 964 and 9
58 to generate FLVTRON (re-
Then, the NAND gate 964
t3 and L Not prohibited by IMDNOF
),. The first OJ diagram is a detailed diagram of the portion L5 of the logic section 62 in Figure 2.
be. Part L5 includes 5YNCIN and 5MSSAMP
These occur in the photostimulator 72 (Fig. 2).
), the flash device 70 is activated, and its operation is EOG.
Computer via interface 30 and part 5
This is performed under the control of the data processor 34. in general
, portion L5 is for driving the photostimulator 72.
Li sends a pulse to the flasher 70 and flashes once on the command.
occurs. In addition, the CEOG system once again
For example, 2.5 mm through the stay simulator 72.
Subject once during any time period such as seconds, 5 milliseconds, etc.
2 stimulation, and thus computing the electrode test data.
Arrangements can be made for transmission to the data processor 34. Referring to the 1st OJ diagram, part L5 is Noritsubu 70 and Tsubu 9.
70 and 97〉, these 7 lip-flops are
Power-on initial setting input (INIT> or computer
Reset by initial setting input (GOMP I NIT)
These are connected to NAND gate 974 and inverter
Flip-flops 970 and 972
given to. Noritsubu flop 970 (7) Q output is one-shot device
w978 and series connected one-shot device 980
drive for a longer (preferably 5 ms) time m period
short (preferably 10 microseconds) pulses separated by
occurs. Such output is indicated by 5MSSAMP
Ru. This is provided to circuit 250 in Figure 6D.
sample J pulse, which is the output SAMPLE (first
(used for ADC in Figure 6A)
It is used for Variable for one shot 1w980 (potentiometer)
to provide time control through data 984 and 986.
, Flip 70 Tsuno 972 is Soleno via Riki Ishikawa
energizes the ID/switch combination 982 to close the switch.
Ru. As a result, the one-shot device 980
a starting sample of duration (preferably 2.5 ms);
can be adjusted to provide a pulse. One shot @1f978 is a flip-flop 970
■Triggered by the falling edge of the pulse output from the output
. This falling edge flips in response to the D input, DOUT13.
generated by flop 970, whose input is a combination
” - “GO bit” input from tablo processor 34 (Figure 2)
Including power. DOUT13 is 5 milliseconds apart according to the mulberry type.
The desired pulse train that occurs is shown. Similarly, the processor 34
Input DOUT II to D input of Noritsubu 70 Tsubu 972
and this gives a starting sample pattern of 2.5 ms.
One-shot device 980 is adjusted to perform pulse separation.
do. Flip-flops 970 and 972 connect to inverter 98
A computer generated screen given via 8
Clocked by the C input by entering the Tr to the trove.
It should be noted that 5TROBO is
(not shown below) in the interface chair 30 of FIG.
(see discussion of Figure 11D below)
) @10J further refer to part L5 in the diagram, and
Sensor 34 (Figure 2) is the D input of Noritsubu flop 990.
Generates a flash bit [1OUT12 which is applied to
Flip-flop 990 is generated by a computer.
Ta strike

[Clocked by Coop STOO]
The Q output of 17 Resop 70 Tsubu 990 is one shot [1
This 8W992 triggers the inverter 99.
Short duration (preferably 157 cross seconds)
generates a square wave pulse. This pulse is the emitter input
is applied to transistor 996 as its collector output.
The force generates a flasher synchronization pulse 5YNCI N. 5YNCI N is pulsed, preferably 25 volts
It has a "shaking" of
to the photo-stay simulator 72 to synchronize the
It will be done. Flip-flop 990 was activated by the operator
Reset (R3TI or NAND gate 998 and
One-shot device provided via inverter 999
! Set by 992's 100 output. 10th figure shows details of part L8 of the logic section 62 in FIG. 2.
rsru. Part L8 is the file from X Kagami Shinshu (XBACK>
Y mirror 14 (Figure 2), especially mirror 14
Generate a signal (YFIX) that is sent to the Yl direction circuit of
, on the cylindrical wall 18 (FIG. 1) of the inspection station 4.
Correct spot (laser spot) distortion. This distortion
, the laser 12 is placed above the head of the subject 2, and therefore
Cylindrical! ! The fact that it is pushed downward on 18
It is something that occurs. Referring to the 10th figure, part L8 is GK to Heka x B,
In other words, it receives the ablog signal given by 14.
Rir. Separation operational amplifier (voltage) A[]wa) 1000 is
Positive input
input (bias and hakama are both podenshome)
adjusted by the controllers 1002 and 1004).
The output is given to both positive inputs of the multiplier 1006.
I can do it. Squared I! I unit 1006 smoothes the output of amplifier 1000.
However, the result can be converted to a separate operational amplification e<w pressure filter A.
(w) Give it as output YFIX via 1008. this
The arrogant output YFIX is the partial LIO (first
0M diagram). As a result of the operation of part L8, light 1! (Laser) 12 and
The line of sight from the cylindrical shape 1118 (Fig. 1) and the eyes of subject 2
and cylindrical! ! ! The vertical line that exists between the 18 open lines of sight.
Correcting or compensating for right angles is achieved. FIG. 10L is a detailed diagram of part L9 of the logic section 62 in FIG.
be. Generally, part L9 is the MOVE
) and stores the four bits from
The 4 bits are as follows. DOUTIO (Go X pit): Part L1 to be described later
0 (Figure 10M) in the X direction according to the circuit included in
Bit that scans the mirror. DOLJTl 1 (CMPS rNE): MOVX
in the X direction using bits 0 to 9 of the register (described later).
This is the bit that scans the mirror that
Ranges from -30″ to +306 in increments of 4111
be. DOLITI 2 (CMPSHTR): Shirtta 66
(Figure 2) Opening bit. DOLJTl3 (YSCAN): Part explained below
In the Y direction according to the signal from L10 (Figure 10M)
The bit that scans the mother-in-law. As mentioned above, input DO4JT10-DOLJTl3
connects NAND gate 1024 and inverter 1025
Each flip-flop is
1020-1023 Hestropped
It is noteworthy. The 100 output of flip 70 tube 1020 is NAND gate 1
026 to form the output X5INE. NAND game
The other input of port 1026 is the operator control of FIG. 9A.
450 switch S+s, so the automatic/sensor
Turn the set-up switch S's to the "set-up" position.
or DOUTlo).
is generated. X5INE is the output of inverter 1028, and NAN
Flip 70 knob 1022 at D gate 1032
10- output is ORed to connect transistor 1036.
Gives the output −[− through. -8-HUT is mirror 14 (No.
Figure 2) has a beak shutter 66! To pHlW1
used. Additionally, X5I from inverter 1028
NE is a NAND gate to provide the output CMPSINF
Flip 7 in 1030 and inverter 1034
AND processing is performed with the Q output of the 0 tube 1021. Inverter 1028 and NAND gate 1030
The outputs of each are ORed in NAND gate 1038.
This gate 1038 is connected to the base IIIll input.
power to transistor 1040. Transistor 1040 provides a collector output ffT, which
This is the radar associated with the sister 14 and the shutter 66 (FIG. 2).
12 shows the operation of the server 12. Q output of flip 70 knob 1023
The power is wired OR to the base of transistor 1040.
The connection is provided via inverter 1042.
It should be noted that In this way, DOLJTl3
The existence of (YSCAN), that is, 70 flips and 710 flips.
The input to 23 also drives the scanning light. C whenever the computer is turned on or off
via NAND gate 1o44 and inverter 1046
The input signal CMPf? One gun is flip 70
Reset knobs 1020-1023. INIT is raw
If the operator resets the system or the chair
An input that occurs whenever you go into “reset” mode.
If the force R31 is also inverter 1046 and 1o48
Flip-flop through NAND gate 1o44
It functions to reset 1020-1023. Part L9 is also the initial setting input - "NONYO C RESET [-
This initial configuration includes a flip-flop 1050 that is
The input is the output signal when power to the system is turned on.
Occurs in seconds. Flip 70 tube 1050 is a computer
writes data to one of its registers.
input WRTONLY to indicate that the
to load data into the MOVY register.
It is set by STRBMY, which is STRO-1. These inputs are connected to inverter 1052 and NAND gate.
via port 1054. flip flop 10
The output at 50 is discussed further below with respect to Figure 10M.
The output is 5 TOREV. FIG. 10M and FIG. 1ON are part of the logic section 62 in FIG.
FIG. 3 is a detailed view of each of minutes LIO and LIO-. Department
minutes [10 and 10' are various analog switching
respond to perform functions, and those functions cause
The drive of the plow 14 (Fig. 2) in the direction is computer controlled.
This can be achieved either by control or local control.
can. Additionally, partial LIO and 10- do the following:
perform various summation and analog switching functions for
Respond accordingly. That is, (1) the operation in Figure 9A
adjustment knob P of the controller control section 450, and the computer
111 in the Y direction by both processors 34 (FIG. 2).
4 (Figure 2). computer processor 3
4 is reached via the MOVEY register as explained in
will be accomplished. (2) As mentioned above, cylindrical! 218 (Figure 1)
Part L8 to correct the distortion of the laser spot located above.
mirror according to the correction signal generated by (Fig. 10)
1L (3) of the Y-direction scan of 14 II as described
, the mirror is generated by the generating circuit in part L11 of FIG.
14. Generation of drive signals for Y-direction scanning. Occurrence of examiner
The @ path also generates a drive signal for scanning in the X direction. In addition to the above, the portion LIO- is 1114 (second
(Fig.) was established for the purpose of feeding back signals from the
Contains two buffer amplifiers and therefore
The processor 34 is located at the corresponding position X, which will be explained in more detail below.
and the position of the X mirror and Y mirror with respect to the position Y register.
It can be read and displayed. Referring to FIG. 10M, the portion L10 is the portion L1i (1
5I, which is an analog signal generated by
GOtJT is received, and this analog signal is transmitted to the laser 12/1.
114 (FIG. 2) of the desired scan to be performed.
Fix the pattern. Furthermore, the portion L10 is
1. The output X5r generated by part L9 of the O1 diagram
NE, which is an enable input enable gate 1100
(preferably a field effect transistor analog switch
) and input 5IGOUT to the negative input of the summation amplifier 1102.
The positive input of this amplifier is connected to ground. So
As a result, the summation amplifier 151102 has a large output signal @
Generates XDRIVE. Part L10 is the input MOVX (MOvx register)
bits 0-9) of input M
OVX is generated by part L9 of the 1lilOL diagram mentioned above.
Gate 1 activated by input CMPSINE
104 to the negative input of summing amplifier 1102.
It will be done. Correct bias for negative input of summation amplifier l11102
is provided by bias circuit 1106. Thus, which input, X5INE or CMPSIN
According to whether E, was received by part L10 or not
, 5IGOUT (generated by part L11 in Figure 100)
pattern) or MOVX (computer-generated pattern) or MOVX (computer-generated pattern)
(generated patterns) to the summing amplifier 110.
2 to gate the chain drive output XDRIVE through
Form. Output XDRIv1ELt x driver card (not shown)
This is the analog input to @14 (Figure 2).
conventional hardware elements provided. With further reference to portion 110, the system initialization (I
NIT) generates 5TOREV, which is generated by the amplifier
switch 111 as enable input via 1112
given to 4. As a result, the bias circuit 1116
The bias voltage given is further applied to another summation amplifier 11.
1118 through switch 1114 to the negative input of 1118.
be done. Scan in the desired Y direction according to pattern 81GOLJT.
In response to input YSCAN specifying switch 1108
passes 5IGOLJT to the negative input of amplifier 1118. So
As a result, amplifier 1118 outputs 81GOUT (Fig.
pattern generated by part L11) or MO
VY (computer generated pattern)
YDRIVE (#I414 in Figure 2)
A Y-direction m motion signal) is generated. Inversion of YSCAN
is switched by inverter 1120 as an enable input.
switch 1122 and thus amplifier 1118
disables further inputs to the negative input of and thus
When using YSCAN, parabolic correction is disabled. In particular, when the switch SW is in the upward position, the input Y
FIX not only has gate 1122 but also resistor 1124 and
of summing amplifier 1118 via potentiometer 1126.
applied to the negative input, thus driving mirror 14 in FIG.
Correction factor for YDRIVE output (described above)
give. Portion L10 provides voltages -VSS and +VoO, respectively.
including circuits 1130 and 1132 that supply the
The circuit also provides voltage to potentiometer 504.
used for Potentiometer 504 is operated
In relation to the adjustment knob P4 of the data control unit 450 (FIG. 9A),
The portion 450 receives light from the light source 12, as described above.
Used to adjust the vertical position of the laser beam. Po
As a result of the adjustment of tensionometer 504, its center tap is
amplification! Give the other summation input to the negative input of 11118, and do
Therefore, Y is adjusted such that the desired vertical positioning of the light beam is achieved.
Achieve the necessary adjustment of the directional chain drive output YDRIVE. Referring to the 1st ON diagram, the part L10' is basically an operation.
This operational amplifier includes an amplifier (voltage follower) 1150.
The device is mirror 14 (feed from the 5t IP circuit of 2nd S)
Receive the back signal XBACK and amplify it appropriately
to obtain analog output posx. analog output posx
As previously discussed, the converter stage 56 (FIG. 2)
i.e. through its ADC part, so that the mirror
A digital input representing the position is input to the computer processor 3.
given to 4. Partial LIO- is analog output PO8
A feedback signal YBACK (
Same as for the Y-direction feedback signal from the sister 14)
It is the same as the circuit that performs the function. FIG. 100 is a detailed diagram of part L11 of the logic section 62 in FIG.
It is. Basically, the hand 1llll function switch S, 2 (
) on operator control 450 in FIG. 9A is a sine wave.
Set to request scanning of light source 12 according to a pattern.
of the light beam generated by the light source 12 when
A sine wave oscillator used in establishing the scanning pattern
, portion L11 includes. As seen below in F, part L1
The frequency of the sine wave generated by the 1 sine wave oscillator is
, by the adjustment knob P of the operator 1111 section 450.
As set, various inputs corresponding to the scan speed settings
Controlled by force signal. Furthermore, the part of Figure 100
L11 is necessary for selection in various scanning waveform patterns.
Contains the necessary circuitry, which is controlled by manual function switch S+2.
selected. Referring to Figure 100, @111200 is a conventional installation.
location, preferably California. I created by Cooper Chino's Intersll
C18038 is good. It is at its output terminal 2 that the device
Adjustable sine given to Ll11 terminal of f1200
has characteristics determined by wave timing circuit 1202.
Generates a sine wave. Furthermore, the apparatus 1200 can generate a square wave.
output to its terminal 9, and -toothed output to its terminal 3.
give to As explained in Figure 9C, the switch
S12 prompts the operator to specify the desired format of output.
Therefore, it is used. Switch 312 is 1'! 5QUA
Generate (selectively) R, TRINGL and 5INE
, and these inputs are connected to the corresponding relays 11. 12 and
and 13, respectively (Figure 10L). Swish
11. As a result of selective energization of 12 or 13, the
1200 square wave, sawtooth or sine wave outputs are separated
to the negative input of amplifier 1204, whose positive input is grounded.
has been done. As a result, the amplifier 11204 outputs 5IGO
Issue UT. The correct bias for the negative input of isolation amplifier 1204 is via
This is performed by the switching circuit 1206. The equipment 1200 has frequency control manual 08R at its terminal 8.
EF is given, and this input 03REF is the voltage divider resistor 4
Voltage divider with 98 and 500 (see Figure 9C)
Source potentiometer 496 connected to the configuration
. Signal 08REF is connected to operator control section 450 (Fig. 9A).
), the frequency control resulting from the operator energization of the adjustment knob P,
It is a powerful force, which allows the operator to maintain the level of 14.
Recall that we adjust the scan speed. This effect can be achieved by using input 03REF as a frequency control input.
11200. at the very end
, reference voltage inputs +VREF and -VREF are device F1
200(f)'II Pressure Input'llA Child V, , OJ:
and VEE, and this input terminal is also
connected to respective supply voltage circuits 1210 and 1212.
It is continued. Part L11 is connected to terminal 10 of @121200
An interlocking switch SN is provided. Switch SN is downward
Normal frequency of operation of the device 1200 when in the oriented position
give rise to a number. However, switch SN is in the upward position.
1, produces a high frequency of operation of the device 1200.
The same and this is caused by the output signal @TEST1 going low.
shown. Figures 11A to 11D and 11G are Figure 2
Detailed logic of the CEOG system interface 30
FIG. 2 is a block diagram and a circuit diagram. Figure 11E, Figure 11F and Figure 11H are C of Figure 2.
Regarding the operation of the interface 30 of the EOG system,
Write (data out) sequence and read (data out) sequence respectively.
tine) sequence and interrupt sequence timing
It is a diagram. With reference to FIG. 11A, three tri-shaped cicada buff doors 1230
．． 1232 and 1234 are provided, each of which
Input message! (Respond to GA-Roro Costco. In particular, r
When low, tri-state buffers 1230, 1232 and
and 1234 are energized to cause processor 34 (FIG.
) at a pre-wired address (e.g. preferred
In the example, address 000.154) is the 3-state buffer y
Output 0AT via 1230.1232 and 1234
Pass to O-DATI 5. The output of recovered patients is further discussed below.
1118 is given in the configuration discussed in FIG. Conversely, when GATVEC goes high, three-state buffer 1
230.1232 and 1234 are output terminals DATO-
detected as an open circuit to DAT15, and as a result the second
Data from DATO-DAT9 from 34 in the diagram
data is applied to the configuration of FIG. 3-state buffer 1
230. "n[5'l path" shape of 1232 and 1234
As a result of the state, outputs DAT10-DATl 5 are not active.
do not have. The tri-state buffers 1230, 1232 and 1234 are
In a preferred embodiment, Texas Instruments
Thus, a 5N74L3365 device was manufactured. ! Referring to Figure 11B, the configuration included here is Pastra.
receiver devices 1240-1243 and 3-state buffers
1244 and 1245. Path transceivers 1240-1243 are operated manually by ATE.
Receive and respond to it. Especially when the DGA is set to low.
Then, data and DATO-DATI5 are internal inverter 1.
246 (for illustrative purposes, only device 1240 is shown)
) to the terminals DALO-DAL15.
The terminals are common to the computer processor 34 (Figure 2).
), and data DALO-DAL
15 is the output terminal DALO- via the inverter 1247.
Passes to DAL15. On the other hand, when ■100 W Ryo Ding goes high, the data becomes 0ATo-D.
ATI 5 over-inverter 124 with internal inverter 1246
7 to the output terminal DALO-DAL15. Output terminal DALO-DALI 1 is a three-state bar as input.
Connected to Tsuhua 1244 and 1245, these buses
The buffer responds to input W with DALO-DAL
I1 is passed to output DTOAO-DTOA11. rear
input to the DAC circuit of converter stage 56 (FIG. 2).
give. Conversely, when GA-TWRIT goes high, state 3
state bar, sofas 1244 and 1245 are placed in an open circuit;
Therefore, any output DTOAO-DTOA 11 is excluded.
remove. To summarize the above explanation, when DGATE goes low,
Data DAT (lDATl 5 is the computer path (D
Write to computer via ALO-DAL 15)
It will be done. Conversely, nGATE goes high and GATWRIT goes low.
, the data is transferred to the computer processor 34 (second
) via the computer bus (DALO-DAL 1
5), path transceiver 1240-1243.3-shaped butterfly
Buffers 1244 and 1245 and output terminal DT
converter stage 56 (second
(Figure) is applied to the DAC circuit. In a preferred embodiment, the computer determines N, 5Y.
NG, WTBT, IAKl, 887 and
ding] further transmits other path transfers via the computer bus.
Receiver equipment M (not shown. Path transceiver 1240-1
243), so that in its output
Corresponding control data DOUT, DIN, 5YNC,
Generates WTBT, IAKr, 887 and INIT
do. These control data are used in the method described below.
. Most importantly, path transceivers 1240-1243 are
In a new embodiment, the path transceiver, Model No. D
M8838 (manufactured by National Semiconductor)
construction). Additionally, three-state buffers 1244 and 1
245 is, in the preferred embodiment, a buffer device 5N74.
LS365 (manufactured by Texas Instruments)
). Referring to FIG. 11C, interface 30 (second
Figure) is also a 3-state buffer device w1250-1253.
and a latch circuit 1254. In operation, device 11250 has GATWRIT low.
In response to proceeding to the data DAL8-DAL13 (
Pastra>Seam @@12 in Figure 11B just mentioned above
4013YU 1241 (7) Output) to output terminal DO
Pass to tJT8-DOUT13. In this way, the latter
The force is the corresponding input ■WT] - fWrT (in Fig. 118)
passtrans from (given via computer bus)
Sheeba@ll! Extract indirectly to 1240 and 1241
and, in particular, the control bits in the control word register (described below).
This is cut 8-13. Conversely, the input GATWπ-F]- is
When high, three-state buffer P1250 goes open circuit.
data will not pass through it. The three-shaped Nawate buffer 1251 is GRPlSTB ([Glue
In response to the output D going low in response to
Connect AT 10-DATl 5 to ground, thus
DATI 0-DATl 5 creates 0-(0) output state.
Start out. Analog-digital converted data (Figure 2)
converter stage 56) is input to the processor 34.
GRPIST■ goes low whenever it should.
It should be noted that. Referring to Figure 6A, the controller
The converters A/D1-A/D5 are 10-pit data (DA
TO-DAT9), so the three-state buffer is 125
1 replaces the preceding O with the most significant 6 bits 11f (DA
Tl 0-DATl 5) Insert the necessary functions into
Let's do it. Returning to Figure 118, DGAT
goes low when data input to the
Let's remember what I said. Therefore, the 3-state buff
0ATO-DATI5 from 1250-1252 is installed.
Computer bus (21240-1243)
DALl-T [λ] Ding]-Ishiichi). Furthermore, with reference to FIG. 11C, the three-state buffer y125
2 goes to low 5 TROBI (r status incos
2 and II OA diagram and
and the data D provided by the logic section 62 of FIG.
Output AT lN9-DAT lN14 [) AT9-D
Pass to ATI 4. As mentioned above, this output is
1240 and 1241 (Figure 11B)
given to the computer bus. When 5TROBI is high,
Tri-state buffer 1252 prevents data transfer. The latch circuit 1254 is
1 strobe), the compiler of FIG.
Computer bus and equipment 11242. t5 and 1243
The data DALO received from the processor 34 of FIG.
- Troop DAL4 to latch circuit 1254; 3
Status buffer 1253 goes low 5TROB1 (r
@121254 in response to status register J strobe)
Outputs data DALO-DAL4 latched by
DATO-DAT4, and this output is connected to the equipment shown in Figure 11B.
to the computer bus via ports 1242 and 1243.
Given. Furthermore, the three-state buffer 1253 inputs (
DO3AMP (when a write operation should occur)
also receives the “-included pidsy” signal set in the logic circuit.
, and in response to 5TROBI going low, DO8AMP
is given to the output DAT15. 5TROBI goes high
, the three-state buffer 1253 prevents data transfer.
. The 11th D1g reads the interface 30 in the w42 diagram.
/write decode and control circuits, and
Explanation regarding timing diagrams 11E and 11F
be done. Referring to FIGS. 11D and 11E, inverter 1
270-1273 are respectively derived from the circuit of FIG. 11B.
Human power DAL12. DAL10. DAL9. DAL3 and
and DAL7. NAND gate 1274 has input B
S7. DAL15°DALl4. Did you receive DALl3?
This receives the output of inverters 1270-1273.
decodes the input from the
Input) DAL7-10. DALI 2-15 is professional
A predetermined block of addresses of sensor 34 (FIG. 2)
Extracts 11 outputs whenever it indicates a block. This particular
For inputs DAL7-DA110 and DALl 2
-DALL 5 is address block 164. Oxx again
indicates 164,1xx. To explain in more detail, DALO-DALl 7 is the second
Address input from the processor 34 in the figure, and various
When the DAL bit of
The corresponding address block is shown. Address 17 16 15 14 13164, O
XX 0111 164, IXX OO111 Address 1211109B 164, Oxx 0 1 0 0
0164, IXX O1000 Address 7 6 5 ... 0164, O
XX OO・・・・・・・・・・・・・・・・・・
・・・164.1xx O1・・・・・・・・・
.........Table 1 When 8'hBS7 is logic 1 (on) and NAND gate
address block 1274 decodes the desired address block.
When the computer inputs its address DALO-DA
Call the data to the desired address via LI 7.
put out. Therefore, the output of NAND gate 1274 is
The WTBT input to AND gate 1280 is high and the write
indicates an input operation (i.e., sending data to a computer).
If so, inverter 1278 and AND gate 1
Set flip 70 knob 1276 via 280
. Input 1sYNc (address synchronization pulse) flips
applied to the clock input of flop 1276, thereby
The output of the AND gate 1280 is connected to the flip-flop 12.
F6 strobes and causes RDYWRIT to go high.
Ru. 5YNC is further connected to NA via inverter 1282.
is applied to the ND gate 1284, the other input of which is NAN
Receives the decoder output of D-Goo 1-1274. like this
, as long as 5YNC is low, or the NAND gate
1274 output is high (this indicates the desired address block
is decoded to be called by the computer.
flip-flop 1 as long as there is
276 is reset by NAND gate 1284
I can't do it. However, on day 5, 5YNC was
or the NAND gate 1274 goes low.
, flip-flop 1276 is reset. The above explanation is for the "preparation writing" state (flip 70 knob 12).
76 is shown as a ready write flip-flop)
, but the same basic operation is used for preparing read flips.
This is also done by inputting the flip flop 1286. input 837
is 11 (on), and WTBT is low and “
“read” operation and the desired address block is
When decoded by NAND gate 1274,
The preparation read flip 70 knob 1286 is the inverter 128
8 and through AND gate 1290. The flip 70 knob 1286 is connected via its C input to the
as described above with respect to the flip 70 tube 1276.
is reset via its R input in the same manner as . The configuration in Figure 110 is also a compilation from the configuration in Figure 11B.
Addresses DAL1-DAL6 generated by the computer
It includes a latch circuit 1292 that receives the signal. Latches 1292 are 7 lip 70 tabs 1276 and 12
NAND whenever any of 86 is set
Strobed by gate 1294. Figure 11E
Refer to the timing diagram for computer-generated
The address data DAL (M) and N-1-6 are
Through pewter bass beans L1-DAL6 (Figure 718)
Given. The desired address block is a NAND gate
When decoded by 1274, WTBT (first
(Figure 1E) goes high, indicating a write operation, and the AND gate
1280 sets preparation write flip 70 knob 1276
be able to do so. This preferably means that there is no sign that WTBT has gone high.
It only takes 20 nanoseconds. Once prepared, write the flip-flop
When flag 1276 is set, NAND gate 1294
preferably when AND gate 1280 goes high.
Gets high within 14 nanoseconds. As explained earlier
, the high output of NAND gate 1294 is
Latch the address data from the server 1292
tap. Returning to FIG. 11D, flip-flop 1276 is
set by D gate 1280 and output RDYW
When RIT is issued, the output of the latter is additionally connected to amplifier 1
Output WRTONLY and inverter 1 through 295
296 to give n-d WRIT. Output ROYWR
IT is also provided to NAND gate 1298 and other
The one input receives the signal MDOUT, and this signal DOUT is
Preferably at least 25 nanoseconds after data output begins
It goes high when it starts outputting data. Please refer to the timing diagram of FIG. 11E. NAND game
Port 1298 is associated with input DOUT and RDYWRIT.
and performs an AND operation, and the NAND gate 1298
The output of
Trigger one shot 1il11302 given as
do. The one-shot device 1302 is short, preferably 1
microsecond, negative pulse whose trailing edge flips 7
0 trigger 1304. Q output of flip 70 tube 1304 is NAND gate 1
306, the other input is NAND gate 12
98 inverted output (via inverter 1308)
receive. NAND gate 1306 pulses negative
Perform an AND operation on the entry to it, as in
Its leading edge is also similar to other one-shot equipment J1310.
Gaga. The output of NAND gate 1306 is 5TROBWRITE
, and this output performs an OR operation on it.
Provided as one input to NAND gate 1312
Ru. The output of NAND gate 1312 is inverter 131
4 to the decoder 1316 as a strobe input.
This decoder 1316 is manually operated by A-C.
Address input ADDR4-AD from latch circuit 1292
Receive DR6. Still other add of latch circuit 1292
The response output ADDRI-ADOR3 is of the decoder 1316.
◇9 - further strobed at its D input by the output
is provided directly to other decoders 1318. In summary, ADDR4-ADD to decoder 1316
R6 human power J: (FSTROBWRI TE (F) result
, decoder 1316 receives strobe signals B and G.
Create a group of RP3STB. Output GRP1STB-8RP3STB is compatible (F)7'
applied to coders 192.194I3 and 196 (Figure 6c).
The decoding operation is carried out by the converter stage 56 (FIG. 2).
To generate N used in the DAC circuit (Figure 6E)
It is done. given to decoder 131 coder 1318
, which is also the address input A from latch circuit 1292
Receives DDR1-ADDR3. Yuishiba of this movement, Deco
The controller 1318 outputs the output 5TROBO through the amplifier 1320.
and the output 5TROBO (inverter 132
2 and 1324 and NANO gate 1326.
"control word" strobe) and output
Generates 5TROB1 (r status word strobe).
Ru. In summary, the circuit of FIG.
Decodes AL1-DAL6 and various strobes
Signal (GRPO8TB, GRPISTB, GRP2ST
B and GRP3STB) resulting in -1 group, which
The strobe signals of these groups are sent to the logic section 62 (10th A).
100) and the DAC of converter stage 56
/ADC circuit (Figures 2 and 6A-6E)
) respectively. These groups of strobe signals
By loop, the view tab 0 sesa 34 (Figure 2) is
Ensures that the correct data comes from the correct address location in memory
Find or paste the correct data to the correct address location.
on the other hand, various transfers and analog-to-digital (
't' or digital-to-analog) conversion function.
Adjust the timing. The leading edge of the output of NANO gate 1306 is a one-shot device.
Recall that we triggered W11310.
. Subsequently, the sliding door edge of the output of the one-shot device 1310 is
Trigger (set) rib 70 rib 1338. pretend
The Q output of flip-flop 1338 is therefore a negative pulse.
Yes, this pulse is connected to NAND gate 1340 and input
so that the output 1RPLY becomes low through the converter 1342.
and this output is sent to the computer via the computer bus.
data processor 34 (FIG. 2). NAND game
Port 1340 also supports computer @1 (i.e., CE
During the OG system) interrupt, the signal generated by the 11th (13th) circuit is
It receives the generated RPLY2 and performs an OR operation.
As a result, RPLY becomes the Q of flip 70 knob 1338.
RPL when negative pulse output occurs or goes low
It goes low at Y2. Finally, some unknown amount of time has elapsed (and therefore non-
synchronous operation) as described in the discussion of Figure 11B.
The input DOtJT received via the computer bus goes low.
(see timing diagram in Figure 11E), so N
The output of ANO gate 1300 goes low. This low belief
The issue is NAND game. - gate 1356 (which acts as an OR gate) and
and the flip 70 tube 13 through the inverter 1358.
04 and 1338, thereby output RP
LY goes high or RPLY goes low. If111
Please refer to the timing diagram in Figure E. Shortly thereafter, the signal
5YNC goes low again and - includes (data out)
Complete the sequence. Further referring to the timing diagram of FIG. 11E, the preferred
In the example, the time course shown therein is preferably as follows:
That's right. The time course TIA is preferably a minimum of 75 na
is preferably a maximum of 66 nanoseconds (20
(including nanosecond setup time) and T2A is preferred.
preferably a minimum of 25 nanoseconds; the TEA is preferably a minimum of 25 nanoseconds;
a maximum of 14 nanoseconds, and T4A is preferably a minimum of 25 nanoseconds.
seconds and Tsa is preferably a minimum of 190 nanoseconds.
, Tl1l is preferably a minimum of 220 nanoseconds, and
T6 is preferably a maximum of 120 nanoseconds;
It is 60 nanoseconds. The above mentioned time periods are not shown in Figure 11A.
CEOG as described above with respect to Figure II/111D
Specific hardware used in the preferred embodiment of the system
It is based on the software. The timing diagram in Figure 11F
Refer to the read (data input to the computer) operation
It is done as follows. Computer enters address D
AL (M) is generated and this input is connected to the latch circuit in Figure 11D.
1292. Computer processor 34 (
Figure 2) has a flip 70 knob 1286 (preparatory reading).
given as a strobe input to the output flip (70 knobs).
Generates 5YNC. This strobe (SYNC) has a D input of 5YNC.
If it is in a logical position at the leading edge of the flip 70 knob 1286
set. As long as WTBT is low indicating a read operation, AN
D gate 1290 is NA with respect to inverter 1278.
The desired address, decoded by ND gate 1274,
In response to detection of address block (BS7 is logic 1)
), AND gate 1290 is a flip 7O block.
The logic N11 is given by the D input of 1286. NAND gate
1344 to generate 5 TROBEREAD,
Input RDYREAD from flipflora 71286
and DIN (this is where the computer receives input data)
perform an AND operation on the
cormorant. DIN is the difference between the occurrence of 5YNC and the leading edge of DIN.
to ensure the required time delay (preferably 60t seconds).
consists of a resistor 1346 and a capacitor 1348.
NAND gate 1344 via RC (delay) network
given to. 5TROBEREAD, which goes low, is a latch circuit 1292
Decode the inputs ADDR9-ADDR4 given by
NAND gate 1312 and inverter
strobes decoder 1316 via data 1314.
Ru. Decoders 1316 and 131B are as described above.
, strobe signals GRPO8TB, GRPISTB, ・
... and -101 ``R1] 1 ``D-gi 5 ``Sacrilege r,...''
It functions to generate groups of. 5TROBEA
The signals generated by D are each connected to the data line 0ATO
- Gating specific sets of data onto DATQ (e.g.
For example, 5TROB10 is the chip in the A/D section of Figure 6A.
gate data from channel 1). At the same time, the line DATIO-DAT15 is connected to Figure 11C.
Zeroed by the indicated GRPlSTB. Additionally, 5TROBEREAD goes low, which causes
One-shot sealing 1302 is triggered. 1 microphone
A second model, one shot @l1f1302 signal sliding door
Set the flip 70 knob 1304 on the edge. flip
The output from the flop 1304 is the NAND gate 1350.
It is ANDed with 5 TROBEREAD, and the S input of the
A signal that sets flip-flop 1338 via
is generated. RPLY is the output of flip-flop 1338.
-, which goes low in response to
to NAND gate 1340 and inverter 1342.
act. On the other hand, 5TROBEREAD uses inverter 1352 and
and DGATE via 1354. inverter
1354 is an open collector device, i.e. its
The output of the other A-bun collector output that generates DGATE
Connected to power. ■GATE is pass line DALO~D
To give data DATO-DAT15 to AL15
Recall that it was used (Figure 11B)
. Once DIN goes low, 5TROBEREAD is
Operation of NAND gate 1344 and inverter 1352
Low due to production. Reset of flip 70 knob 1338
The (R) terminal is therefore connected to the NAND gate 1300 and
and 1356 (the latter is related to input -R5〒-r]
) and inverter 1358 to perform an OR operation).
Therefore, it is activated. In this way, flip 70 knobs 1
338 is reset, which causes RPLY to become NAN.
For the operation of D games 1 to 1340 and inverter 1342
Get higher. Then, by computer, 5Y
NC goes low and successive (data in) sequence
Complete the side. Furthermore, referring to the timing diagram of IF111F diagram,
In the preferred embodiment, the time period disclosed in
It is. Duration T+r is preferably at most 54 nanoseconds
118 for too long a period of time.
Removed the previous code from what remained in the carder 1316.
(thus eliminating erroneous codes), Tzr is preferred.
preferably 60 nanoseconds, and Tsr is preferably 83 nanoseconds.
and T4r is preferably 1 microsecond. Also, the above-mentioned time periods are shown in FIGS. 11A to 11D.
Preferably, the circuit is based on the circuit described above. Interface 30 in FIG. and in the interrupt request procedure.
Furthermore, if the logic block diagram/circuit diagram in Figure 11G is
This will be explained with reference to the timing diagram of FIG. 11H. Enter
power 100] ψ〒 “b-(]” is 7 lipflops 1400 (
data preparation flip-flop) and its
Set the Noritsubu 70 tube, and use the other manual DAL15 (I
The most significant bit from the control register described above is 7 times
70 tube 1402 (interrupt enable flip-flop)
is received by and selects the flip-flop 1402.
cut. Noritsubu 70 Tsubu 1400 and 1402
Q output goes to NANO game (NANO game) 1404 that performs AND operation.
and its output is via inverter 1406.
Flip-flop 140 provided as clock input
Set 8. The Q output of flip-flop 1408 is
The output is given as IRQ through inverter 1410.
(See IRQ in the timing diagram of Figure 11H.
). The flip 70 knob 1402 is operated by the circuit shown in FIG.
Can be clocked by 5 TROBO generated
It deserves attention. IRQ is "interrupt computer"
The command is transmitted to the controller 34 as a command. The circuit of Figure 11G receives an input IAKIN, which input is
issued by the computer received via the computer path.
In response to the generated input 11AKI, the equipment shown in Figure 11B *12
40-1243 by 1Ilt6 bus transceiver device.
is generated. In this way, FIGS. 11G and 11
1”, IAKIN and inverter 140
6 are both high, the NAND gate 141
The output EC of 2 is the inverter 1414 and RCil delay.
is provided to an inverter 1418 via a network 1416;
Its output is RPLY2. Therefore, RPLY2
goes low in response to GATVEC going low. Sara
When GATVEC goes low, DGAT
E (This is the output of inverter 1420 and its input
power is connected to inverter 1414) is also
become. 7 in the morning! Jy77oy71408LtGA
TVEC goes low or R8Tl goes low.
and those things are reset in response to the NAND gate.
Achieved via gate 1409J5 and inverter 1411
be done. Returning to FIG. 11D, RPLY2 is NAND gate 13
ORed with Q output of 40 7 lips 70 tubes 1338
The resulting output RPLY is
respond to a computer interrupt (RPLY) or
DIN or D for data read or computer write operations
Remember that it goes low in response to OUT.
cormorant. Furthermore, in its low state, the output DGATE is past
Enable input for transceivers 1240-1243
, which causes transceivers 1240-1243 to
Data DATI 5. DATI 4. ...computer
data path (DAL15.DAL14....)
It would be even more important to be able to do so. Returning to Figure 11G, -1AKIN (bus transceiver
input from the computer via a device (not shown).
IAKIN...see discussion in Figure 118)
goes low in response to RPLY2, the NAND gate
1412's output GATVE-δ goes high, resulting in
GATVEC goes low (Figure 11H). therefore
, outputs DGATE and RPLY2 also go low. Furthermore, IAKIN is computed by IAK(0).
It is passed to other IIw on the data bus and it is passed to the CEOG system.
in response to IAKIN when the system has not requested an interrupt.
Generated by NAND gate 1422. The circuit in Figure 11G can be reset in one of the following three states.
This is achieved in response to In other words, there is no splash return switch.
1424, thereby performing an OR operation.
Now NANO gate 1426 and inverter 1428
Manual switch SWA to generate output rgo through
(Preferably physically located at interface 30)
operation): NAND via inverter 1430
INIT going high given to gate 1426: also
is connected to NAND gate 1426 via inverter 1434
and 1 second timer 1 which provides output to inverter 1428
Turn on the system driving 432, either
A reset of the circuit of FIG. 11G is achieved in response to the condition.
Ru. In the preferred embodiment, the input RST A/D is
NA via amplifier 1427 and wired OR connection
connected to one input of ND gate 1426, thereby
rSTl locks in response to R8TA/D going low.
- and therefore A of converter stage 56 (FIG. 2)
The circuit of Figure 11G is reset in response to the reset of the DO circuit.
cut. Returning to the discussion of inverter 1430 receiving input INIT
and the output of inverter 1430 is the input of amplifier 1436.
and its output is connected to CMPINIT as described above.
occurs. The circuit of Figure 11G is further clocked by input 5TROBO.
Locked and set by input DAL 14
Including lip 70 knob 1437, this human-powered DAL14
Control word register of computer processor 34 of FIG.
This is the 14th bit of the data (IIM description). set
As a result, the flip 70 knob 1437 outputs low output D.
O8AMP is generated, and this output is stored in the status word register (
bit 15 of (l) above). Depending on the inverter 14
The output CMPSAMP from 38 goes high. lastly,
R8T1 or one applied to NAND gate 1440
In response to the trap being reset via τ-F1-
Then, the flip 70 knob 1437 connects the inverter 1442.
It is reset through, and the result is 1! DO8AMP goes high
, while CMPSAMP goes low. The computer processor 34 of FIG. 2 will now be described. The processor 34 is a computer program (software).
) 361 display device 38. Hard copy printer 40. centre
Loppy disk 42 and keyboard (for user control)
)44. Any general purpose having at least the elements/capabilities mentioned above.
You can use a digital computer for
A preferred embodiment of the invention uses a PD as processor 34.
P11103 Central processing training, display 38/keyboard 44
As LJT-52 terminal, floppy disk 42 as
RXV-11 disk unit and computer
Program 36 (this is the digital equipment comment
- easily obtained from poration) as RT-1
1 software package included. Furthermore, Figure 11A
or the circuit in Figure 11G is placed in the memory location of the computer.
will be added. A summary of this addition is shown in Table 2. Table 2 Register Address Read/Load Control Word
Register 164,000 Write only inertia
Register 164.002 Read only data input
Ch 1 164,020 Data CHI2
22 Data CH2 324 Data CH3 426 Data CH4 530 Data CH5 6 32 7”-Evening CH6 734 Chair Speed 8 36 Stripe Cage Speed Data Out 164,040 Write Only
Chl-8-184,056 Move X 164,060
Includes Positelon X 164,06
2 Read only Move Y 164
,070 Write only Po5ition Y
1B4.072 Read-only chair control
164,004 Write only interrupt @
000.154 for data 000.160
The control word register shown in Table 2 for zero adjustment is for 16-bit writing only.
A register, bit 15 to bit 0 as follows:
It is composed of Bit 15: Interrupt enable bit...This bit is
, computer processor 34 (FIG. 2) or logic section 6
2 (Figures 10A to 100) initializes the system.
It is reset whenever the value is set. Otherwise, the
This is done by a computer program (software) 36.
is set/reset. This bit is the preferred
In the example, 7 lip 70 knob 14o2 in Fig. 11G is used.
is actually generated. Bit 14: Provided to ADC of converter 56 (Figure 2)
This is the “1 step” bit. I like this bit
In the new embodiment, it is generated by Noritsubu 70 and Tsubu 1437.
is sent via the data out DAL 14 in Figure 11G.
It generates the number CMPSAMP, which is SAMPLE (the
(see Figure 6D), and is one of the signals that generate
Used in log-digital conversion process II (Figure 6A)
There is. Bit 13: GO pit, send @5MSSAMP
Input DOUT 1 to @X in the 1st OJ diagram to generate
3, one sushi every 5 milliseconds
Request data generation at pull point speed (6 channels)
. DOLIT13 turns on the flip 70 knob 970.
one shot to generate 5MSSAMP.
It will be recalled that triggering the trigger device 978
. Bit 12: Flash bit is input DOLIT12 (CMP
SHTR) as 7 lip 70 knob 102 in Figure 10L
2, which generates the output “HUT and flashes
pulse the device 70. Bit 11: 2.5 ms sample bit is the 1st OJ diagram
It is given as input DOUT11 to the 7 lip 70 tube 972 of
available. Flip 70 knob 972 is therefore
Relay (solenoid/switch) 98 via Q output
2 and thereby one-shot @@980's
Adjust timing. As a result, the sampling time is
Reduced from 5 ms to 2.5 ms. Bit 10: Bit DOLITIO is set to 7 in Figure 10L.
It is given to Tsubu 70 Tsubu 1020 and its Noritsubu Flood
Set the tap. As a result, the flip-flop 1020
generates the output RECORDING via its Q output.
Ru. When RECORDIN100 becomes 0-, Figure 9A and
and display indicator DS9 in Figure 9B are illuminated and the system
indicates that the system is in “record” operating mode. Bit 9: Copy bit, hard copy printer
40 (Figure 2) will print out the test results.
do. Bits 8-0: Bits 5-8 perform other functions or indications.
These are "spare" bits that can be used for
and as determined by a person skilled in the art as necessary regarding the CEOG system.
It will be cut off. Furthermore, bits 0-4 are set by 5TROBO.
The latch circuit 1254 of FIG. 11C is written therein.
Stored in Therefore, these bits are 5TR
3-state buffer 1253 activated by OB1
read back by computer processor 34 via
Ru. This is done in the interface 30 (Fig. 2).
As well as advantageous testing ability for testing timing
, through the computer bus via the interface 30.
CEOG has the ability to perform error checking on existing data.
Give to users of the system. The status word register consists of bits 15 to 0.
It is a 16-pit glue-only register. Bit 15: Write busy pit, control register
1 word to any of the registers except
Must be checked before writing. Moshi beep
15 is on, this means that the CEOG system is
During the “write” command, the convert tab 0 sensor 34 (second
included when memorizing one word transmitted by
It shows that In the preferred embodiment, bit 15
is given by 7 lip 70 knob 1437 in Figure 11G.
It will be done. Noritsubu 70 Tsubu 1437 output DO8AMP
is compiled via trilayer buffer 1253 in FIG. 11C.
It should be noted that the computer input is DAT15.
It is possible. Pit 14: Striped cage of I-skills movement @1116
Striped on pin indicating that 76 is rotating.
It is a cut. This pit is turned on by the operator.
When switched on, switch 811 (FIGS. 9A and 9C)
) and as input DATIN14,
To view tab 0tt34, part 141 of diagram 1oH
7) NAND gate 912. Inverter 918. NAN
Provided via D gate 924 and inverter 928
It will be done. Pit 13 varnish drive right bit, striped
page 76 to the right (bit 13-1) or to the left (bit 13-1).
13-0). Bit 12: Copy busy pit, hard copy
If the printer 40 (Fig. 1) is printing from the last command,
Show what you mean. Pit 11-0: These bits are used as spare bits
As shown, but as is clear to those skilled in the art,
To provide various other control functions/display indicators
can be used. Is the data in register the I10 address in Table 2 mentioned above?
and they are created by each channel 1
- Corresponds to the information of 8. Discussion of ADC circuit (Figure 6A)
As you may recall, digital channel 1 (analog)
in response to log input AMPOUT1) is the left vertical eye movement test.
Channel 2 contains right vertical eye movement test data.
channel 3 includes left horizontal eye movement test data;
Channel 4 contains right horizontal eye movement test data;
5 and 6 contain VER test data, channel 7 (A
(corresponding to analog input TACH2) inputs chair speed data.
Contains and channel 8 (analog human power STR1PE5P
(corresponding to D) contains cage speed test data. Data out channels 1-8 (shown in Table 2) are
The computer of FIG. 2 for the conversion in the converter stage 56
Contains digital data from processor 34. In particular,
Channel 1-1tze Oi1 rectification M of data-out channel
When generating ZRADJ LJ-1, 2°..., 6)
Analog signal BIASN (N-1, 2
,...,6) (see Figure 6E)
Including digital art. The discussion on Channel 5-8 is for full disclosure of this development.
are not important and will be omitted, but channels 5-8
may be used to generate various other analog functions.
It will be obvious to those skilled in the art that
. The MOVEX register (shown in Table 2) is configured as follows.
16-bit write-only register (in the preferred embodiment)
It is ta. Bit 10: GOX mirror, with its own sine wave in the X direction
chain 14 (and associated drive circuitry) to begin scanning in the direction
). 7 in Figure 10L that generates X5INE
The input DOUTIO to the lip-flop 1020 is
reference. Pit 11: CMPS INE bit, mirror 1
For 4, computer processor 34 is 14 x
command that the should be controlled, thereby
The 10 lowest pits of the MOVX register are mirrors for xII.
The operation of the machine is being controlled. 7 lip floats in Figure 10L
Input DOUT11 (CMPS I
NE), and CMPSI by inverter 1034
See occurrence of NE. Pit 12: CMPSHTR bit, this pin
The cut opens the shutter 66 (FIG. 2) and lights the laser 12.
allows light to pass through it, which is usually a pitch
10 or 11. 7 in Figure 10L
Input DOUT12 applied to lip-flop 1022
(CMPSHTR). As a result, NPN
)--generates 5HUT of transistor 1036. Pit 13: YSCAN pit, this pit
causes the Y deflection mirror to scan, which means scanning in the Y direction.
It is similar to Pit 10 except that it is controlled. 1st
See input YSCAN to amplifier 1110 in diagram 0M.
and refer to the occurrence of chain drive output YDRIVE following that bond.
I want to be In a preferred embodiment, humans 10 and 13 are turned on at the same time.
When the mirror is turned on, it scans the mirror in a 45 degree direction (i.e. one
along a line with a slope) is achieved
should be noted. Pit 0-9: These 10 bits are input by processor 34.
C converter stage 56 (
Figure 2). In particular, in a preferred embodiment, the pin
Bits 0-9 are shown as DAC circuit 300 in FIG. 6E.
Provided as input DTOAO-DTOA9 to the circuit of the format
and these f) Te9 bust D-7 human power STRO8MX
(STRO8rl: similar to It) by latch circuit
302 and 303 Hestropped. There, the de
Digital data is converted from digital to analog T7t
D'l output MOVX (similar to Figure 6E (7) BIASN)
(similar to), and therefore the XII of mirror 14 (Fig. 2)
An analog voltage defining the desired movement (preferably -5
+5 volts (111) from volts (000...000)
...111) with - up to) is given. The position @X register (shown in Table 2) is a read-only register.
and this register 7 is for X scan #14 digit 1
Feeds information to second computer processor 34
Check. The 10 lowest pits of this register are mirror
Gives the relative X position. However, in preferred embodiments, GO pits or
1 step pit (both shown above) is on
and the 10 most significant wx registers must be
An interrupt must be received before the lower bits contain the updated data.
Must be. (This is the A/D converter 5 in Figure 6A.
This applies to all outputs of 6'. ) The MOVEY register scans [14] in the Y direction.
This is a write-only register used to
Ru. The ten least significant bits (0-9) of this register are
For the pit 〇-10 that controls the scanning in the X direction,
D/A conversion is performed in the same tube-like manner as [, and MOVY is formed.
, this analog voltage changes the Y position according to operator control.
Works with the potentiometer to move the Y-direction mirror.
Ru. Potentiometer 5 in circuit 502 of FIG. 9C
Please refer to 04. The position Y register is a read-only register;
The least significant bit of gives the relative Y position 1 of chain 14. Place-X
Go pit or 1 step as in register
One of the pits must be on and the position ffY
The ten least significant bits of a register are the updates contained therein.
Interrupts must be accepted before having f-data. Finally, regarding the above discussion, “U, CEOG system ad
The response decoding method is explained in Table 3 below. good
In a preferred embodiment, memory locations w164.000 to 1
64.176 is the true memory in processor 34 (Figure 2).
It should be noted that this is not a harpoon position. insect
, positions 164°000-164,016 are control words.
register. Contains a status word register, and a chair IIJ-register.
and the address of these locations must be decoded to the correct address.
5TROBO, 5TROB1. ···of
The decoding NAND gate in Figure 11D (described above) that occurs
1274. Reached by decoder 1316°1318 etc.
will be accomplished. (Left below) & 3 164,0000 0 0 0 0 0 0 5TR
OBOControlLout0020 0 0 0 0
1 0 1 5tatusin004
0 0 0 0 1 0 0 2
chair0060000110 3 0100001000 4 12 1 0 1 0 51
4 1 1 0 0 616
1 1 1 0 724
10 100 12 1through
826 1 0 1 1 0 1
330 1 1 0 0 0 1
432 1 1 0 1 0
1534 1 1 1 0 0
1636 1 1 1 1 0
1744 100100 22
1 through 846100110 23 50101000 24 52101010 25 54101100 26 56101110 27 74111100 36 76 1 1 1 1 10 37*S
method, position IF164.020-164°036 is professional
Data input from the CEOG system to sensor 34
channels 1-8, such data input is
Of course, it is converted from analog to digital before being input. Position 164,040-164.056 is 7o sesa 34
'3 Channels 1-8 of data output to CEOG system
Of course, such data output is
Taru is converted to analog. Finally, positions 164.060-164.076 are MOV
X register, position X register, MOVEY register,
This is a 1fY register. Thus, in a preferred embodiment, FIGS.
Many of the circuits described above in Figure 11G are located at location 164.000-
It functions to perform the functions of 164.076. in this way
, to "1" in pit 12 at address 164.000.
Therefore, the flash device 70 (FIG. 2) flashes. This pit is
A flash of light occurred and was reset. Referring to Table 3, address data bits D6-DO are in
l1164.000-164.076
The 7-most significant bit of the data address for specifying the address.
represents the cut. In the preferred embodiment, alternating positions (16
4,000: 164°002, etc.) are used.
Therefore, pit DO is the octal value of pit, 06-DO.
Can be dropped by code. in this way,
Pit D6-DI is the path transceiver device shown in Figure 118.
21240-1243 by computer bus
data address line input DAL9-[[
The address line given by DAL6-DALI
Correspondingly, and further, decoder 1316 and FIG.
and input ADDR6-ADDRI given to 1318.
handle. Oscillation decoding in the decoder as described above
As a result of the coding, the strobe signal GRPO of various groups
8TB. GRPISTB, GRP2STB and GRP3STB
is generated, especially 5TROBO-8TRO87,5TR
OBIO~5TROBI 7.5TROB20-3TR
OB27 and 5TROB30-8TROB37 occur
be done. As explained earlier, the CEOG system in Figure 2
preferably by a computer program 36.
The processor includes an a-controlled processor 34. As previously explained, the computer program 36 is
Preferably, use the RT-11 software package (
This is with the preferred processor unit PDP11103.
Digital equipment corporation for use in
provided by the application). Figures 12A and 12B are computer programs.
As a preferred embodiment of 36, the CEOG system of FIG.
The inspection program and the
General flowcharts for each
It is. That is, the computer program in FIG.
36, various selected tests are performed on the patient.
The driving program (Figure 12A) and the test results are analyzed.
Manage test results in a convenient format
analysis program to display or hard copy to
(Figure 12B). Before discussing Figures 12A and 128, a few
Additional introductory explanations may be appropriate. This issue
In the preferred embodiment of the CEOG system, inspection,
Three things to analyze and consider! 1 & it makes sense. In particular, RUN
TEST provides stimulation to the patient and evaluates the patient's response.
Call the inspection process to record and RUN ANAL
YSIS invokes the analytical process, thereby determining the patient's response.
is analyzed and recorded in the patient's record, and the RLI
NREVIEW invokes the review process, which causes II
1 directory of patients whose records were reviewed and processed
can be viewed, and a hard copy of the patient's records
-Copying can be done. As is clear to those skilled in the art
, the processor 34 is preferably an operator (inspection tube I!!
Which of the three treatments (inspection, analysis or consideration) can be selected by the
Select the appropriate alphabet on the keyboard 44 (Fig. 2).
the ability to enter a cut letter (for example, T, A or R)
may be programmed to give. Referring to Figure 12A, assume that the inspection process is selected.
Therefore, such inspection process
By loading the
(Figure 12A)
block 1500). Trivial data such as “today”
placed in the computer's file record (block
1501). The inspection process will start the system.
Thus, for example, RUN on the keyboard 44 in FIG.
You can formally begin by typing SYS (
Block 1502). The screen on display 138 (FIG. 2)
The user data format is displayed (block 1503).
. The test administrator then enters various information about the suspect (e.g. name).
, IQ, etc.) from the keyboard 44 into the data format.
(Block 1504). After completing the data entry, the system will display the inspection menu.
(block 1505), for example, as shown in block 1505),
It is. P-Follow-up Test C-Chair Movement Test ■-Visual Evoked Response (VER) Test R-Return to CEOG System Select Follow-up Test (block 1507), Follow-up Test
The menu is shown as follows. C-Calibration F-Fixed Target J-Jumping Target M-Moving Target R-Rotating Pattern S-Recall Test Type Menu It is assumed that the calibration procedure has been selected.
(1510), the test administrator then performs the calibration
Start the procedure. Such a calibration procedure is
The processor 34 is programmed via the computer program 36.
A specific carry commanded by logging
Predetermined according to the bration regimen. for example
, in a preferred embodiment, such a calibration
The steps are as follows. 1. Perform automatic zero adjustment: Type C6 when completed 2. Continue calibration. Horizontal 15° left carry
Perform bration. Once completed, type C0 3, continue with calibration. Perform automatic zero,
When completed, type C0 4, calibration completed. Horizontal 156 right calibre
- Perform a ceremony. When completed, type C05, caliber
Continue the ration. Performs auto zero, and when completed, the
Type C6 6. Continue calibration. Vertical 8° upkiya
Perform calibration, and when complete, type C0 7, continue calibration. Perform automatic zero,
When complete, type C0 8, continue calibration. Vertical 8° down gear
After performing the riblation, it becomes type CI. 9. Calibration completed. computer is tracking menu
Return to queue. inspection! ! Assuming that the administrator has selected fixed target testing.
(block 1511), the fixed target inspection
is the l of processor 34 and computer program 36.
It will be held after l1m. In a preferred embodiment, fixed
The instructions for performing a target inspection are as follows:
It is. E-Tracking Menu Recall. Press the spacebar to begin recording the test results.
then press again to stop. T-time scale. This is 5.7.5.10°12.
Lasts in 5.15.17.5 or 20 seconds. Otherwise the timescale is 2.5 seconds. A-Auto zero. Press C when finished. 〇 - Open your eyes, press carriage return and stop. C- Close your eyes. Press carriage return to stop
. The operator selects the target inspection that is jumping.
block 1512). The preferred procedure is as follows. E-Recall tracking menu. To record, press spacebar to start and again
Press to stop. ■ - Time scale. 5,7.5,10.12゜5.1
5. Lasts in 17.5 or 20 seconds. Otherwise, Thailand
The time scale is 2.5 seconds. A-Auto zero. Press C when finished. H-Horizontal. Press carriage return to stop. ■ - Vertical. Press carriage return to stop. FH-50 spot horizontal. FV-50 spot sac. Selecting moving target inspection (block 1513)
, the preferred testing procedure is as follows. E-Recall tracking menu. To record, press the spacebar to start, then press again
and stop. T-time scale. 5.7.5.10.12゜5.1
5. Lasts in 17.5 or 20 seconds. Otherwise, Thailand
The time scale is 2.5 seconds. To select the period,
Turn the potentiometer adjustment knob (horizontal speed r in Figure 9A).
! 1llI adjustment knob P3). Remains inspection: Press carriage return to stop. A~Auto zero. Press C when finished. HT - horizontal, triangular wave. H3 = horizontal, sine wave. VT - Vertical, triangular wave. ■S-Vertical, sine wave. If rotational pattern inspection is selected (block 1
514), the preferred procedure is as follows. E-Recall tracking menu. To record, press the spacebar to start, then press again
and stop. T-time scale. 5.7.5.10.12゜5.1
5.17. Lasts for 5 or 20 seconds, otherwise time
The scale is 2.5 seconds. Rotated by operator II3II1 part 450 of FIG. 9A.
Lower the rotating drum. To select the rotation speed, use the potentiometer adjustment knob (I
Turn P2) in 1%9A diagram. P- Perform rotation pattern inspection and check the carriage return.
Stop pushing. TP - Rotate the drum 3 times for pattern inspection. If the test administrator selects a chair motion test (block 150
8) , chair rotation (block 1515) or chair rotation
Either vibration (block 1516) may be selected. The preferred procedure is as follows. C - Calibration R = Rotate the chair to the right or left C = Vibrate the chair for 4 cycles F - Rotate the chair with fixed light S - Recall test format menu. For the chair rotation (block 1515), the following moves are made:
Order is preferred. E-Recall chair exercise menu. To record, press the spacebar to start, then press again.
and stop. T-time scale. 5.7.5.10,12゜5.1
5. Lasts in 17.5 or 20 seconds. Otherwise, Thailand
The time scale is 2.5 seconds. Rotation speed selection knob (potentiometer adjustment knob in figure 9)
P1). To set the rotation speed, select any number from 1 to 14.
Type N4 according to the number. A-4-1 to zero. Press C when finished. R-Rotate the chair to the right. When finished, take horizontal data. Shi = Rotate the chair to the left. When finished, take horizontal data. RHV - Rotate chair to the right. Horizontal and vertical ends
Take data. LHV-Rotate the chair to the left. Horizontal and vertical ends
Take data f. In the chair rotation test, the data is the rotation test and the chair rotation test.
Note that the child can be taken even after it has stopped.
It is possible. If vibration (block 1516) is selected, the chair will
It automatically vibrates in 4 cycles and the data shows the chair's luck.
The movement is captured. The steps are preferably as follows:
Ru. To recall the E-Chair exercise menu press the spacebar to start and press again to record.
Stop. T-time scale. 5,7.5.10.12゜5.1
5. Follow in 17.5 or 20 seconds. Otherwise,
The time scale is 2.5 seconds. Set the rotation speed selection knob to "vibration" position 1. A-Auto zero. Press C when finished. Perform T-test. As mentioned above, the dark side of the rotation test (block 1515)
, the operator can specify rotation using a fixed light.
data is extracted during chair rotation. preferable
The procedure is the same as described above for chair vibration, but
, the only exception is ``Turn the rotation speed selection knob to the vibration position.''
Change j to set the pupil as follows. Fixed light via switch S9 and slo in Figure 9A.
Position and turn on the light. Set the rotation speed selection knob to "Fixed Light 1". Assuming that the Visual Evoked Response (VER) test is selected (
block 1509), the preferred procedure is as follows:
be. The letters blinking on the display wheel load 38 in Figure 2 are normal VER.
Indicates the next test to be performed in the sequence. B8-Open both eyes, 128 flashes, once per second B4-Both eyes
Open, 64 flashes, once per second R4-Close right eye, 6
4 flashes, 1 per second [4-Close left eye, 64 flashes, 1
Once per second T (f, r) - number of flashes f (f is
16.32°64 or 128) and per second
VER using flash of light (" is 1/2.1 or 2)
Inspect. M (-> Turn on the display and select the magnification factor.
Bu. RFC - Record Display S - Recall Study Format Menu To summarize the above explanation, in each case the study administrator
Therefore, the specific test or group of tests selected
Dynamically controls the processor 34/software 36 of FIG.
given to the patient according to his command. In particular, prior art manual or
or semi-automated systems with pre-described procedures for each test.
(Typically, bulky and inconvenient instructions as mentioned above)
Operate various inspection equipment according to the manual)
inspection! ! The system of this invention
The instructions for each inspection listed above are displayed sequentially @@3
8 (Figure 2), it is truly self-contained.
Dynamic inspection 9! ! do luck the smallest amount of information
Miga inspection! ! Information requested by a member and such information is
Entered by the administrator using the keyboard 44. difference
In addition, the test supervisor should check the potentiometer adjustment knob in Figure 9A.
Parameters such as chair rotation speed can be input via P1 etc.
If required by the inspection program to give
Such information is provided by the integrated operator shown in Figure 9A.
Very quick and efficient setup using the controller 450
can be done. This automated inspection is performed using the integrated CEOG system.
Inspection V! Traditionally, these management methods have been relatively inefficient due to
Targeted follow-up tests, chair rotation test and visual evoked responses
(VER) Test management is very fast and efficient.
It can be done. Of course, the result is that a large number of patients will benefit from the integration of this invention.
handled by using the CEOG system
This means that it is possible. Furthermore, one aspect of this invention
The embodied CEOG system, as explained in detail above,
In addition, the test manager always controls the operator control section 45 in FIG. 9A.
1 or it by operating various controls of 0.
There is no option to perform the above specific tests manually.
It is very flexible in that it also has
Ru. Finally, either automatic or manual inspection management mode of operation
The accompanying test administrator or doctor can easily
Test results are displayed immediately in a graphical format that can be used
(display device M38 of the first cause). Inspection manager or
To immediately display useful test results to the accompanying doctor
Therefore,! ! The practitioner or doctor is responsible for ensuring that the test is performed correctly.
(2) it is possible to immediately determine whether the patient has
Whether the test stimulus was effectively received and responded to.
can be determined, and (3) therefore [further examination
Determine whether inspection (or repeat inspection) is necessary.
can be done. The analysis program of software 36 in FIG.
Let me explain with reference to the diagram. When you start the analysis program (
START block 1540), the next step is
It is done. Heading information is read from disk 42 (FIG. 1) (
block 1550). Heading information is displayed (block 1551). Message [Is this the right disc? ” is the print
(block 1552). Operator selects Y (for yes) or N (for no)
) (block 1553). If no, the system will get the correct disk.
(block 1554), and returns to block 1550. If yes, the system sends the message “Record
``Enter Number'' is printed (block 1555). The operator enters the record number rNJ (block 155
6). N is compared to zero (block 1557) and then also
If N is equal to or greater than zero, then N
The second two conditions are obtained from the disk (block 1559).
, on the other hand, if N is smaller than zero, then another judgment
A determination (block 1558) is performed. Especially if-
If 1 is less than or equal to N, the system
Return to TART (block 1550) and set the other
is greater than N, the system stops. Once the Nth record from the disk is obtained (the block
(1550), the system stores type and mode information.
Display (block 1560). A determination is made as to whether the VER check has been performed (block
Lock 1561). If VER (block 1562), the system
creates two channels with labels and scaling
Display block 1563) and Print route
Enter the (I!) section. If not VER, the data is the result of calibration.
(block 1564). Four chips with labels and scales are displayed.
(block 1565). Next, if the test is a follow-up test, the first half (H or
V) is displayed, and if chair rotation is requested, the chair
The printer speed is displayed (block 1566) and
The routine [・] is inserted. In the pudding[-routine, the following senuta is applied. "Group size" is printed (block 1567)
. The operator then sets the group size to N-1, 2,
Enter 3 (block 1558). In this regard, the print routine is configured so that the test question is a VER test.
You can enter it if you have it. The system sends the message ``Locate points and their array.''
The system that prints “Yo” (Pro-Tsuku 1569) is
A cursor is displayed (block 1570). Operator is 3 alphabetic characters S, E or F
(block 1571). When S is entered, the seat S (entered first) is saved.
(block 1572). A decision is then made regarding the size of the group (
block 1573). If the group size is equal to 1, the system will
page ``Insert Label'' (block 1574)
and the operator enters a character (block 1575);
The system will not display or block the labels you have entered in this way.
1576), and the system displays ``Show cursor''.
Return to (block 1570). If the group size is 2 or 3 (block 1573)
If so, no decision is made as to whether the group is complete.
(block 1577). When a group is completed, the next group is started (block
lock 1577), and then to "Show Cursor"
A return (block 1570) is performed. Return to “Show Cursor” if group is not completed
(Block 1570) is immediately performed. When the operator enters E (block 1571), the portion
Information is saved and the start of the next section is
(block 1579). The system says "Show cursor"
” (block 1570) Operator enters F
(at block 1571), the channel information is saved.
and the start of the next channel is performed (block 1
580) followed by channel less than 4 or 4
is equal to or greater than 4.
(block 1581). If the channel is less than or equal to 4, the cursor
II to “Display”! (Block 1570) is performed. On the other hand, if the channels are greater than 4, the system
Measure and display the speed and block 15B2>,
and print the message “Saving?” (Block 15
83). The operator then selects Y (yes) or N (no).
(block 1584). If no, the system reverts to “Show cursor”.
(block 1570), and on the other hand, if “Yes J”
For example, the system writes this record to disk (block
1585), then return to ``Show power'' (block
(1570). The inspection program in Figure 12A and the analysis program in Figure 12B
The program is a variety of computer programs 36 (Fig.
), preferably a mask control program,
Individual test programs for each EOG and VER test
program, and their respective EOG and VER inspections
realized by an individual main analysis program for
. To explain in more detail, the computer program shown in Figure 1
Program 36 is performed in the preferred embodiment as follows. Ma
disk control and stored formats (printout)
Program that calls the program (EOG) display format
RAM (EOGMAC) EOG Inspection Program (EOG
, BOB). VER inspection program (VERBOB). Main analysis program (for EOG test analysis) (EOGE
DT EDITING PROGRAM). Main analysis program (for VER test analysis) (VERE
DT). Display program (COR3OR). Numerous modifications and variations of the system of this invention will occur to those skilled in the art.
and therefore the true nature of this invention.
All such modifications and variations within the spirit and scope of
It is intended by the following claims to cover the form
Illustrated. 4. Brief explanation of the drawings Figure 1 is a diagram showing the appearance of the CEOG system of this invention.
be. Figure 2 shows a more detailed diagram of the CEOG system of this invention.
This is a diagram. Figure 3A is a preparatory diagram of the CEOG system in Figure 2.
width! 1 is an illustrative diagram of a circuit network 24. FIG. Figure 3B shows the front 1 amplification of the front station amplifier circuit network 24 in Figure 3A.
llA1. A2. ... is a detailed view of A6. Figure 4A shows amplifier network 2 of the CEOG system in Figure 2.
6 - FIG. 4B is an illustration of amplifier A11 of amplifier network 26 of FIG. 4A.
．． A12. ... is a detailed diagram of A16. Figure 5 shows the amplification ml1l route network of the CEOG system in Figure 2.
FIG. 6A is a schematic diagram of the bias circuit f846'' included in the CEOG system of FIG.
FIG. 6 is an illustration of the ADC section 56' of No. Figure 6B shows details of half of the converter A/DI in Figure 6A.
It is a diagram. FIG. 6C Converter stage 56 of the CEOG system of FIG.
2 is a schematic diagram of an address decode logic circuit 190 in FIG.
Ru. Figure 6D shows converter stage 5 of the CEOG system of Figure 2.
Further details of other ADC logic circuits 200 and 250 of 6.
FIG. Figure 6E shows converter stage 5 of the CEOG system in Figure 2.
FIG. 6 is a detailed view of the DAC section 300 of FIG. Figure 7A is the motor control device of the CEOG system in Figure 2.
1152 is an illustrative diagram. Figure 7B is the details of 7th construction Ilsey 7th 1326 in Figure 7A.
It is a diagram. FIG. 7C shows the chair interlock circuit 328 of FIG. 7A.
It is a detailed view. Figure 7D shows the dynamic brake relay 32 of Figure 7A.
FIG. 2 is a detailed diagram of No. 2. Figure 8 shows the relay panel 20 of the CEOG system in Figure 2.
This is an illustrative diagram. FIG. 9A shows the control panel 54 of the CEOG system of FIG.
FIG. Figures 9B to 9E show the CEOG system in Figure 2.
5 is a detailed view of the control panel 54. FIG. Figures 10A to 100 are the CEOG system i of Figure 2.
Detailed logic block diagram and circuit diagram 1 of the logic unit 62 of the system
be. Figures 1'lA to 11L) and 11G are
Details of the interface 30 of the CEOG system in Figure 2
FIG. 2 is a logical block diagram and circuit diagram. Figures 11E, 11F and 11H are the same as in Figure 2.
carried out at the interface 30 of the CEOG system.
write (data out) and read data, respectively.
timing diagrams related to interrupt operations.
Ru. Figures 12A and 12B respectively represent C of Figure 2.
Inspection realized by processor 34 of the EOG system
General flowchart for programs and analysis programs
Indicates the route. In the figure, 24 is a pre-amplifier circuit network, and 26 is an amplifier circuit.
46' is a bias circuit, 56 is a converter stage, 56
' is the ADC part, 190 is the address decode logic circuit,
200 and 250 are ADC logic circuits, 52 is motor control
control device, 326 is a fail-safe circuit, 328 is a chair
Interlock circuit, 322 is dynamic brake relay
-, 20 is the relay panel, 30 is the interface,
and 34 indicate a processor. Patent applicant Lopert Steven Ledley (et al.)
1 person)

Claims (1)

What is claimed is: An integrated medical testing system for automated management of test stimuli to a patient, the selection of which is responsive to an operator's selection of a desired stimulus to be applied to the patient. operator control means for providing a processor input signal corresponding to the processor input signal; processor means for generating a control signal representative of the desired stimulus to be provided in response to the processor input signal from the operator control means; stimulation control means for automatically administering said stimulation to said patient in response to said control signal from said means.