JPS58150196U - recording device - Google Patents
recording deviceInfo
- Publication number
- JPS58150196U JPS58150196U JP4479382U JP4479382U JPS58150196U JP S58150196 U JPS58150196 U JP S58150196U JP 4479382 U JP4479382 U JP 4479382U JP 4479382 U JP4479382 U JP 4479382U JP S58150196 U JPS58150196 U JP S58150196U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- signal
- converter
- processing unit
- recording
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Recording Measured Values (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来技術の構成図、第２図は、本考案の構成
図である。
１・・・ポテンショ、２・・・増幅器、３・・・オフセ
ット設定用つまみ、４・・・キーボード、５・・・演算
処理装置、６・・・Ｄ／Ａ変換器、７・・・増幅器、訃
・・記録紙。FIG. 1 is a block diagram of the prior art, and FIG. 2 is a block diagram of the present invention. DESCRIPTION OF SYMBOLS 1... Potentiometer, 2... Amplifier, 3... Offset setting knob, 4... Keyboard, 5... Arithmetic processing unit, 6... D/A converter, 7... Amplifier , death...record paper.
Claims (1)
且つ出力できる機能を有する演算処理装置、並びに該出
力であるディジタル信号をアナログ信号に変換するＤ／
Ａ変換器を具備して成る記録計に於て、演算処理装置へ
アナログ記録信号の他に、更に少なくとも任意に変更が
できるディジタル信号もしくは値が固定したディジタル
信号のいずれかを並列に入力させて両者の信号を論理的
演算を行ない、該演算結果を駆動部に伝達し記録するこ
とを特徴とする記録装置。Receives recording signals, performs calculation processing, stores calculation results,
and an arithmetic processing unit that has the function of outputting a digital signal, as well as a D/D converter that converts the digital signal that is the output into an analog signal.
In a recorder equipped with an A converter, in addition to the analog recording signal, at least either a digital signal that can be changed arbitrarily or a digital signal with a fixed value is input in parallel to the arithmetic processing unit. A recording device characterized in that a logical operation is performed on both signals, and the result of the operation is transmitted to a driving section and recorded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4479382U JPS58150196U (en) | 1982-03-31 | 1982-03-31 | recording device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4479382U JPS58150196U (en) | 1982-03-31 | 1982-03-31 | recording device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58150196U true JPS58150196U (en) | 1983-10-07 |
Family
ID=30055839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4479382U Pending JPS58150196U (en) | 1982-03-31 | 1982-03-31 | recording device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58150196U (en) |
-
1982
- 1982-03-31 JP JP4479382U patent/JPS58150196U/en active Pending
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