JPS58149567A - Processing system of merging of vector length control range - Google Patents

Abstract

PURPOSE:To optimize the processing without setting again contents of a vector length register, by checking precedence relations throughout plural vector length control ranges using the same vector register and merging length control ranges on condition that merging is impossible. CONSTITUTION:A source program 17 processed by a processor is interpreted in a source interpreting part 20 of a compiler 18 and is developed to an intermediate code, and addresses in a storage area are allocated to various appearing data by a storage area allocating part 21. Loop structures in this address-allocated program 17 are detected by a vector converting part 22, and parallel executable parts are recognized and are changed to the intermediate code. The program is subjected to the optimization for using effectively a vector processing processor in the level of the intermediate code by an intermediate code optimizing part 23, and registers (resources) on the vector processing processor are assigned by a register use determining part 24. By an object program output part 25, the machine language is outputted to an object program 19 and the optimization in the level of instruction words is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a vector length control range fusion processing method,
In particular, for vector processing processors equipped with multiple parallel processing units, a compiler that generates and supplies a target program from a source program can process multiple vectors with the same vector length.
The present invention relates to a vector-length control range fusion processing method for merging length control ranges into a single vector-length control range as much as possible.

(B) Technical Background and Problems An example of this is as shown in Figure 1 (A), where the elements al t a2 r... belonging to vector A and the elements b1 y b2 t... belonging to vector B. By adding the elements together, element c1. c2. ...Vector processing processors exist that execute vector instructions, such as generating a vector C. Figure 1 (
A) In the case shown, whether or not to perform mutual addition of the first element (Mask Niremen) ml p m2 #
. . , and the processing shown in FIG. 1 (CB) is performed.

One embodiment of a data processing system having a vector processing processor that performs the above processing has a system configuration as shown in FIG.

In the figure, 1 is a main storage device, 2 is a memory control device, 3 is a vector processing processor, 4 is a channel processor,
5 is a large storage device, 6 is a scalar processing circuit section, 7 is a vector processing circuit section, 8-0.8-1° . . . are floating point data registers, 9-0° 9-1. ... are vector registers 10-o each capable of storing a plurality of data (element data).

10-1. . . . are mask registers that can each store a plurality of mask data (mask element data), and 11 is a vector length register in which information on the number of elements stored in each vector register is set. 12-0 and 12-1 are memory access pipelines, 13 is an addition/subtraction pipeline, 14 is a multiplication processing pipeline, 15 is a division processing bike line, 1
6 is a mask processing pipeline 'Yff'.

When a vector processing processor as described above executes a process, a given source program is compiled and a target program is generated in a form suitable for execution by the processor. The configuration of the compiler that performs the compilation will be described later with reference to Figure 3.
In compiling processing by the compiler, the range that can be executed without resetting the contents of the vector length register when the vector processing processor executes processing is increased, and the overall processing is optimized. It is hoped that The vector length control range referred to in the present invention may be considered to be related to the range of program steps that can be executed without resetting the contents of the vector length register. This will be discussed later with reference to FIG.

(C) Purpose and structure of the invention The present invention aims to solve the above-mentioned problems.
Array data such as A (ID
The present invention is characterized in that the preceding order relationship of X, J) is checked, and if there are no conditions that prohibit merging, the plurality of vector length control ranges are fused. This will be explained below with reference to the drawings.

(1)) Embodiment of the Invention Fig. 3 shows the configuration of an embodiment of the compiler used in the present invention, Fig. 4 is an explanatory diagram illustrating the manner in which the source number is transferred to the globulum χ intermediate code (text) in the present invention. Fifth
The figure is an explanatory diagram explaining the vector length control range, Figures 6 to 12 are explanatory diagrams explaining the processing according to the present invention, and Figure 13 corresponds to the processing directly related to the present invention in the vectorization section. An example flowchart is shown below.

2, 17 is a source program stored in the large storage device, 18 is a compiler, 19 is a target program that is to be compiled and stored in the large storage device, 2
0 represents a source interpretation section, 21 a storage allocation section, 22 a vectorization section, 23 an intermediate code optimization section, 24 a register use determination section, and 25 a target program output section.

A compiler 18 takes in a source program 17 from a large storage device and generates a desired target program 19. At this time, each of the illustrated units performs the following processing.

That is, the source interpreter 20 takes in the source program 17 from the storage device, performs sentence interpretation, and develops it into an intermediate code (text). For example, if the source program is as shown on the left side of FIG. 4, it is developed into intermediate code as shown on the right side of the figure. The memory area allocation unit 21 allocates addresses χ in the memory area corresponding to various data appearing in the block diagram. The vectorization unit 22 detects loop structures in the program,
BWlj with the parallel executable part, and change the intermediate code as shown in FIG. The intermediate code optimization unit 23 levels the intermediate code and performs optimization for effectively utilizing the vector processing processor as shown in FIG. The processor group determining unit 24 determines the resources (registers) on the vector processing processor for the data appearing in the intermediate code.
Assign. The target program output unit 2'5 outputs machine commands to a large storage device and performs optimization at the command level.

A compiler for operating a vector processing processor has a configuration as shown in Figure 3, and compiles a given source program into a target program that allows the vector processing processor to execute processing in a preferred manner. I'm going to go.

This compilation includes processing to generate intermediate code as shown in Figure 5, and a DO loop performed while changing the value of ■ from 11'' to 1100'' as shown on the right side of Figure 5. A change to a vector text representation is performed. In this case, the range that can be processed without resetting the vector length (VLENG) set in the vector length register 11 (FIG. 2), for example, VLENG = 100 as shown in the figure, is insufficient. In the invention, this is called the vector length control range. The range of keys and brackets shown on the right side of FIG. 5 corresponds to one vector length control range.

When the vector processing processor executes processing, resetting the contents of the vector length register 11 (Fig. 2) corresponds to performing separate vector processing, and it is possible to From the viewpoint of processing optimization, it is desirable to perform all of the above processes in a single vector process.

That is, for example, a plurality of Ds as shown on the left side of FIG.
When there is a program with an o-loop, this corresponds to changing it into a single fused DO loop, as shown on the right side of FIG. Expressing this in a vector text expression, as shown by the white arrows in FIG. This corresponds to changing to a single vector length control range C on the condition that C is satisfied.

Hereinafter, a mode of checking whether the above-mentioned fusion is possible will be explained. FIG. 8 shows a case where fusion is possible, and the three vector length control ranges p + q ! shown on the left side of the figure are shown in FIG. r has the following relationship for array data A. That is, for example, when IDX=3,
Data A (4, J) is defined in the control range p, then data A (3, J) is defined in the control range q, and then data A (2, J) is defined in the control range r. ing. It is assumed that three vector length control ranges p + q + r'k having such a relationship are merged into a single vector length control range S shown on the right side of the figure.

The manner in which data A is defined on the storage area by the processing on the left side of the diagram in FIG. 8 is shown in FIG.
While the value of X is being updated, ■, ・■, ■, ...
-... Then, corresponding to the processing by the control range q, it is defined as ■, (island ■,...), and then the processing by the control range r It can be seen that data A is defined on the storage area by the processing on the right side of Figure 8. As shown in FIG. 9(B), while the value of IDX is being updated in the storage area 26 in response to the processing by the control range S,
■、■、■、■、・・・・・・・・・■、■・・・・・・
It is defined as...

As can be seen by comparing FIGS. 9(A) and (B)i, at the stage when the processing is completed, the contents of the location in the storage area 26, for example, where IDX=, are based on the processing by the control range r shown in FIG. 8. As shown in the processing on the left side of Figure 8 and the processing on the right side of Figure 8, a single vector
It can be seen that it may be merged into the length control range.

Figure io shows the case where fusion is not possible;
Vector range control range p+q+ shown on the left side of the diagram
rt- If the vector length control range S is merged into a single vector length control range S as shown on the right side of the figure, the following contradiction will occur.

Corresponding to the processing on the left side of FIG. 10, as shown in FIG. 11(A), while the value of IDX of data A is being updated in the storage area 26, ■, ■, ■, . . .・・・・・・１■
,■,■,・・・・・・・・・■,■,(■,・・・・
It is defined as... On the other hand, the first
In the case of the process on the right side of Figure 11, as shown in Figure 11 (B), while the value of IDX of data A is being updated in the storage area 26, ■, ■, ■, ■, etc.・・・・・・・・・IL
■p... It can be seen that it is defined as follows. In this case, the contents of the position indicated by IDX= are originally
Corresponding to the processing on the left side of Figure 10, the results should correspond to the processing using the vector length control range r, whereas in the case of the processing on the right side of Figure 10, the results are as shown in ■. ni A (IDX -1, J) - VRi...
It has been rewritten to correspond to... That is, the first
In the case shown in Figure 0, it can be seen that fusion is not possible.

When comparing the case shown in Fig. 8 and the case shown in Fig. 10, consider that all the vectors given by A(xDx+g, J) - 1 vector ri, When the preceding order relationships of the vectors are indicated by all the arrows, as shown in FIG. However, if there is a case in which the preceding order relationship follows the upward arrow in the figure as shown in FIG. 12 (B), it can be seen that the above fusion is impossible.

11- FIGS. 13(A) and 13(B), which together constitute one diagram, show an embodiment flowchart corresponding to processing directly related to the present invention in the vectorization unit.

The process is roughly as follows.

(1) Select a plurality of vector/length control ranges with the same vector/length.

(2) Extract array data A.

(3) Extract one vector length control range.

(4) Check whether there is a reference to array data A within the control range.

(5) Remember the citation mode, if any.

(6) When all the vector length control ranges are investigated, as shown in FIG. 13(B), determine the dependence of array data A, Move to dependencies between.

(8) Then, processing begins for the next array data.

(9) When the array data runs out, as shown in FIG. 13(B), items that have dependencies from bottom to top will not be combined.

(10) Then, merge those that have not become impossible to fuse.

Fusion is performed in the manner described above.

(E) As described in detail, according to the present invention, it is possible to compile a plurality of DO loops into one DO loop, so that when processing by a vector processing processor, the vector length is Processing such as resetting the contents of registers is simplified, making it possible to improve processing speed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram conceptually explaining the entire process corresponding to vector instructions, FIG. 2 is an example of a processing system having a vector processor according to the present invention, and FIG. 3 is an example of a compiler used in the present invention. Embodiment configuration, FIG. 4 is an explanatory diagram illustrating the mode of transferring a source program to intermediate code (text) in the present invention, FIG. 5 is an explanatory diagram illustrating the vector length control range, and FIGS. 12th
FIG. 13 is an explanatory diagram illustrating the entire process according to the present invention, and FIG. 13 is a flowchart of an embodiment corresponding to the process directly related to the present invention in the vectorization section. In the figure, 1 is a main storage device, 2 is a memory control device, 3 is a vector processing processor, 4 is a channel processor, 5 is a large storage device, 9 is a vector register, and IO is a mask.
Registers 11 to 16 are pipeline operation units, respectively;
17 is a source program, 18 is a compiler, 19 is an objective program, 20 is a source interpretation section, 21 is a storage allocation section, 22 is a vectorization section, 23 is an intermediate code optimization section, 24 is a register use determination section, 25 represents a target program output section. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) = 15- Figure 1 (A) (α1.α2...., αz) + (b,
shi2-)"'7reno)0(C+ l C27"・y C
l1) [-('rrLj z m2)"' 2m1)
]”” VAD ('Jector ADcl)
[witL wuxsk] Ritsu 12 Figure (A) INDE'l IE) X/2. N/A(I
DX+1. :J)--m- A (IDX, J)=--- A(IDX-7, J)=-m- CB) INDEXIDX/2. N/ A (IDX-1, J) = --- A (IEIX, J) = --- A (IDX + 1.σ) = -m- 436- JP-A-58-149567 (9) -437-

Claims (1)

[Claims] A compiler that generates and supplies a target program from a given source program to a vector processing processor that is equipped with a plurality of parallel processing units and at least a plurality of registers and executes vector instructions. The source interpretation section interprets the sentences and develops them into intermediate code, the storage allocation section allocates storage areas for various data that appears in the program, and the memory allocation section detects loop structures in the program and recognizes parts that can be executed in parallel. A vectorization unit that performs optimization and changes the intermediate code, an intermediate code optimization unit that performs optimization to effectively utilize the vector processing processor at the intermediate code level, and an intermediate code optimization unit that performs optimization to effectively utilize the vector processing processor at the intermediate code level; The vectorization unit includes a register used foot to allocate, and a target program output unit, and the vectorization unit extracts a plurality of vector length control ranges that make the vector length yt liJ. Focusing on any one array data within the vector length control range, record the preceding order relationship for the array data within the plurality of vector length control ranges, and record the preceding order relationship for all array data. A vector-length control range fusion processing method characterized by merging a plurality of vector-length control ranges into a single vector-length control range when the relationship is not in a fusion-impossible condition.