JPS58147080A - Input protection circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a semiconductor IC due to static electricity, by utilizing the breakdown of a semi-insulating substrate sandwiched by one conductive type semiconductor regions which are closely contacted each other. CONSTITUTION:Semiconductor regions 2 and 3 of n<+> type are formed in the GaAs semi-insulating substrate 1, and a Zener diode is formed between the substrate 1. Semiconductor regions 10 and 17 of n<+> type serving as a drain and a source, and an n<-> type semiconductor region 14 serving as a gate are formed in the substrate, and a metallic semiconductor (MES)-FET is formed of regions 10, 14 and 17. In this cnstitution, when the surge due to static electricity is impressed on an external input terminal 4, the voltage of a node N2 increases, and, when it exceeds the reverse breakdown voltage of the Zener diode in an equivalent circuit, breakdown generates between the regions 2 and 3. As a result, the voltage of a node N3 increases, and, when it exceeds the threshold voltage of the MES-FET 9, the FET 9 turns into an ''ON'' state and will drop the voltage of a node N4 down to the earth voltage. Therefore, high potential is prevented from being transmitted into the IC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection circuit for a Li-Ma compound semiconductor integrated circuit.

An embodiment of the present invention will be described below using an n-channel GaAs integrated circuit. FIG. 1 is a sectional view showing one embodiment of the present invention. In the same figure, (1) is 107 to 101
It is a semi-insulating GaAs substrate having a specific resistance of about 1Ω·1. (2) is the n formed in the semi-insulating substrate (1).
Is the 10-type semiconductor region (3) intertwined with the n10-type semiconductor region (2)? The contacted metal wiring layer (4) is an external input terminal of the integrated circuit, and (5) is a resistor R11 (one end connected to the external input terminal (4) and the other end connected to the metal wiring layer (3)).
6) is an n-type semiconductor region formed in the semi-insulating substrate (1) in close proximity to the n-type semiconductor region (2), and (7) is a metal in ohmic contact with the n-type conductor region (3). Wiring layer, (
8) is a resistor R2 whose one end is connected to the metal wiring layer (7) and the other end is connected to ground, and (9) is a normally-off type MES/FET (METal) formed in a semi-insulating substrate.
-3emiconductor FieldEffec
t Transistor), αQ is MES-FET
(9) is the n-type semiconductor region which becomes the drain, (b) is M
A metal wiring layer in ohmic contact with the drain QO of ES-FET (9), (2) is a resistor R3 whose one end is connected to the metal wiring layer (3) and the other end is connected to the metal wiring layer αυ.
, (to) is the metal wiring layer (11) at the internal input end of the integrated circuit.
connected to. α◆ is an n-type semiconductor region which becomes the gate of MES-FET (9), (g) is a gate electrode of MES-FET (+)) which is in rectifying contact with n-type semiconductor region α◆, and wiring layer ( 7). (To) is ME
The n+ type semiconductor region, a't), which becomes the source of the S-FET (9), is connected to ground through a metal wiring layer in ohmic contact with the n+ type semiconductor region Q. (to) is an insulating film.

FIG. 2 is an equivalent circuit of one embodiment of the present invention shown in FIG. In the figure, a is a stray capacitance Co connected to node N2.
, (e) are the n-domain semiconductor regions (
2), (6), and the equivalent circuit of the part consisting of the semi-insulating substrate between them. The value of the resistance R4eυ is n
The reverse breakdown voltage of the Zener diode ZD@ is determined by the distance between the ten-shaped semiconductor regions (2) and (6), their respective depths, and the specific resistance of the semi-insulating substrate (1), and the reverse breakdown voltage of the Zener diode ZD@ The carrier concentration in regions (2) and (6) and (2
) (6) Determined by the distance between them and their respective depths.

The operation of the input protection circuit configured as described above will be explained using FIG. In the figure, axis) is the waveform of voltage VN at node N, and (b) is the waveform of voltage VN at node N! voltage VN.

(c) is the waveform of voltage VN3 at node N3, (d
) shows the waveform of the voltage VN,' at the node N4.

Now, point 1. to t3, a surge due to static electricity as shown in FIG. 8(a) occurs at the external input terminal Nl of the integrated circuit.
Suppose that (4) is applied. The potential of the node N2 changes with a time constant determined by the resistor R1(5) and the stray capacitance CoH, and its level is also attenuated to some extent by R1(5) and CoQl. If the surge voltage is high enough, node N2
When the voltage VN2 rises to several tens of V at time t2, causing a reverse breakdown voltage of zD@ in the equivalent circuit shown in FIG.
), and a relatively large current flows between (2) and (3). As a result, the voltage VN3 of N3 is (
The current flowing between (2) and (3)) x (value of resistance Rz (8)) rises to a value determined by MES-FET (
When the threshold voltage of 9) is raised, the MESFEf19) turns on and attempts to lower the voltage at node N4 (to) to the ground voltage.

Therefore, since the voltage of node N4 (Ll is suppressed from increasing by MESFE 9), it is possible to prevent a high potential from being transmitted to the inside of the integrated circuit.

As described above, according to the present invention, an input protection circuit for an integrated circuit can be constructed by utilizing the breakdown of a semi-insulating substrate sandwiched between adjacent n-type semiconductor regions. I can bs.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is an equivalent circuit of FIG. 1, and FIG. 8 is a voltage waveform diagram for explaining the operation of the present invention. Regarding the figures, (1) is a semi-insulating substrate of a V-group compound semiconductor, (2) and (6) are n+ semiconductor regions, and (9) is a MES-FET% (5), (g) and (6).
is resistance. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 t, t2t3

Claims (3)

[Claims] (1) In an integrated circuit using a semi-insulating substrate made of a group IV compound semiconductor, a semiconductor device formed within the semi-insulating substrate and connected to an external input terminal of the integrated circuit via a first resistor. a first semiconductor region of one conductivity type; and a first semiconductor region formed in the semi-insulating substrate adjacent to the first conductivity type semiconductor region and connected to ground via a second resistor. a second semiconductor region of the same conductivity type as the conductivity type semiconductor region;
A MES-FE whose drain is connected to the first conductivity type semiconductor region through an eighth resistor, whose gate is connected to the second conductivity type semiconductor region, and whose source is connected to ground.
T(MEtal Sem1conductor Fie
ld Effect Transistor: metal, semiconductor field effect transistor), the above MES-FE
An input protection circuit characterized in that the drain of T is connected to an internal input terminal of an integrated circuit. (2) A transistor whose drain is connected to the first conductivity type semiconductor region via the eighth resistor, whose gate is connected to the second conductivity type semiconductor region, and whose source is connected to ground is an MIS-FET. The input protection circuit according to claim 1, characterized in that ξ. (3) A transistor whose drain is connected to the first conductivity type semiconductor region via the eighth resistor, whose gate is connected to the second conductivity type semiconductor region, and whose source is connected to ground is a J-FET (Junction Field Eff
2. The input protection circuit according to claim 1, wherein the input protection circuit is an ectTransistor.