JPS58145261A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve the efficiency of transmission, by adding violation for a N partial response code series of multivalued class. CONSTITUTION:A time division multiplex circuit 1 performs time division multiplex for input code series a-c. A multiplexed series (d) is applied with random- coding at a scrambling circuit 2, supplied to a serial/parallel conversion circuit 3, where the series is converted into code series (e) and (f). The series (e), (f) are given to an encoding circuit 4, encoded into a class N partial response code and given to a many-value conversion circuit 5. The circuit 5 converts this signal into a many-value code c'n and supplies it on a transmission line 6. Further, a received partial response code c''n is code-converted at a conversion circuit 7, the converted signals c'', f'' and n'' are given to a detection circuit 8, which detects block synchronism information and status information j', k' and l' of each channel. The signals are given to a descrambling circuit 10 through a parallel/serial conversion circuit 9 and serial/parallel-converted 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system that performs multi-value class (1), (1), (2), (2), (2), (2), (2), (2), (2) and (3) levels coding.

Generally, in order to transmit a 2-time division multiplexed code sequence from the transmitting side and separate it for each channel on the receiving side, redundant time slots are set on one time axis in addition to the time slot for main information transmission. A method is used in which the transmission side inserts synchronization information into the time slot, and the reception side separates each channel based on the inserted synchronization information. On the other hand, when sub-information such as status information indicating the status of each channel is transmitted together with main information, it is common to provide separate time slots for this sub-information. Accordingly.

Currently, when transmitting synchronization information and sub-information, it is necessary to reduce the transmission efficiency of the original main information.

It has been pointed out that when a class response encoding method is adopted, sub information can be transmitted without reducing the transmission efficiency of main information (Japanese Patent Application No. 1986-
No. 45.567). This method.

Consideration has been given to applying this method to a multilevel transmission system in which code sequences from multiple systems are multileveled and transmitted as a multilevel signal. Since multilevel signals contain information from multiple channels in a superimposed manner, it is difficult to detect the status information of each channel unless information that serves as a channel separation standard is also transmitted. Become.

An object of the present invention is to provide a data transmission method that can transmit sub-information such as block synchronization information and status information without reducing transmission efficiency by utilizing the characteristics of multivalued class ■/zoosal response code sequences. That's true.

A detailed explanation will be given below with reference to two drawings.

A transmitter according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. In FIG. 1, the transmitting section in this embodiment has a time division multiplexing circuit 1. In FIG. As shown in FIG. 2, this multiplexing circuit 1 has multiple systems (here,
low-speed input code sequences a, b, and C from three systems) are received in parallel.

It is converted into a time division multiplexed code sequence d. The input code sequences a, b, and C given to the multiplexing circuit 1 are composed of channels A, B, and C having the same transmission speed, respectively, and the multiplexing circuit 1 receives the input code sequence a.

Time division multiplexing is performed using a timing signal having a frequency three times that of signals b and c. The multiplexed sequence d is randomly encoded by the scrambler circuit 2 and supplied to the serial-to-parallel conversion circuit 3.

This conversion circuit 3 converts into two code sequences e and f. In FIG. 2, the code A/l in the code sequence e indicates that the code AI is a code after code conversion in the scrambler circuit 2, and other codes as well.

Assume that a similar relationship exists.

The code sequences e and f are applied to an encoding circuit 4 that performs class response encoding according to the present invention, which will be described in detail with reference to FIG.
encoded into a physical response code. The encoding circuit 4 has i? '/In order to intentionally disturb the response encoding rules and give a pie/can, the timing signal g + h + 1 + (Fig. 2) and the status according to the status of each channel are created. 4j,
, t is supplied from a communications subcircuit (not shown). Here, the timing signal g is a signal indicating the position on the time axis where the code of channel A exists for the code sequence e, and h indicates the next time slot following g for the code sequences e and f. The signal l is a signal indicating the next time slot.

The encoding circuit 4 performs processing to be described later on the code sequences e and f according to the signal g = t, and generates a 3-bit parallel signal e.
/ , (/ and W' are sent to the multi-value conversion circuit 5. The multi-value conversion circuit 5 converts this parallel signal into a 7-value multi-value code (class ■ze-Charles Ince code) C, The signal is supplied onto the transmission line 6. It is assumed that the transmission line 6 includes a waveform shaping circuit, a modulation/demodulation circuit, etc.

Referring to FIG. 3, the digital response encoding circuit 4 shown in FIG.
4-6.・AND circuits 4-7 to 4-1 for turn detection
0. OR circuit 4-11゜4-12, AND circuit 4-
13-4-17. Exclusive logic circuit 4-18. and an inverter circuit 4-19.

First, a multi-valued code an as shown in Table 1 can be defined for a combination of two manual code sequences e and f given to the encoding circuit 4.

For a code an generated by a combination of code sequences e and f, if the output code of the adder 4-1 is bn, then the output codes of the delay circuits 4-2, 4-3, and 4-4 are bn. -2, n-4, and bn-6, and performs code processing that satisfies the following relationship.

cn = bn 1) n-2 (1) Using the code sequence an indicated by L, bn is expressed as the following formula 1 formula % (2) However, ■ indicates that it is modulo 4 addition.

Now, as shown in Table 2, the relationship in equation (1) can be expressed by a combination of carry n and ψan by addition in equation (2).

The following plan Table 2 Referring to Table 2, when an-o and no.

co-0 and F), la, == l, if n=0.

cn-1; an-1, when n=1, r CH=-3. Similarly, y an== 2 + n ”' O
When.

When cn-2 and + &n-2+ n-1, cn-
It becomes 7. Furthermore, when + an”3 r n”O, co
-3 and v a n-3+ n-1 then rcn-1
It becomes.

Therefore, by code sequence afi and carry n.

It is possible to create a code corresponding to the class 2nd class code Cn. Here, H&B is code series e and f
Since it is a combination of , Cn is e.

It is produced by the combination of f and n.

Considering the point marked L, in FIG. 3, the code sequences e and f
In addition, the output signal n of the adder 4-1 that performs the addition of equation (2) is sent out in parallel. As is clear from this, adder 4-1. The delay circuit 4-2 works as a precoder.

Code sequences e, f, and n are each delay circuit 4-5.4
-6 causes a delay of 4 time slots. The delayed code sequences e' and f' are sent as they are to the multi-value conversion circuit 5 shown in FIG. On the other hand, the delayed series n' is inverted by 1 and supplied to the multi-value conversion circuit 5 as on' via an exclusive OR circuit 4-18 and an i/putter 4-19, which will be described later.

The multi-value conversion circuit 5 converts these three code series e/, (/, , / into multi-value class ■) 9-/Year response code string c according to the conversion rules shown in Table 3.
Convert to n'.

Table 3 As can be understood from Table 3, the code sequence cn' has 2
Information on code sequences e and f (FIG. 2) from the system is included in a temporally superimposed manner. Moreover.

As shown in FIG. 2, channels A/, .about.C'4 of code sequences a+b+c from three systems are scattered in each code sequence e, f. Therefore, to separate each channel A/, ~C'4 from the code system IJc'n.

Information that serves as a basis for separation is required. Here, A'1 is a combination of six channels in code sequences e and f in FIG.
= C'2; If A'3 to C'4 are called blocks, a specific channel in each block (for example, A'I
, A'2: A'3, A'4) are specified on the sending side.

By detecting this specific channel designation on the receiving side,
Each channel can be separated. Therefore, hereinafter, information serving as a reference for channel separation will be referred to as block synchronization information.

The encoding circuit 4 shown in FIG. 3 performs code processing according to the relationship shown in Table 2, and sends the multi-value class ■/9-Charless Ins code sequence c'n onto the transmission path 6 through the multi-value converter 5. However, the encoding circuit 4 according to the present invention further intentionally disturbs the aforementioned encoding rule, that is, performs a violation before transmitting.

This makes it possible to transmit not only status information (sub-information) that indicates the status of each channel, but also block synchronization information that serves as a reference when separating each channel on the receiving side. Moreover, even if the above-mentioned violation is performed, the transmission of the original main information of 9 will not be interfered with in any way.

The code processing described in No. 1 will be explained with reference to FIG.

First of all, in the class ■ Gunyarres I/Sne series,
It has been pointed out that there are several specific types of information that can provide a biased signal without affecting the transmission of the main information (Japanese Patent Application No. 567/1983).

If a violation is given to this pattern, the receiving side cannot detect two consecutive violations, so it identifies the violation as a violation.
11 have also been pointed out.

We will clarify that multiple types of information with different qualities can be transmitted in addition to the main information.

Table 11 Code a given by the relationship in Table 2. , bn code series, there are four cases shown in Table 4 where the above-mentioned specific pattern occurs in the code series cn.

However, in Table 2, only codes on the time axis that are two time slots apart from each other are focused, and adjacent codes are indicated by marks (x). This is an interleaved code series of class ■partial response codes.

This is because there is no need to consider adjacent codes. Further, in each case (1) to (4) of Table 1, the code sequence after the violation is shown as Cn.

Table 4 Case (1) Case (2) an z×
2×2×Oan z×2×2×Obn O×2×0×O
bn 3×1×3×3cn YX2X 2XOcn
YX 2X2XOCn YX-2X-2XOCn Y
X2X2XO case (3) case (4
)an Z×2×1×Oan zX2×3×Obn l
X3XOXOb, 2XOX3X3cnYX2X-3
XOcnYX-2X3XOCn YX-2X-3XOC
n YX2X3XO, where Z is <0.1, 2.3),
Y is -(0°±1.±2.±3) as above or -
It takes a certain value according to the social response encoding rule.

Now, in cases (1) to (4), the W code sequence cn according to the encoding rule differs from the code sequence Cn to which the violation has been added by only one code among the four codes. When a code sequence such as Cn is received on the receiving side, it can easily be violated in light of the encoding rule, and moreover, it is detected as two consecutive violations. therefore.

On the receiving side that receives this code sequence Cn, it can be distinguished from piracy caused by a single code error on the transmission path. Also, as is clear from Table 2, the code series C
Since both 2 and -2 on n are decoded to 2, even if sub-information is loaded by ``MyOreinyo/'' like the code sequence Cn, it does not affect the main information. therefore,
Information other than main information can be transmitted using the code sequence Cn.

Furthermore, the code sequences Cn in cases (1) and (2) and the case (3
) and (4) can be identified on the receiving side, information with different properties can be transmitted.

In the encoding circuit 4 shown in FIG. 3, the AI'lJD circuit 4-7 is a circuit for detecting the second turn of bn in case (1). Specifically, the output of the adder 4-1 is O, that is, (' o o ''), the output of the delay circuit 4-2 is 0 ("00"), and the output of the delay circuit is 2 (lO").
, and the output of the delay circuit 4-4 is 0 (oo), the AND circuit 4-7 sends out a logic "1" signal to its output. Similarly.

AND circuit 4-8 is case (2), AND circuit 4-9
In case (3), the AND circuit 4-1O works as a circuit for detecting the no or turn of each BN in case (4). next,
A case where block synchronization information is transmitted as information other than main information will be explained.

In the relationship of code system y'J e and l=signal g in FIG.

Since the position of the logic "l" part of the signal g and the code of channel A match, the first condition is that a violation be given at the timing of the logic "l" of the signal g.

Since the conditions for signal g can also be used as conditions for transmitting status information as sub-information different from the professional synchronization information of channel A, another condition is required as a block synchronization signal. As the second condition, the condition for the second turn of the code sequence bn in cases (1) and (2) is introduced. That is, in order to provide information that serves as a reference for block synchronization on the transmitting side, the signal g is
When "gutter/" in case (1) or case (2) is detected from the code series "l'', a violation can be given to the physical response code series Cn. FIG. The circuit shown in 4-7.4-8.4-11゜4
-13.4-17.4-18 is an example that realizes the above conditions. Here, when the output of the circuit 4-17 is logic '1'', the exclusive OR circuit 4-18 inverts the other input signal and outputs it. In case (1), r Cn
The sign of 2 is converted to -2.

In the above explanation. As conditions for cases (1) and (
The two conditions in 2) have been introduced, but simply to distinguish them from status information.

It is clear that either condition is better. but,
One of the reasons why class II nominal response codes are used even with redundancy in the amplitude direction is that the code series has a very good DC balance. When a violation is given to the normal response code in class ■, the DC balance is disrupted, but in the method of the present invention, there is very little disruption of the DC balance after the violation is given. Code sequence C in case (1) and case (2)
It is clear by comparing n, but if these are transmitted with equal probability.

It can be said that there is almost no collapse of DC balance, and the above conditions are satisfied in the two embodiments of the present invention.

Next, a method of transmitting status information of each channel will be explained. Referring to FIG. 2, it can be seen that the status information of channels A, B, and C can be provided at the timing of logic "1" of signals g, h, and i, respectively. However, since the condition of the signal g is one condition of the block peer information transmission means, other conditions are required to distinguish it from this condition. The conditions for the code sequence bn in cases (3) and (4) above are used as the conditions for the other corner.

The conditions for transmitting the status information of channel A are as follows: when the status signal j of channel A is logic 14j "l" and the logic of signal g is "1" (3
) or in case (4) when the bn/P turn is detected.
, . . . - It is sufficient to give the noyal response code ni-quiole/kan. The reason why both cases (3) and (4) are used here is to improve the DC balance, as explained in detail in the explanation of the method for transmitting the same amount of information in the previous section. It is.

In FIG. 3, circuits 4-9, 4-10, 1-12
4-14.4-17.4-18 is an example in which the above conditions are realized. Transmission of channel B status information is performed in the same manner as channel A, using the signals shown in FIG. 2 for channel B status signals.

Regarding channel C, the channel C status signal t,
Status information is similarly conveyed using signal 1 of FIG.

The code sequence including the above-mentioned block synchronization information and status information is sent to the transmission path 6 as a transmission code sequence.

On the receiving side, block synchronization information and status information corresponding to each channel are extracted from the received glyph response code sequence to which glyphs are intentionally added. A detailed explanation will be given below with reference to FIGS. 4 and 5.

Referring to FIG. 4, the reception unit according to the second embodiment of the present invention includes an analog-to-digital conversion circuit 7 that converts the received multi-level bar/response code received through the transmission path 6 into a 3-bit parallel signal. have. Here, since the received partial response code does not necessarily match the transmitted partial response code c'n, here,
Hail in ct. The conversion circuit 7 is c/, , n in Table 3.
Code conversion is performed according to the conversion rules for /, e/, and f', and a 3-bit parallel signal is sent out. The 3-bit parallel signal is the output signal e' of the encoding circuit 4 in FIG.
Since it corresponds to f′ and n′, ell , (11
, n11, respectively. Therefore, eIt, (
1/ represents the playback signs e and f in Figure 2, and n1
1 indicates the polarity of the sign.

The output signals eN, f''r and n are given to a detection circuit 8, which will be described later with reference to FIG. is detected.Still, the output signal eI
I, fII, and n〃 are given to the descrambler circuit 10 through the parallel-to-serial conversion circuit 9, and are applied to the serial-to-parallel conversion circuit 1 as a code sequence d' corresponding to the code sequence d in FIG.
1. This conversion circuit 11 decodes the code sequence d' into three code sequences a', b', c'.
and separate them and send them out.

In Fig. 4, there is a possibility that code errors may occur in the transmission path 6 in the reception/F-char response code sequence + c%, l, but the error rate is assumed to be at a level that can be used for normal data transmission. , It is also assumed that the timing for bit synchronization is also reproduced. Referring to FIG. 5, a detection circuit 8 according to an embodiment of the present invention is used to reproduce a block synchronization signal and a status signal of each channel.
2゜8-3, AND circuit 8-4.2 Time slot delay ・Circuit 8-5.8-6.・A for turn detection
ND circuit 8-7.8-10. OR circuit 8-11.8-1
2'.

8-14 is AND circuit 8-13.8-14, phase synchronized circuit 8-15. and AND circuits 8-16 to 8-18.

In Fig. 5, it is assumed that each input signal n#, e/7°f''u, represents a nosocial response code in a disortal manner according to the relationship shown in Table 3, and that there are no code errors on the transmission path. Assume that the partial response codes including the codes and turns of C1 in each of cases (1) to (4) described above are received one after another.

Circuit 8-7 is the cn pattern detection circuit in case (1).

c, = o The output of circuit 8-5 is -2 (2 time slots.

When a turn is detected, the output of the circuit 8-6 becomes -2 (4 time slots, when the received signal cn is -2) is logic “
The circuit 8-8 similarly detects the Cn pattern in case (2).The violation detection circuit 8-1 detects the following for each received code sequence in cases (1) to (4). Violations are detected as shown in the following.
-139456) Case (1) Case (2) Cn YX-2
x-2xOC, Yx2X2xO case (3)
Case (4) CnYX-2X-3XOCnYX2X3
XO (however, 0 indicates no violation, 1 indicates a grave) In other words, if a violation as shown in cases (1) to (4) is added, it will be detected as two consecutive violations on the receiving side, This can be distinguished from a violation caused by a code error on the transmission path. Even if a violation is intentionally added as described above, as is clear from the relationship in Table 3, both +2 and -2 of the partial response code need only be decoded as 2, so the polarity can be changed by adding the violation /. It can be seen that even if the data is reversed, it is correctly decoded, so there is no interference with the transmission of the original main information. For online code error monitoring, we can detect code errors with high accuracy by looking at each sporadically detected violation, excluding two consecutive violations. Possible (see Japanese Patent Application No. 56-36576).

Now, the circuit 8-4 in Fig. 5 corresponds to cases (1) to (4).
P-turn detection circuit.

If the output of the circuit 8-1 is O, and the pie ray 7 detected 2 time slots ago is 1, and the pie ray 7 detected 4 time slots ago is 1, the logic of the output is 1''.
'.

In other words, when the somewhat negative response code sequence to which a violation has been added in case (1) or case (2) is received, the circuit 8-13 becomes logic P1''.

As described above regarding the transmission of block synchronization information from the transmitter, this serves as a reference for extracting the code of channel A, a stepping stone, and a reference signal for block synchronization. Circuit 8-15
In order to achieve bit synchronization in the phase synchronization circuit, the reception timing "RT" regenerated on the reception side is phase synchronized with the reference signal for professional synchronization, and then the signals are shown at g, h, and i in Figure 1. The corresponding timings gL, h/, +L are generated. The circuit 8-9 is a circuit for detecting the sign/e turn of Cn in case (3).

Also, circuit +110 is a circuit that detects the sign/Pter/ of Cn in case (4), and the output of one circuit 8-14 (when the status information of any of the moss channels A, B, or C is detected, the logic It becomes l#.

On the transmitting side, the status information of channel A is sent only when the signal g in FIG. is obtained.

The status information of channel B is based on the signal shown in Figure 2.
Since it is sent only at the timing of 1", 2 circuits 8-1
Channel B status information is detected at the output of 7. Similarly, circuit 8 is used for the status information of channel C.
-18 output is detected.

Regarding FIG. 4, circuits 9, 10. To give some explanation about II, it was detailed earlier that the signals e and f are signals decoded into code sequences corresponding to e and f in FIG. It is a circuit that performs parallel-to-serial conversion based on the timing signal created using the received timing signal "RT" and the block synchronization signal, and is decoded into the code sequence d' corresponding to Fig. 1d by a descrambler with one circuit IO. Ru. The circuit 11 is a circuit that separates the signal d' into code sequences of channels A, B, and C based on the block synchronization signal. By intentionally adding violations according to the status information of each channel.

It is possible to transmit synchronization information and channel-corresponding status information without allocating redundant time slots on the time axis, and at the same time to monitor transmission line code errors online, thereby increasing transmission efficiency.

Remaining days below

[Brief explanation of drawings]

Fig. 1 is a block diagram of a transmitter according to an embodiment of the present invention that transmits code sequences of channels A, B, and C and status signals of each channel, and Fig. 2 is an example of time division multiplexing of code sequences of channels. Figure 6 shows the circuit used in Figure 2 to intentionally violate the passive response code sequence in order to transmit the block synchronization information and the status information of each channel. FIG. 4 is a block diagram of a receiving section according to the present invention, and FIG. 5 is a block diagram of a circuit for detecting a block synchronization signal and a status signal of each channel. In Figures 1 and 5, 1 is a time division multiplexing circuit, 2 is a scrambler circuit, 3 is a serial-to-parallel conversion circuit, 4 is a partial response encoding circuit, 5 is a multi-level conversion circuit, and 6 is a transmission line. , 7 is an analog-to-digital conversion circuit, 8 is a block synchronization signal and status signal detection circuit for each channel, 9 is a parallel-to-serial conversion circuit, 10 is a descrambler circuit, and 1 and 1 are separation circuits. Further, in FIGS. 3 and 5, 4-1 is an adder circuit. 4-2 to 4-6 are two time slot delay circuits. 4-7 to 4-10 are no and turn detection circuits, 4-11゜4
-12 is an OR circuit, 4-13 to 4-16 are AND circuits,
4-17 is an OR circuit, 4-18 is an exclusive OR circuit, 8
-1 is a violation detection circuit. 8-2.8-3 is a 2-time delay circuit. 8-4 is a pie ole/can/P turn detection circuit. 8-5.8-6 is a 2-time delay circuit. 8-7 to 8-10 are...! Turn detection circuit, 8-11. 8-12 is an OR circuit, 8-13.8-14 is an AND circuit, 8-15 is a phase synchronization circuit, 8-16 to 8-18 are AN
This is the D circuit.

Claims (1)

[Claims] 1. A transmitting side and a receiving side, where the transmitting side time-division multiplexes a code sequence given through a plurality of channels, and then generates an e-Charleshons code including an f IJ coder. A multilevel/physical response encoding circuit is used to construct and transmit a block containing information for multiple channels. In the data transmission method to separate. The transmitting side monitors the code sequence output from the glycoder, and when first and second specific patterns that are different from each other occur due to a combination of codes on the code sequence, the first and second specific patterns are detected. The receiving side has a circuit for giving a violation according to a second specific/mother turn, and the receiving side receives the transmitted signal. a circuit for demodulating a code sequence given a violation; and a first circuit for detecting the first and second specific signals.
a second detection circuit that receives a demodulation code sequence given the piorage and detects piorage that occurs twice in succession in the demodulation sequence; and first and second detection circuits. 1. A data transmission system comprising a circuit that performs block synchronization based on a signal detected by the circuit and obtains sub-information corresponding to each channel.