JPS58145209A - Delay line - Google Patents

Delay line

Info

Publication number
JPS58145209A
JPS58145209A JP2713582A JP2713582A JPS58145209A JP S58145209 A JPS58145209 A JP S58145209A JP 2713582 A JP2713582 A JP 2713582A JP 2713582 A JP2713582 A JP 2713582A JP S58145209 A JPS58145209 A JP S58145209A
Authority
JP
Japan
Prior art keywords
inductance element
delay line
conductor
bobbin
pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2713582A
Other languages
Japanese (ja)
Other versions
JPH0126203B2 (en
Inventor
Kazuo Kametani
一雄 亀谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmec Corp
Original Assignee
Elmec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elmec Corp filed Critical Elmec Corp
Priority to JP2713582A priority Critical patent/JPS58145209A/en
Priority to US06/467,635 priority patent/US4570135A/en
Publication of JPS58145209A publication Critical patent/JPS58145209A/en
Publication of JPH0126203B2 publication Critical patent/JPH0126203B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30Time-delay networks
    • H03H7/32Time-delay networks with lumped inductance and capacitance

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  • Coils Or Transformers For Communication (AREA)

Abstract

PURPOSE:To speed up the leading time, by specifying the shape of an inductance element, in a lump constant time delay line combining the inductance element and a capacitor. CONSTITUTION:A conductor 2 is wound around a rod shaped bobbin 1 having rectangular shape, T in thickness and W in width, in the lengthwise direction of the bobbin in a pitch P, with space winding of single solenoid, to form the inductance element 3. A capacitor C is connected between the conductor 2 and ground at each turn of the inductance element 3. The pitch P of the inductance element 3 and the winding width T at the shorter side has the relation of 0.2< P/T<1.9. Thus, the leading time is quickened.

Description

【発明の詳細な説明】 本発明はインダクタンス素子と容量を組合せてなる集中
定数型の遅延線に係り、特に立上り時1川が極めて速く
ディジタル回路等に好適な超高連作1線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lumped constant type delay line formed by combining an inductance element and a capacitance, and particularly to a super-high-contact single line that has an extremely fast rise time and is suitable for digital circuits.

従来、立上り時間の速い、例えば立上り時間がIns以
下の遅延線としては、同軸ケーブルを目的の遅延時間と
なる長さに切った構成のものや、メアンダーライン等の
分布定数回路の一種と考えられる構成のものが提案され
ている。しかし+iIjgは形状が大きく端末処理が面
倒であるし、後背は形状も大きく高価であるうえ特性か
良好でない等の理由から、いずれの遅延線も実用化され
ていない0また一方、インダクタンス素子と容量を組合
せた集中定数型遅延線もある。ところが、この構成の遅
延線は、高い使用周波数帯域(例えば1GHz以上)で
はインダクタンス素子が周波数特性を持つうえインダク
タンス素子のQも低下し、遅延特性と振幅特性が共に劣
化するので、立上がり時間がIns以下の高速遅延線を
得ることが困難となっていた。
Conventionally, delay lines with a fast rise time, for example, a rise time of less than Ins, have been constructed by cutting a coaxial cable to a length that provides the desired delay time, or are considered to be a type of distributed constant circuit such as a meander line. A configuration has been proposed. However, +iIjg has a large shape and terminal processing is troublesome, and the back is large and expensive, and its characteristics are not good, so none of the delay lines have been put into practical use.On the other hand, inductance elements and capacitors There is also a lumped constant delay line that combines However, in a delay line with this configuration, in a high operating frequency band (for example, 1 GHz or higher), the inductance element has a frequency characteristic and the Q of the inductance element also decreases, deteriorating both the delay characteristic and the amplitude characteristic, so the rise time is Ins. It has become difficult to obtain a high-speed delay line with the following characteristics.

本発明は以上の欠点を解消するためになされたもので、
超小型、超高速かつ安価な遅延線の提供を目的とする。
The present invention has been made to solve the above-mentioned drawbacks.
The aim is to provide an ultra-small, ultra-high-speed, and inexpensive delay line.

この目的を達成するために本発明は、導体にてスペース
を有するピッチPの単層ソレノイド状インダクタンス素
子を形成し、このインダクタンス素子の各ターン毎に前
記導体とアース間に容量を挿入接続するとともに、前記
インダクタンス素子のピッチPと短径方向の巻径Tとが
1 0.2 < P/T < 1.9なる関係に設定されて
なることを特徴とするものである。
In order to achieve this object, the present invention forms a single-layer solenoid-like inductance element with a pitch P having a space with a conductor, and inserts and connects a capacitor between the conductor and ground for each turn of this inductance element. , the pitch P of the inductance element and the winding diameter T in the minor axis direction are set to have a relationship of 1 0.2 < P/T < 1.9.

以下本発明の詳細な説明する。The present invention will be explained in detail below.

第1図は本発明の詳細な説明するための概略図であり・
第2図は第1図に示す遅延線の等価回路図である。第1
図において、厚さ■および幅Wの断面方形の棒状非磁性
ポビン1上に、導線2が長手方向にピッチPで単層ソレ
ノイド状にスペース巻きされインダクタンス素子3が形
成されている。なお、厚みおよび幅寸法T、Wは、正確
にはボビン1における厚み1幅方向の対向面上の導線2
の中心間の距離をいう。
FIG. 1 is a schematic diagram for explaining the present invention in detail.
FIG. 2 is an equivalent circuit diagram of the delay line shown in FIG. 1. 1st
In the figure, an inductance element 3 is formed by space-wound a conductive wire 2 in a single-layer solenoid shape at a pitch P in the longitudinal direction on a rod-shaped non-magnetic pobbin 1 having a rectangular cross-section and a thickness ■ and a width W. Note that the thickness and width dimensions T and W are, more precisely, the thickness and width of the conductor 2 on the opposite surface in the width direction of the bobbin 1.
The distance between the centers of

インダクタンス素子3の1ターンをインダクタンスLと
し、各ターン毎に導線2とアースの間に容置Cが挿入接
続され、1タ一ン分のインダクタンスLが遅延線の1区
間となっており、各インダクタンスしは第2図に示すよ
うに他のインダクタンスLと相互誘導結合している。な
お、第2図で・は最左端のインダクタンスしだけに関し
て、その右側にあるインダクタンスLとの結合を示して
いるが、当然その左側にもインダクタンスLがありかつ
それらとも同様に結合しており、他のインダクタンスL
も同様に左右のインダクタンスLと結合している。
One turn of the inductance element 3 is an inductance L, a capacitor C is inserted and connected between the conductor 2 and the ground for each turn, and the inductance L for one turn is one section of the delay line. The inductance L is mutually inductively coupled to another inductance L as shown in FIG. Note that in Fig. 2, only the leftmost inductance is connected to the inductance L on the right side, but naturally there is also an inductance L on the left side, and it is also connected to them in the same way. Other inductance L
are similarly coupled to the left and right inductances L.

そして各インダクタンスt、a、IIりのイ/ダクタン
スLト結合係数alで、2番目のインダクタンスとは鉛
で、・・・・・・・・・ n番目のインダクタンスとは
結合係数a1で結合している。
Then, each inductance t, a, and II is coupled with a coupling coefficient al, the second inductance is lead, and the nth inductance is coupled with a coupling coefficient a1. ing.

次に本発明の遅延線を検討する。まず結合係数a1+a
1+・・・・・・、aユを求める。
Next, consider the delay line of the present invention. First, the coupling coefficient a1+a
1+..., find ayu.

第1図のボビン1上面の幅Wの任意の1本の導線を基準
とし、ボビン上面における導線間の結合係数を、第3図
に示すように、順次に、、に、、・・・・・・。
Using any one conductor having the width W on the top surface of the bobbin 1 in FIG. 1 as a reference, the coupling coefficient between the conductors on the top surface of the bobbin is determined sequentially as shown in FIG. ....

kln ’ボビン下面における導線間の結合係数を順次
に1+に3+”””+ kln−1+ k、B+1とす
る。
kln' The coupling coefficient between the conducting wires on the lower surface of the bobbin is sequentially set to 1+, 3+"""+ kln-1+ k, and B+1.

ここで基準となる導線を流れる電流を考えると、−L面
の導線においては同方向であるので正の結合となり、下
面の導線に対しては逆方向となるので結合が各々負とな
る。その結合係数の絶対値は、導線間の距離が長くなる
程、小さくなる。
Considering the current flowing through the reference conductor, the currents flow in the same direction for the conductor on the -L plane, resulting in positive coupling, and the currents flow in the opposite direction for the conductor on the lower surface, so the coupling becomes negative. The absolute value of the coupling coefficient becomes smaller as the distance between the conducting wires becomes longer.

説明を簡単にするため、第1図Bに示す幅Wおよび厚み
Tの寸法を等しくすると、遅延線の各区間の間の結合係
数a++at+・・・・・・、anは、で示すことがで
きる。
To simplify the explanation, if the dimensions of width W and thickness T shown in FIG. .

遅延線の遅延特性は、主にこれら結合係数a1.a、。The delay characteristics of the delay line are mainly determined by these coupling coefficients a1. a.

ず結合係数a1について検討する。First, let us consider the coupling coefficient a1.

alの符号が正で、a、以下が存在しないと仮定した場
合、従来からの理論計算ではa、 =0.142 (誘
導m型のm=1.34に相当)が最適とされている。
Assuming that the sign of al is positive and there is no value below a, conventional theoretical calculations indicate that a = 0.142 (corresponding to m = 1.34 in the induced m-type) is optimal.

しかし実用上は、a、以下の結合の存在や浮遊容量の影
響を考慮しなければならず、結局a、=0.1〜02程
度の範囲で検討されていた。
However, in practice, it is necessary to take into account the existence of couplings below a and the influence of stray capacitance, and in the end, studies have been carried out in the range of about a=0.1 to 02.

一方、第3図における結合係数に1とに、を構成する3
本の導体が互いに等間隔(正3角形の各頂点)に位置す
る場合には、It<1=ktとなる。
On the other hand, when the coupling coefficient in Fig. 3 is 1, 3 constitutes
When the conductors of the book are located at equal intervals from each other (at each vertex of a regular triangle), It<1=kt.

従ってこのような条件の下において上述の(1)式は、
となる。そして結合係数りとに3の関係Fi1第3図か
ら明らかなようにに+>lk、1であるから、この条件
では必ず結合係数alI/ia+>Oとなる。すなわち
、同図におけるピッチPと厚み方向の寸法■の関係が、
T−(1/?J/2 ) pすなわちP/T=1.15
5ではal〉0であることが容易に分る。そしてこの条
件よりもP/Tが増加すると81=0の点を経てa I
< Oすなわちalは負となる。逆に、P/Tが1.1
55より減少すると81は単調に増加する。このように
P/Tを変化させると8.が増減する。
Therefore, under these conditions, the above equation (1) becomes
becomes. As is clear from FIG. 3, the relationship Fi1 between the coupling coefficient R and 3 is +>lk and 1, so under this condition, the coupling coefficient alI/ia+>O is always satisfied. In other words, the relationship between the pitch P and the dimension ■ in the thickness direction in the same figure is
T-(1/?J/2) p or P/T=1.15
5, it is easily seen that al>0. When P/T increases beyond this condition, it passes through the point of 81=0 and a I
<O, that is, al becomes negative. On the other hand, P/T is 1.1
When it decreases from 55, 81 increases monotonically. When P/T is changed in this way, 8. increases or decreases.

次に結合係数aIについて検討する。Next, the coupling coefficient aI will be considered.

a、は理論的には符号が負で、その絶対値が002〜0
03程度が良いとされている。これに対し第3図におけ
る各導体間の間隔から、結合係数kH+に4・k、は・
 lkl Dk+>lk+ 1の関係となり、これらの
絶対値がかなり接近しているこ七が判る。その結果・上
述の(2)式の分子の値が、かなり小さくなり・結合係
数a、も非常に小さくなる。また同図に示すピッチPが
減少すると81が正に増加する。
Theoretically, the sign of a is negative, and its absolute value is 002 to 0.
It is said that around 03 is good. On the other hand, from the spacing between each conductor in Fig. 3, the coupling coefficient kH+ is 4·k.
It can be seen that the relationship is lkl Dk+>lk+ 1, and these absolute values are quite close. As a result, the value of the numerator of the above equation (2) becomes considerably small, and the coupling coefficient a also becomes very small. Further, when the pitch P shown in the figure decreases, 81 increases positively.

また結合係数a++・・・・・・、amは〜上述の(3
)式および第3図から、 k t n−+ L:=k t n # k r n+
 iとなると考えられ、はとんど無視できる程度の値と
なる。
In addition, the coupling coefficient a++..., am is ~ the above (3
) formula and Figure 3, k t n-+ L:=k t n #k r n+
It is considered that i, and the value is almost negligible.

第4図は、幅Wと厚みTの寸法比W/Tをパラメータと
し、alではW/Tが1.10.100の場合について
、またa、およびa、にあってはW/Tが1の場合につ
いてP/Tとの関係を理論式から求めた特性図であり、
更に導線の線径をdとする七、第4図Aは線径dと厚み
Tの関係がd/T=0.02 (実用上の範囲で比較的
小さい比)の場合で、第4図Bは同じ< d/T=0.
9(実用上の範囲で最も大きくできる比)の場合で示し
である。
Figure 4 shows the case where W/T is 1.10.100 for al, and the case where W/T is 1 for a and a, using the dimension ratio W/T of width W and thickness T as a parameter. It is a characteristic diagram obtained from a theoretical formula for the relationship with P/T in the case of
Furthermore, the wire diameter of the conductor is d, and Figure 4A shows the case where the relationship between the wire diameter d and the thickness T is d/T=0.02 (a relatively small ratio within a practical range). B is the same < d/T=0.
9 (the ratio that can be maximized within a practical range) is shown.

同図からW/イが1、すなわちボビン1の断面が正方形
の場合から、W/Tが100、すなわちボビン1が非常
に薄い板状のものにおいて、更に、 d/Tが002、
すなわち導線の線径dを比較的細く選んだ場合から、d
yT25輸、9.すなわち導線の線径を非常に太く選ん
だ場合の実用上の広い範囲において、遅延線のピッチP
と厚みTの関係を適当に選定することにより、結合係数
81の最適値を容易に決定できる。その場合、結合係数
a!は遅延特性に殆んど影響しない程度の小さい正の値
に抑え、結合係数al以下を無視できる程度にすること
が可能となり、結合係数a、だけが存在する 誘導m型
遅延線に極めて近い特性を得ることができる。
From the same figure, when W/i is 1, that is, the cross section of bobbin 1 is square, W/T is 100, that is, when bobbin 1 is very thin and plate-shaped, d/T is 002,
In other words, if the wire diameter d of the conducting wire is selected to be relatively small, then d
yT25 export, 9. In other words, in a wide practical range when the wire diameter of the conductor is selected to be very thick, the delay line pitch P
By appropriately selecting the relationship between T and thickness T, the optimum value of the coupling coefficient 81 can be easily determined. In that case, the coupling coefficient a! is suppressed to a small positive value that has almost no effect on the delay characteristics, making it possible to make the coupling coefficient a and below negligible, and only the coupling coefficient a exists.Characteristics that are very close to those of an induced m-type delay line can be obtained.

もっとも、実際の遅延線を構成する場合には、遅延特性
がインダクタンス間の分布容量やインダクタンスに接続
する容量のリードが有するインダクタンス等によって影
響を受けるので、平担な遅延特性を有する遅延線を得る
ためには、結合係数a、=0.1〜02に選定する。さ
らに遅延線は)平担な遅延特性に限らず、外部回路の位
相補償を行なう目的から遅延特性に、傾斜を持たせる場
合もあるので、結局、結合係数a、=0.05〜0.2
5程度に選定することが実用的である。
However, when configuring an actual delay line, the delay characteristics are affected by the distributed capacitance between the inductances, the inductance of the capacitor lead connected to the inductance, etc., so a delay line with even delay characteristics is obtained. In order to achieve this, the coupling coefficient a is selected to be from 0.1 to 02. Furthermore, the delay characteristic of the delay line is not limited to a flat delay characteristic, but may have a sloped delay characteristic for the purpose of phase compensation of the external circuit, so the coupling coefficient a = 0.05 to 0.2
It is practical to select around 5.

そして第4図からも判るように、 W/Tとd/Tの値
の大きな範囲においても結合係数81を0.05〜0.
25の範囲にするためにP/Tを0.2(第8図A。
As can be seen from FIG. 4, even in a large range of W/T and d/T values, the coupling coefficient 81 can be set at 0.05 to 0.05.
P/T is 0.2 to make it in the range of 25 (Fig. 8A).

Q点)〜1.9 (第8図B、R点)の範囲に選定する
ことにより、目的の結合係数81を有するインダクタン
ス素子が容易に構成可能となる。
By selecting a value in the range from point Q) to 1.9 (points B and R in FIG. 8), an inductance element having a desired coupling coefficient of 81 can be easily constructed.

これらの関係をまとめると、インダクタンス素子のピッ
チPと厚み方向の寸法■とを 0.2 (P/T (1,9(5) の関係の範囲内に選定することにより、各種の州道 途に適する祐延線が得られることが判った。
To summarize these relationships, by selecting the pitch P and thickness direction dimension ■ of the inductance element within the range of the relationship 0.2 (P/T (1,9(5)), various state highways can be used. It was found that a suitable Yunobu wire could be obtained.

以上の遅延線に係る理論的検討をふまえて以下に本発明
の遅延線の具体的実施例を示す。
Based on the above theoretical study regarding the delay line, specific embodiments of the delay line of the present invention will be shown below.

第5図において、インダクタンス素子3は、幅がWより
僅かに短くかつ厚みもTより僅かに短い長方形の棒状非
磁性ボビン1の外周に、(5)式に基づいて、銀メツキ
裸導線2をピッチP、幅W、厚みTで単層ソレノイド状
に巻回されて構成されている。インダクタンス素子3の
各ターン毎に導線2とアース間には容量素子7が挿入接
続されている。この容量素子7は1ボビン1の下部に長
子方向に延びる誘電体板6と1この誘電体板5の下向、
に形成されたアース電極6と・上−面にインダクタンス
素子3のピッチPと同ピツチで形成された複数の容量電
極4からなっている。そして、インダクタンス素子3の
下部短辺側の導線2と、容量電極4とを半田リフロー法
等によって接続して遅延線8が構成されている。
In FIG. 5, the inductance element 3 is constructed by attaching a silver-plated bare conductive wire 2 to the outer periphery of a rectangular rod-shaped nonmagnetic bobbin 1 whose width is slightly shorter than W and whose thickness is also slightly shorter than T. It is wound in a single layer solenoid shape with pitch P, width W, and thickness T. A capacitive element 7 is inserted and connected between the conducting wire 2 and the ground for each turn of the inductance element 3. This capacitive element 7 includes a dielectric plate 6 extending in the longitudinal direction at the bottom of the bobbin 1, and a dielectric plate 6 extending downwardly from the dielectric plate 5.
A plurality of capacitor electrodes 4 are formed on the upper surface at the same pitch as the pitch P of the inductance element 3. The delay line 8 is constructed by connecting the conductive wire 2 on the lower short side of the inductance element 3 and the capacitor electrode 4 by a solder reflow method or the like.

このような構成の遅延線8は、インダクタンス素子3の
導線2の大部分がアース電極6から離れているため、過
電流によるインダクタンス素子3の損失が少なく、複数
個並列配置が容易であって高密度実装に適している。
In the delay line 8 having such a configuration, most of the conducting wire 2 of the inductance element 3 is away from the ground electrode 6, so there is little loss in the inductance element 3 due to overcurrent, and multiple pieces can be easily arranged in parallel, resulting in high performance. Suitable for density mounting.

発明者は、第5図に示す構成の遅延線において直径0.
06謔の銀メツキ裸銅線をピッチP0.411に、厚さ
TO,6fiW、幅W2闘で40回巻回し長さ16朋に
形成したインダクタンス素子3と、0.5PFの容量4
0個を有する容量素子7を組合せて実施したところ特性
インピーダンス100Ω、遅延時間2ns、立上り時間
150pS、 −3dB通過帯域23GHzノ特性を得
たO このように本発明の遅延線は、超小型で簡単な構造にも
かかわらず・超高速で・大きい値の遅延時間と立上り時
間の比(13,3程度)が得られ、従来の集中定数型遅
延線においては得られなかった良好な特性を実現できる
The inventor proposed that the delay line of the configuration shown in FIG. 5 has a diameter of 0.
An inductance element 3 is formed by winding 40 turns of silver-plated bare copper wire with a pitch P0.411, a thickness TO, 6fiW, and a width W2 to a length of 16mm, and a capacitance 4 of 0.5PF.
When this experiment was carried out using a combination of capacitive elements 7 having 0 elements, the characteristic impedance was 100 Ω, the delay time was 2 ns, the rise time was 150 pS, and the -3 dB passband was 23 GHz. Despite its structure, it is ultra-high speed and has a large delay time to rise time ratio (approximately 13.3), achieving good characteristics that were not possible with conventional lumped delay lines. .

なお本発明は、第6図のように、インダクタンス素子3
の各ターン毎に半田付は固定されて自立可能となってい
るので、遅延線8から非磁性ボビン1を引抜いて空心自
立構造で用いるならば、超高周波におけるボビン1の誘
電体損失を更に低減することができる。
In addition, in the present invention, as shown in FIG. 6, the inductance element 3
Since the solder is fixed for each turn and can stand on its own, if the non-magnetic bobbin 1 is pulled out from the delay line 8 and used in an air-core free-standing structure, the dielectric loss of the bobbin 1 at ultra-high frequencies can be further reduced. can do.

第6図は本発明の他の実施例を示すものである。FIG. 6 shows another embodiment of the invention.

この遅延線8は、断面長方形の非磁性ボビン1に導体条
21をピッチPで形成してインダクタンス素子3を構成
上、このインダクタンス素子3の厚みT側の導体条2′
を容量電極4′に兼用するとともに、誘電体板6を挾ん
でアース電極6に対向させて容量素子7と組合せて成る
ものである。
This delay line 8 is constructed by forming an inductance element 3 by forming conductor strips 21 at a pitch P on a non-magnetic bobbin 1 having a rectangular cross section.
is also used as a capacitive electrode 4', and is combined with a capacitive element 7 with a dielectric plate 6 sandwiched therebetween and facing the ground electrode 6.

この構成においてもピッチPおよび厚さTの関係を0.
2 < P/T < 1.9の範囲で選定すれば良好な
遅延特性が得られるし・また容量素子7の構成の簡素化
を図ることができる。
Also in this configuration, the relationship between pitch P and thickness T is 0.
If it is selected within the range of 2<P/T<1.9, good delay characteristics can be obtained and the structure of the capacitive element 7 can be simplified.

さらに本発明は、断面長方形のボビン1を用いる例に限
らず、例えば、第7図に示すような断面円形や断面楕円
形のボビンを用いることが可・能である。これらのボビ
ンにおいても円形の直径および楕円形の短径をTとして
、0.2 (P/T (1,9の関係でインダクタンス
素子3を構成すればよい。なお円形の直径は短径■のみ
からなると考えればよい。
Furthermore, the present invention is not limited to the example of using the bobbin 1 with a rectangular cross section, but it is also possible to use a bobbin with a circular or elliptical cross section as shown in FIG. 7, for example. In these bobbins as well, the diameter of the circle and the short axis of the ellipse are T, and the inductance element 3 may be constructed according to the relationship of 0.2 (P/T (1, 9). You can think of it as consisting of

第8図は本発明の更に他の実施例を示すものである。図
における遅延!fMは、非磁性ボビン1′として第6図
に示す如き棒状ボビン1に代えてトロイダル状ボビン(
図中2点鎖線で示す)を用い、このトロイダル状の非磁
性ボビン1′に導線2を単層ソレノイド状にスペース巻
きした(図中3ターンを示す)インダクタンス素子3を
備えてなるものである。この遅延線は、ボビン1′の内
周側ピッチP1と外周側ピッチP2が異なり、当然P 
+ <p lとなるが、上述の(5)式におけるピッチ
Pは1平均ピンチすなわち・P=(PI十P+ )/2
として上述の(5)式を適用すればよい。
FIG. 8 shows still another embodiment of the present invention. Delay in figure! fM is a non-magnetic bobbin 1' in which a toroidal bobbin (
(indicated by a two-dot chain line in the figure), and is equipped with an inductance element 3 (indicated by three turns in the figure) in which a conducting wire 2 is space-wound in a single-layer solenoid shape around this toroidal non-magnetic bobbin 1'. . This delay line has a different pitch P1 on the inner circumferential side and a pitch P2 on the outer circumferential side of the bobbin 1', and naturally P
+ < p l, but the pitch P in the above equation (5) is one average pinch, that is, P = (PI + P + )/2
The above equation (5) may be applied as follows.

このような構成の遅延線は・インダクタンス素子3の形
状は、枠形等の環状にも実施できるが、特にトロイダル
状のボビンを用いるならば、円弧状の固定接点列の形成
が可能となり、ボビンの中心を支点として可動接点がそ
の固定接点列上を極めて容易に摺動できるので、小型で
操作の簡単な可変遅延線を実現することができる。
The delay line with such a configuration can be formed into an annular shape such as a frame shape, but especially if a toroidal bobbin is used, it becomes possible to form an arc-shaped fixed contact array, and the bobbin Since the movable contacts can very easily slide on the fixed contact array using the center as a fulcrum, it is possible to realize a variable delay line that is small and easy to operate.

以上説明したように本発明の遅延線は、構造簡単で、形
状や導体線径等の設計上の自由度が大きく、かつ超高速
でしかも任意の遅延特性が得られるが、本発明はこれに
とどまらず、次の大きい特徴を有する。
As explained above, the delay line of the present invention has a simple structure, has a large degree of freedom in design such as shape and conductor wire diameter, is ultra-high speed, and can obtain arbitrary delay characteristics. It also has the following major features:

遅延線の遅延特性を決定する結合係数がすべて遅延線を
構成する寸法の絶対値ではなく・寸法の比で決定される
とともに、1延線を構成する寸法と緒特性の関係が明快
に得られる。すなわち、遅延線を構成する諸寸法をすべ
て1/Sに比例して小さくする(但、容量Cもl/8の
値にする)と、特性インピーダンスは変らず、遅延時間
と立上り時間は1/5(−3dE1通過帯域は8倍)に
・取付面積は1/8“に一体積は1/8″になる。
The coupling coefficients that determine the delay characteristics of the delay line are determined not by the absolute values of the dimensions that make up the delay line, but by the ratio of the dimensions, and the relationship between the dimensions that make up one extension line and the characteristics can be clearly obtained. . In other words, if all the dimensions constituting the delay line are reduced in proportion to 1/S (however, the capacitance C is also set to a value of 1/8), the characteristic impedance remains unchanged and the delay time and rise time become 1/S. 5 (-3dE1 passband is 8 times) - The installation area is 1/8" and the volume is 1/8".

このことは・本発明の遅延線は微細化することにより、
飛躍的に高速化と高密度化が実現で゛きることを意味す
る。そして、本発明の遅延線に用いるインダクタンス素
子3は、非常に単純な構造を有し微細加工に適するもの
である。例えば導線の巻回のほか1、アルミナ磁器等の
非磁性ボビンの表面にメッキ加工等によって導体層を形
成した後、ボビン表向を機械的精密研削、フォトエツチ
ングもしくはレーザービーム加工等、従来知られた手段
によって単層ソレノイド状のインダクタンス素子を形成
することも可能であり、導線等の導体の断面形状も任意
である。さらに容量素子7もインダクタンス素子3の上
に誘電体および電極を高速スパッタリング等で容易に形
成することが可能である。
This means that by miniaturizing the delay line of the present invention,
This means that it will be possible to dramatically increase speed and density. The inductance element 3 used in the delay line of the present invention has a very simple structure and is suitable for microfabrication. For example, in addition to winding a conductor wire, 1. After forming a conductive layer on the surface of a non-magnetic bobbin such as alumina porcelain by plating, etc., the surface of the bobbin is subjected to mechanical precision grinding, photo etching, or laser beam processing, etc. It is also possible to form a single-layer solenoid-like inductance element by other means, and the cross-sectional shape of the conductor such as a conductor wire can also be arbitrary. Furthermore, the capacitive element 7 can also be easily formed with a dielectric material and an electrode on the inductance element 3 by high-speed sputtering or the like.

また・本発明の遅延線は、非磁性ボビン上の導体条に固
定接点列を形成し、この上を可動接点を摺動させるなら
ば・超高速の可変遅延線が得られる0 以上説明したように本発明の遅延線は、立上り時間In
s付近で限界に達していた遅延特性を飛躍的に向上させ
、遅延特性の高速化および構造の小型化・高密度化を実
現した。
Furthermore, in the delay line of the present invention, if a fixed contact array is formed on a conductor strip on a non-magnetic bobbin and a movable contact is slid on this, an ultra-high-speed variable delay line can be obtained. The delay line of the present invention has a rise time In
The delay characteristics, which had reached their limit near s, have been dramatically improved, achieving faster delay characteristics and a smaller, more dense structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の詳細な説明する概略図お
よびその等価回路図、第3図は第1図に示すインダクタ
ンス素子における導体間の結合関係を説明する図、第4
図はインダクタンス素子におけるピッチPに対する巻径
Tの比と結合係数の関係を示す特性図、第5図は本発明
の遅延線の正 一実施例を示す部分平面図および側面図、第6図および
第8図は本発明の遅延線の他の実施例を7ドす部分÷面
図および側面図、第7図は本発明のインダクタンス素子
に用いるボビンの実施例を不す図である。 1・・・・・・ボビン・2,2′・・・・・・導体(導
線、導体条)3・・・・・・インダクタンス素子、7・
・・・・・容量素子、P・・・・・・ピッチ、■・・・
・・・ボビンの短径方向の巻径・a++・・・、aユ・
・・・・・結合係数特許出願人 エルメック株式会社 ヤ 1 図 (A)               CB)ヤ 2 
図 ヤ 3 図 ヤ 5 図 ヤ 6 図 ヤ 8 図 1′
1 and 2 are schematic diagrams explaining the present invention in detail and their equivalent circuit diagrams, FIG. 3 is a diagram explaining the coupling relationship between conductors in the inductance element shown in FIG. 1, and FIG.
The figure is a characteristic diagram showing the relationship between the ratio of the winding diameter T to the pitch P and the coupling coefficient in an inductance element, FIG. 5 is a partial plan view and side view showing a positive embodiment of the delay line of the present invention, and FIGS. FIG. 8 is a partial cross-sectional view and a side view of another embodiment of the delay line of the present invention, and FIG. 7 is a diagram showing an embodiment of the bobbin used in the inductance element of the present invention. 1...Bobbin 2, 2'...Conductor (conductor wire, conductor strip) 3...Inductance element, 7...
... Capacitive element, P ... Pitch, ■ ...
... Winding diameter in the short diameter direction of the bobbin, a++..., ayu...
... Coupling coefficient patent applicant Elmec Co., Ltd. Ya 1 Figure (A) CB) Ya 2
Figure 3 Figure 5 Figure 6 Figure 8 Figure 1'

Claims (5)

【特許請求の範囲】[Claims] (1)導体にてスペースを有するピッチPの単層ソレノ
イド状インダクタンス素子を形成シ、このインタリタン ス素子の各ターン毎に前記導体とアース間に容量を挿入
接続するとともに、前記インダクタンス素子・のピッチ
Pと短径方向の巻径Tとが、0.2 (P / T (
1,9 なる関係に設定されてなる遅延線。
(1) Form a single-layer solenoid-like inductance element with a pitch P having a space with a conductor, insert and connect a capacitor between the conductor and the ground for each turn of this inductance element, and connect the inductance element with a pitch P of the inductance element. and the winding diameter T in the minor axis direction is 0.2 (P / T (
A delay line set in the relationship 1,9.
(2)  インダクタンス素子の導体が、非磁性ボビン
に形成されてなることを特徴とする特許請求の範囲第1
項記載の遅延線。
(2) Claim 1, characterized in that the conductor of the inductance element is formed on a non-magnetic bobbin.
Delay line as described in section.
(3)  インタフタンス素子が、空心自立構成されて
なることを特徴とする特許請求の範囲第1項の遅延線〇
(3) The delay line according to claim 1, characterized in that the interface element has an air-core self-supporting configuration.
(4)  インダクタンス素子が、環状に形成されてな
ることを特徴とする特許請求の範囲第1項もしくは第2
項記載の遅延線。
(4) Claim 1 or 2, characterized in that the inductance element is formed in an annular shape.
Delay line as described in section.
(5)  インダクタンス素子の導体が、トロイダル状
のボビンに形成されてなることを特徴とする特許請求の
範囲第4項記載の遅延線。
(5) The delay line according to claim 4, wherein the conductor of the inductance element is formed in a toroidal bobbin.
JP2713582A 1982-02-22 1982-02-22 Delay line Granted JPS58145209A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2713582A JPS58145209A (en) 1982-02-22 1982-02-22 Delay line
US06/467,635 US4570135A (en) 1982-02-22 1983-02-18 Delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2713582A JPS58145209A (en) 1982-02-22 1982-02-22 Delay line

Publications (2)

Publication Number Publication Date
JPS58145209A true JPS58145209A (en) 1983-08-30
JPH0126203B2 JPH0126203B2 (en) 1989-05-23

Family

ID=12212604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2713582A Granted JPS58145209A (en) 1982-02-22 1982-02-22 Delay line

Country Status (1)

Country Link
JP (1) JPS58145209A (en)

Also Published As

Publication number Publication date
JPH0126203B2 (en) 1989-05-23

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