JPS5814231U - random access circuit - Google Patents
random access circuitInfo
- Publication number
- JPS5814231U JPS5814231U JP10565581U JP10565581U JPS5814231U JP S5814231 U JPS5814231 U JP S5814231U JP 10565581 U JP10565581 U JP 10565581U JP 10565581 U JP10565581 U JP 10565581U JP S5814231 U JPS5814231 U JP S5814231U
- Authority
- JP
- Japan
- Prior art keywords
- mirror
- access
- frame number
- circuit
- pickup
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の一実施例に係る回路ブロック図を示す。
主な図番の説明、１・・・フレーム番号設定回路、２・
・・フレーム番号ラッチ回路、１３・・・アップダウン
カウンタ、１０・・・アクセス終了検出回路。The figure shows a circuit block diagram according to an embodiment of the present invention. Explanation of main drawing numbers, 1...Frame number setting circuit, 2.
... Frame number latch circuit, 13... Up/down counter, 10... Access end detection circuit.
Claims (1)
の設定出力と再生フレーム番号をラッチするラッチ回路
のラッチ出力とを比較して指定フレームに先行するミラ
ーアクセス範囲にピックアップを強制移送せしめると共
にミラーアクセス範囲を再生する前記ピックアップのト
ラッキングミラーの飛越を制御して指定フレームへのア
クセスを為すランダムアクセス機構に於て、ミラーアク
セス後ミラーアクセス範囲を外れる度に指定フレーム番
号をカウントダウンする前記フレーム番号設定回路と、
ミラーアクセス後ミラーアクセス範囲を外れる度にカウ
ントアツプし設定出力とラッチ出力が一致した後フレー
ム周期でカウントダウンするアップダウンカウンタと、
設定出力とラッチ出力が一致した後前記アップダウンカ
ウンタが初期状態となったことを検出してスチル再生用
の飛越パルスを発するアクセス終了検出回路とをそれぞ
れ配して成るランダムアリセス回路。Compares the setting output of a frame number setting circuit that sets and stores the designated frame number with the latch output of the latch circuit that latches the playback frame number, and forcibly moves the pickup to the mirror access range preceding the designated frame and sets the mirror access range. In the random access mechanism that controls skipping of a tracking mirror of the pickup to be reproduced to access a designated frame, the frame number setting circuit counts down a designated frame number each time the pickup exits a mirror access range after accessing the mirror;
An up/down counter that counts up each time the mirror access range is removed after mirror access, and counts down at frame intervals after the set output and latch output match;
A random access circuit comprising an access end detection circuit which detects that the up/down counter is in an initial state after a set output and a latch output match and generates a skip pulse for still reproduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10565581U JPS5814231U (en) | 1981-07-15 | 1981-07-15 | random access circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10565581U JPS5814231U (en) | 1981-07-15 | 1981-07-15 | random access circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5814231U true JPS5814231U (en) | 1983-01-28 |
| JPS6346930Y2 JPS6346930Y2 (en) | 1988-12-05 |
Family
ID=29900184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10565581U Granted JPS5814231U (en) | 1981-07-15 | 1981-07-15 | random access circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814231U (en) |
-
1981
- 1981-07-15 JP JP10565581U patent/JPS5814231U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6346930Y2 (en) | 1988-12-05 |
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