JPS58138439U

JPS58138439U - timer device

Info

Publication number: JPS58138439U
Application number: JP3475482U
Authority: JP
Inventors: 島野　圭司
Original assignee: セイコーインスツルメンツ株式会社
Priority date: 1982-03-12
Filing date: 1982-03-12
Publication date: 1983-09-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の実施例を示すブロック図で、第２図は
本考案のさらに詳細な実施例を示す回路ブロシク図であ
る。１・・・・・・受信回路、２・・・・・・アラート符号
判別回路、３・・・・・・操作部、４・・・・・・クロ
ック回路、５・・・・・・時刻データ一致判別回路、６
・・・・・・外部装置制御回路、−７・・・・・・操作
部、８・・・・・・第１の時刻データ記憶回路、９・・
・・・・第２の時刻データ記憶回路、１０・・・用第１
の時刻データ一致判別回路、１１・・・・・・発振回路
、１２・・・・・・クロック回路、１３・・・・・・オ
アゲート、１４・・・・・・Ｒ−Ｓフリップフロップ、
１５・・・・・・トランジスタ、１６・・・・・・リレ
ー、１７・・・・・・外部装置、１８・・・・・・第２
の時刻データ一致判別回路、１９・・・・・・オアゲー
ト、２０・・・・・・高周波回路部、２１・・・・・・
検波回路部、２２・・・・・・増幅回路、２３・・・・
・・アラート符号判別回路、２４・・・・・・タイマー
回路。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit block diagram showing a more detailed embodiment of the present invention. 1... Receiving circuit, 2... Alert code discrimination circuit, 3... Operating unit, 4... Clock circuit, 5... Time Data match determination circuit, 6
. . . External device control circuit, -7 . . . Operation unit, 8 . . . First time data storage circuit, 9 .
...Second time data storage circuit, first for 10...
11...Oscillation circuit, 12...Clock circuit, 13...OR gate, 14...R-S flip-flop,
15...Transistor, 16...Relay, 17...External device, 18...Second
time data coincidence determination circuit, 19...OR gate, 20...high frequency circuit section, 21...
Detection circuit section, 22...Amplification circuit, 23...
...Alert code discrimination circuit, 24...Timer circuit.

Claims

[Scope of utility model registration request]

The alert system includes a receiving section capable of receiving an emergency warning broadcast, an alarm code discrimination circuit, a clock circuit and a time data coincidence discrimination circuit, and an external device control circuit connected to the time data coincidence circuit on the alert code discrimination circuit. A timer device configured such that an external device control circuit operates preferentially when a code discrimination circuit operates.