JPS581310A - Driving circuit for automatic gain adjusting circuit - Google Patents

Driving circuit for automatic gain adjusting circuit

Info

Publication number
JPS581310A
JPS581310A JP9998781A JP9998781A JPS581310A JP S581310 A JPS581310 A JP S581310A JP 9998781 A JP9998781 A JP 9998781A JP 9998781 A JP9998781 A JP 9998781A JP S581310 A JPS581310 A JP S581310A
Authority
JP
Japan
Prior art keywords
circuit
amplifier
thermistor
time constant
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9998781A
Other languages
Japanese (ja)
Inventor
Susumu Kubo
進 久保
Isamu Kishi
岸 勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9998781A priority Critical patent/JPS581310A/en
Publication of JPS581310A publication Critical patent/JPS581310A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/005Control by a pilot signal

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To eliminate variance of response characteristics by allowing an AGC circuit which uses a thermistor to have a sufficiently great time constant. CONSTITUTION:A pilot signal extracted through a pilot filter 1 is converted by a rectifier 3 into a direct current. This DC component is inputted to a DC amplifying circuit 7, whose output is amplified by an amplifier IC to control a transistor TR. Consequently, the current flowing through a thermistor 5 is controlled to hold the level of the pilot signal constant. To the feedback path of the amplifier IC, a capacitor C is connected, and the DC amplifying circuit 7 constitutes an analog integrating circuit having a large time constant. Therefore, variance of the response characteristics of the thermistor 5 are made much less than the time constant of the whole circuit.

Description

【発明の詳細な説明】 本発明は、自動利得g*回路1動回路、特にサ一(スタ
を用いて自動利得調整回路(以下AGCという)を構成
させたものにおいて、サーミスタに電流を供給する直流
増幅器に積分機能を附加し。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for supplying current to a thermistor in an automatic gain g* circuit, particularly in an automatic gain control circuit (hereinafter referred to as AGC) using a thermostat. Integration function added to DC amplifier.

サーミスタを含めたAGC全体の時定数をバラツキ少な
く設定できるようにした自動利得調整回路駆動回路に関
するものである。
The present invention relates to an automatic gain adjustment circuit drive circuit that allows the time constant of the entire AGC including the thermistor to be set with less variation.

従来から伝送システム内与こAGC’)挿置して利得を
所定レベル辷調整することが行なわれており。
Conventionally, an AGC') has been inserted into a transmission system to adjust the gain to a predetermined level.

例えばiイタ−波伝送システムにおいてはマイクρ波の
瞬断現象も奔在することなどからパイロット信号を一緒
に乗せ、当該パイロット信号によりてAGCを働らかせ
ると共に上記マイグー波伝送システムでの障害を検出す
ることが行なわれている。
For example, in an i-wave transmission system, there are many instantaneous interruptions of microphone ρ waves, so a pilot signal is added to the i-wave transmission system, and the pilot signal activates the AGC and eliminates the disturbance in the mi-goo wave transmission system. Detection is being carried out.

上記の如きAGCにおいて0例えば上記パイロット信号
を増幅してサーi六夕に流れる電流を制御し、伝送路中
にもうけられた利得調整部の利得を調整することが行な
われているが、4t−−ミスタ□ 自体の応答時定数が
比較的大きいこともあってAGC全体の時定数、が上記
す−ミスタ自体の時定数で決定され、バッフ中の大きい
ものとなっていた。
In the above AGC, for example, the pilot signal is amplified to control the current flowing through the circuit, and the gain of the gain adjustment section provided in the transmission path is adjusted. Since the response time constant of the -mister□ itself is relatively large, the time constant of the entire AGC is determined by the time constant of the -mister itself, which is the large one in the buffer.

本発明は、上記の点を解決することを目的としておf)
、AGC内の直流増幅器に積分機能を附加し、必要な時
定数を与えるに当って比較的小さい容量を用いて設計で
きるようにし、直流増幅機能と積分機能と管兼ね与える
ようにすることf目的としている。そしてそのため1本
発明の自動利得輿瞥回路駆動回路は、信号電流が流通す
る伝送路中にもうけられた利得調整部に対して、上記信
号電流の一部を抽出して当該信号電流の一部の信号レベ
ルに対応した帰還を行なう自動利得5kis回路におい
て、上記抽出された信号電流の一部に対応した入力信号
を増幅する直流増幅器と該直流増幅器の出力によって駆
動されて上記利得調整部tm御するサーミスタとをそな
えると共に、上記電流増幅器は、容量性帰還回路をそな
え、上記サーミスタに流れる電f11を制御すると共に
上記入力信号を積分する積分囲路として動作すること全
特徴としている。以下図面管参照しつつ説明する。
The present invention aims to solve the above points.
, To add an integral function to the DC amplifier in the AGC, so that it can be designed using a relatively small capacity to provide the necessary time constant, and to provide the DC amplifier function, integral function, and tube. It is said that For this reason, (1) the automatic gain control circuit driving circuit of the present invention extracts a part of the signal current to a gain adjustment section provided in a transmission line through which the signal current flows. In the automatic gain 5kis circuit that performs feedback corresponding to the signal level of , there is a DC amplifier that amplifies an input signal corresponding to a part of the extracted signal current, and a gain adjustment section tm driven by the output of the DC amplifier. The current amplifier is characterized in that it is provided with a capacitive feedback circuit and operates as an integrating circuit that controls the current f11 flowing through the thermistor and integrates the input signal. The explanation will be given below with reference to the drawings.

第1図は本発明の一実施例構成、72図および第3図は
第1図図示構成の動作を説明する説明図を示す。
FIG. 1 shows a configuration of an embodiment of the present invention, and FIGS. 72 and 3 are explanatory diagrams for explaining the operation of the configuration shown in FIG. 1.

才1図゛において、lはパイーット・フィルタ。In Figure 1, l is a pilot filter.

2は交流増幅器、3は整流器、4は比較器であって上記
パイロット信号の単なる瞬断時でなく伝送路の障害によ
って長期間の断状態になりたことt検出するもの、5は
サーミスタ、6は伝送路上のれるもの、TRはトランジ
スタ、R1ないしR9は夫々抵抗、Cはコンデンサ、I
Cはアンプを表わしている。なお、:1ンデンtCと抵
抗R4とは本発明にいう容量性帰還回路に相当し、抵抗
R3は入力抵抗を構成し、抵抗R1とR2とは直流増幅
回路7に対する入力基準電圧を与える分圧器を構成し、
抵抗R6とR7とはトランジスjllTRに対するいわ
ば半固定バイアス回路を構成し、抵抗R9はサーミスタ
TRに流れる最大電流1i−制限する限流抵抗に相当し
てりる。
2 is an AC amplifier, 3 is a rectifier, 4 is a comparator that detects not just a momentary interruption of the pilot signal but a long-term disconnection due to a fault in the transmission path, 5 is a thermistor, and 6 is a component on the transmission path, TR is a transistor, R1 to R9 are each a resistor, C is a capacitor, and I
C represents an amplifier. Incidentally, the resistor tC and the resistor R4 correspond to a capacitive feedback circuit according to the present invention, the resistor R3 constitutes an input resistor, and the resistors R1 and R2 constitute a voltage divider that provides an input reference voltage to the DC amplifier circuit 7. constitutes,
The resistors R6 and R7 constitute a so-called semi-fixed bias circuit for the transistor jllTR, and the resistor R9 corresponds to a current limiting resistor that limits the maximum current 1i flowing through the thermistor TR.

上述のパイロット信号はパイーット・フィルタlによっ
て抽出され、交流増幅器2によって増幅され、1流11
3によって直流に髪換される。そし゛て該直流成分は、
直流増幅回路7の入力信号となり、アンプICにまっで
増幅されてトランジスタT′″Rfl制御する。これに
よって、サーミスタ5を流れる゛電流が上記パイロット
信号の信号レベルによって制御され、利得調整部6の利
得が制御される。即ちバイラット信号の信号レベルを所
定レベルに保持するよう制御が行なわれる。
The above-mentioned pilot signal is extracted by the pilot filter l, amplified by the AC amplifier 2, and the first stream 11
3, it is converted to direct current. Then, the DC component is
It becomes an input signal to the DC amplifier circuit 7, is directly amplified by the amplifier IC, and is controlled by the transistor T''Rfl.As a result, the current flowing through the thermistor 5 is controlled by the signal level of the pilot signal, and the gain adjustment section 6 The gain is controlled, that is, the signal level of the Virat signal is maintained at a predetermined level.

また上述の一部でなく、伝送路の障害によりて。Also, not some of the above, but due to a failure in the transmission line.

アンプICの出力が予め定めた閾値以下に低下すると、
比較lI4がこれを検出して警l11を発する。
When the output of the amplifier IC drops below a predetermined threshold,
Comparison lI4 detects this and issues an alarm l11.

上述の如く輯流増幅回路7はサー(スタ5に流れる。電
流を制御するが、フンデンすCを含む帰還回路がアンプ
ICに対して接続されているために。
As described above, the current amplifying circuit 7 controls the current flowing to the servo amplifier 5, but this is because the feedback circuit including the circuit is connected to the amplifier IC.

直流増幅回路7はアナーグ積分演算li]−を構成、p
でいる。そしてその゛時定数は主として、フ・ンデンサ
Cと抵抗R3とR4とによって決定さn、単にCRの時
定数回路をサー(スタ5.に並列に接続するものに(、
らべてフンデン″V″Cの容量が比較的小さく工も、抵
抗R3やR4の値を大きくとることができ0例えばす、
−ミスタ5自体の応答時定数にくらべて十分大きい時定
数をAGC回路にもたせることが可能となる。
The DC amplifier circuit 7 constitutes the Anag integral calculation li]-, p
I'm here. The time constant is mainly determined by the capacitor C and the resistors R3 and R4.
Even if the capacitance of Funden "V"C is relatively small, the values of resistors R3 and R4 can be set large.
- It becomes possible to provide the AGC circuit with a sufficiently larger time constant than the response time constant of the mister 5 itself.

また図示直流増幅回路7は、第2図図示の如き特性管も
ってサーミスタ5に流れる電流を制御することができる
。即ち、サーミスタ5を流れる電流ITHの最大値は抵
抗R9によりて決定され、また当該電流ITHの最小値
は抵抗R6によるトランジスタTRに対するベース電流
によって実質的に決定される。また9第2図図示の勾配
は抵抗R3とR4とによって決定され、か・つ図示矢印
方向で示す勾配め中心は°抵抗R1とR2とによる基準
電圧レベルによって決定されることとなる。このために
、、第1図図示の直流増幅回路7にお一°二では。
Further, the illustrated DC amplifying circuit 7 can control the current flowing through the thermistor 5 with the characteristics shown in FIG. That is, the maximum value of the current ITH flowing through the thermistor 5 is determined by the resistor R9, and the minimum value of the current ITH is substantially determined by the base current for the transistor TR caused by the resistor R6. Further, the slope shown in FIG. 2 is determined by resistors R3 and R4, and the center of the slope shown in the direction of the arrow shown in the figure is determined by the reference voltage level of resistors R1 and R2. For this purpose, the DC amplifier circuit 7 shown in FIG.

抵抗R1,R3!、R3,R−4,R6,R9を夫埼独
立に設定して、ik体と−してめ新線の特性を附与する
ことが可能となる。
Resistance R1, R3! , R3, R-4, R6, and R9 can be set independently and used as an ik body to impart the characteristics of the new line.

なお言うまでもなく、上−の如くアンプIC管含む回路
部分は積分演算回路を構成しているために、第3図図示
の如く、入力レベルAがいわゆる瞬断によって一時的に
低下した状態が生じても。
Needless to say, since the circuit section including the amplifier IC tube constitutes an integral calculation circuit as shown above, a state in which the input level A temporarily drops due to a so-called instantaneous interruption occurs as shown in Fig. 3. too.

比較194に入力されるレベルは図示レベルBの如く、
比較的大ぎい時定数管もって低下することとなる。この
ために、比較1B4における閾値レベルを図示Cの如く
与えておくことによって、瞬断時にいちいち警報を発す
ることがなくかつ障害発生時に限って警報を発するよう
にすることが可能となる。
The level input to the comparison 194 is as shown in level B,
This results in a relatively large time constant tube. For this reason, by providing the threshold level for comparison 1B4 as shown in C in the figure, it becomes possible to issue an alarm only when a failure occurs, without issuing an alarm every time a momentary power outage occurs.

以上説明した如く0本発明によれば、AGCのために必
要な定常状態特性を自由に設定でき、かつサーミスタ自
体の応答時定数によって基本的には影響を受けない形で
AGC全体の時定数を設定することが可能となる。
As explained above, according to the present invention, the steady state characteristics necessary for AGC can be freely set, and the time constant of the entire AGC can be set in a manner that is basically not affected by the response time constant of the thermistor itself. It becomes possible to set.

ttm面のmsな説明 、第1図は本発明の一実織例構成、第2図および第3図
は第1図図示構成の動作を説明する説明図を示す。
ms explanation of the ttm plane, FIG. 1 shows an example configuration of the present invention, and FIGS. 2 and 3 show explanatory diagrams explaining the operation of the configuration shown in FIG. 1.

図中、4は比較論、5はす−ミスタ、6は利1lllI
I1部、7は直流増幅回路、TRはトランジスタ。
In the diagram, 4 is comparative theory, 5 is Mr., and 6 is interest 1llllI
Part I1, 7 is a DC amplifier circuit, and TR is a transistor.

ICはアンプ、CおよびR4は容量性帰還回路を表わす
IC represents an amplifier, and C and R4 represent a capacitive feedback circuit.

特許出願人  富士通株式会社 代理人弁理士  森 1)   寛Patent applicant: Fujitsu Limited Representative Patent Attorney Mori 1) Hiroshi

Claims (1)

【特許請求の範囲】[Claims] 信号電流が流通する伝送路中にもうけられた利得調整部
に対して、上記信号電流の一部を抽出して当蒙信号電流
の一部の信号レベルに対応した帰還を行なう自動利得、
調整回路に詔いて、上記抽出さnた信号電流の一部に対
応した入力信号を増幅する直流増1Illl+と験直流
増幅器の出力によって駆動されて上記利得調整部を制御
する一v−1スタとをそなえると共に、上記直流増II
器は、合量性帰還回路をそなえ、上記サーミスタに流れ
る電流を制御すると共に上記入力信号を積分する積分回
路として動作することを特徴とする自動利得調整回路駆
動回路。
an automatic gain that extracts a part of the signal current and feeds it back in accordance with the signal level of the part of the signal current to a gain adjustment section provided in a transmission path through which the signal current flows;
A DC amplifier 1Ill+ for amplifying an input signal corresponding to a part of the extracted signal current by controlling the adjustment circuit, and a 1V-1 star driven by the output of the experimental DC amplifier to control the gain adjustment section. In addition to providing the above-mentioned DC increase II
1. An automatic gain adjustment circuit driving circuit, characterized in that the device is provided with a combinant feedback circuit, and operates as an integrating circuit that controls the current flowing through the thermistor and integrates the input signal.
JP9998781A 1981-06-27 1981-06-27 Driving circuit for automatic gain adjusting circuit Pending JPS581310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9998781A JPS581310A (en) 1981-06-27 1981-06-27 Driving circuit for automatic gain adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9998781A JPS581310A (en) 1981-06-27 1981-06-27 Driving circuit for automatic gain adjusting circuit

Publications (1)

Publication Number Publication Date
JPS581310A true JPS581310A (en) 1983-01-06

Family

ID=14261995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9998781A Pending JPS581310A (en) 1981-06-27 1981-06-27 Driving circuit for automatic gain adjusting circuit

Country Status (1)

Country Link
JP (1) JPS581310A (en)

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