JPS58130621A - Logical circuit - Google Patents

Abstract

PURPOSE:To enable an operation of a short delay time even in case the capacity which is connected to an output is large or a TTL, etc. is connected, by driving the gate of a field effect transistor for power supply current with an output of a front stage. CONSTITUTION:The basic constitution of this example is equal to a conventional one, and the 2nd stage enclosed by a dotted line, i.e., an output stage inverter differs. That is, the gate of a current source FET provided at an output terminal is not grounded but connected to an output terminal of a front stage via a diode D44 for level shift. An MESFETQ37 is used for current source of the diode D44. When the gate of an FET-Q32 is set at level ''1'', the gate of an FET-Q32 is set at level ''1'' via the diode D44. Therefore the FET-Q36 can extract quickly the electric charge of above-mentioned gates even in case the FET group is connected in parallel to an output terminal.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a normally-on field effect transistor (r
gT).

[Technical background of the invention]

Gaps integrated circuits have a mobility 5 to 6 times greater than silicon, making them suitable for high-speed signal processing. However, Ga-containing S cannot be used for MO8 type FICT because a high-quality insulating film cannot be formed on the surface. Instead, JFICT using PH junction (r-) or Mg2 using dart with Schottky barrier
F) CT is used. However, these dart structures operate as a diode in the forward direction between the gate and the source when the potential becomes high with respect to the source, and the gate-source voltage is approximately 1.2V at the PN junction.

, the voltage is about 0.8V in the case of a tokey fault, so the logic amplitude cannot be obtained sufficiently. So ζ f-)・FgT of the type where the drain current flows even when the source voltage is 0 (normally-on 111
Logic circuits using FETs were considered. An example of this is shown in FIG. 1(a), which is a logical diagram. This circuit is typically 11FL (qlf @dFET Logi
c), and by providing a joint stage with a source follower and a level shift circuit between each G1*Gn switching stage and the next stage, the logic amplitude can be kept sufficiently large (approximately 25V). Become. However, this circuit has the drawback of requiring two power supplies, a positive power supply and a negative power supply.

Therefore, the present inventor has previously proposed a logic circuit that can operate with a single power supply and consumes less power than BFLK. FIG. 2 shows an example of a logic circuit using three stages of inverters. Qll~Qss has pinch irami pressure of about -0.7
A normally-on type Mg2 PICT of V performs multiple switching operations. Q14~Qas is each step 4, ? /FICT-Ql, -QB, no load FE'l'. Dat~)3 is a diode constituting the level shift circuit tube, and Ckl-Qk is a current source FET for these. Further, Dsl is a diode serving as a level shift circuit for floating the common source potential of the switching FIT Qstbei from the tube ground potential. This circuit will be briefly explained. -4''': Let the current of im s be 11. The current of Q snow y and ms be Ij, respectively. Consider the case where the gate of ζ is at the "0" level. At this time, Qll is cut-off, so Ql4's I jFi flows through the t. When the 11" level enters the dirt, Qss operates as a forward diode, so the current minus Ij from 11 flows from the dirt of QB. At this time, Qss is on. The state and the current of the citrain are of bribery! 1 to false.

The current minus IJ flows. Looking at the whole circuit in this way, the diode DaxK#i switching "'T-
Ql s ΣI− which is always constant no matter what state Ql is in
When the current ΣI flows, the common source potential becomes a constant potential that is higher than the ground potential.

FIG. 3 is a diagram showing each current relationship using the static characteristics of the FET-Qsm shown in FIG. For the static characteristic curve 11A of Qlm in Figure 812, the current is false 1! 1 becomes *gland B, Qlg
The drain current of is calculated by subtracting the current Ij of Qss from B.
It will be represented by IC. At this time, the low level is V. =
Characteristics of O, SV - Voltage v at the point where IIA and curved edge C intersect
The four-way high level L is determined by 1.5V of the voltage vH which is the sum of the forward voltage of the diode and the common source voltage.

[Problems with background technology]

Although the circuit of FIG. 2 operates with a single power supply and provides a configuration with sufficient logic amplitude, it still has the following drawbacks.

When considering a logic circuit (, there are cases where many logic darts are connected to the output of one logic dart, so-called fan-out. In this case, a capacitance of an isometrically large value is connected, which is the same as 9. ].

Delay time increases. 1N, IC output circuits have parasitic capacitances such as gloss, couzo capacitance, and board capacitance, and other circuits to be driven must also have sufficient drive capability, such as TTL, which needs to sink current at low levels. Need a stone.

Taking the output stage inverter portion of FIG. 2 as an example, FIG. 4 shows the state when the capacitance ct moves. When injecting charge into capacitor C, what is the maximum current that can be injected? 1
It is. Also, what is the maximum current when extracting charge from capacitor C? , is. At this time, if the capacitance C is large, the change in the dirt potential Vl of (ha) (on the other hand, the change in the potential Vl of the capacitance C is
As shown in the figure, the delay times 'd1 and td2 become large.

[Purpose of the invention]

The present invention has a short delay time when the capacitance connected to the output is large due to a large number of fan-outs, or when a TTL etc. that needs to sink current at low level is connected to the output. The object of the present invention is to provide a logic circuit that can operate and has a large driving capacity.

[Summary of the invention]

The present invention improves the driving ability of at least the output stage inverter of a logic circuit as shown in FIG. That is, using a normally-on FI FET whose drain is connected to a first constant potential (for example, a positive power supply) via a load and whose source is connected to a second constant potential (for example, ground potential) via a level shift circuit, When the output stage inverter is configured by connecting the output terminal to the output terminal via a level shift circuit and providing a current source FIT t between the output terminal and the second constant potential, the current It is characterized in that the dirt of the source FIT is driven by the output of the previous stage.

〔Effect of the invention〕

According to the present invention, when the output terminal of the output stage inverter becomes a low rail, the current source PET provided at the output terminal
is driven by the output of the previous stage and is sufficiently turned on, so even if an equivalently large capacitor is connected to the output terminal, the charge stored in the capacitor can be quickly extracted. That is, it is possible to obtain a logic circuit with high driving ability that can operate with short delay time even when the number of fan-outs is large.

[Embodiments of the invention]

Fig. 6 2W1 of an embodiment of the present invention. This is a BFL consisting of an inverter. QsaeQss is a normally-on switching MES PET, and each drain is connected to the positive power supply (vDI) via the load ME8 FET Qss and Q34, and the source is commonly grounded via the level shift diode Dast. . D4
1#041 is a level shift diode for inter-stage coupling), QsssQa is a current source M]C8F'E
It is T. The above basic configuration is the same as in Figure 2.
The characteristic part of this embodiment is that the date of the current source FIT provided at the output terminal of the second stage surrounded by the broken line, that is, the output stage inverter, is not grounded, and is connected to the previous stage output terminal via the level shift diode D44. To! It is continuous.

Qsv is ME8 FIT -1' 6 for D44 current source
Le.

With such a configuration, FET-Qss (09'
) reaches the "1" level, t', FET -Qs@
C-to becomes @1'' level via diode D44.

Therefore, even when a group of FETs are connected in parallel to the output terminal as shown in the figure, the charges of these darts are transferred to the FET -Q
s@ can be extracted quickly, and the delay time can be significantly shortened. Input potential v1 of this output stage inverter
FIG. 2 shows how the output potential v1 changes. As is clear from the comparison with FIG. 5, 'dl is greatly shortened.

FIG. 8 shows another embodiment, in which a source follower FIT-Qs- is connected between the FIT-Qsa in FIG. 6 and the diode 04m.
According to this embodiment, when the output of the output stage inverter changes to the "1" level, the charge injection into the FET group connected in parallel to the output terminal is caused by FET-Qs.
Due to rounding performed quickly (by s), not only the delay time 'dl at the fall of the output terminal potential V, but also the delay time td2 at the time of the rise are greatly improved. This situation is shown in FIG. 9 in correspondence with FIG. 7.

FIG. 10 shows another embodiment of the present invention, and shows the factors shown in FIG.
The difference from the diagram is that the GooF potential of FET-QB- is determined through the diode D441s044m. The embodiment shown in FIG. 11 is an example in which a source follower F'ET-Qss is added to the embodiment shown in FIG. 910.

In these embodiments, the same effects as in FIGS. 6 and 8 can be obtained, respectively.

Further, FIG. 12 shows still another embodiment of the present invention. In the circuit shown in Fig. 6, a constant current always flows through the diode Q4s, so that WET-Qs>aQs
The common source potential of * will be kept constant, but F
When the dart of ET-Qlg reaches @1" level, a large amount of current flows through FIT-QB, and the FE
The current flowing to the common source differs depending on whether the dirt level of T-Qll is @1” or @0#.In the overall circuit, when there are few P and F circuits in Fig. 6, the current flows to the common source almost 1'! Although it does not have any effect, such as when there are many PA and 77 circuits, etc.
The impact will be greater. Therefore, in Figure 12, FICT-Qs
Depending on the state of the dart m, when it is at the ``1'' level, the FI
T-QCs 1Q4G is added. By doing so, the common source potential is kept constant. FIG. 13 shows the circuit of FIG. 12 with a source follower FET added.

By the way, in the example so far, the number of switching FETs in one pack stage is one, that is, in the case of a double-sided inverter. It is of course possible to apply the present invention to a buffered Noah gate. Furthermore, in the embodiments so far, only logic circuits that operate with a single power supply have been described, but the current source FgT-Qsis *
It goes without saying that the present invention is effective even in the case of a positive and negative two source where the source such as Qs 6 # Qs y is connected to a negative power supply. Furthermore, when a plurality of level shift diodes D41 are connected to raise the common source potential,
Further, variations not shown in the drawings may be considered, such as a case where a plurality of level shift diodes 041 for interstage coupling are connected.

Furthermore, FIG. 14 shows the previously proposed NOR gate using a diode that operates with a single power supply.

1) 111. I) s is the input diode sI) ms is the level shift diode, -1 is the current source FET + Q
s1 is a normally-on switching FET, Ql
l is a load)"i;'r, l)s 4 is a diode for raising the common source potential from the ground potential.

FIG. 15 shows an embodiment of the present invention in which the output stage inverter portion of this circuit is improved. Qss is a source follower FET, and D+i is a level shift diode.

Qsa is a current source FET, and the dart of Qit is connected to the dart of Q84 via a diode Dis. Q
sv is a current source FET to the diode.

In this circuit, as in FIG. 6, it is possible to drive a large number of dates connected to the next stage at high speed.

In the examples so far, a diode has been used as the level shift circuit, but it goes without saying that this can be replaced with a resistor.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a logic circuit using a conventional normally-on type FET, Figure 2 is a diagram showing an example of a logic circuit using the previously proposed normally-on type FET that operates with a single power supply, Figure 3 is a characteristic diagram to explain the operation of Figure 2, Figure 4 is a diagram showing the state in which the output stage of Figure 2 drives capacitor C, and Figure 5 is the input/output characteristic at that time. Waveform diagram shown, No. 6
The figure shows a logic circuit according to an embodiment of the present invention, and FIG. 7 is a waveform diagram showing the input/output characteristics of the output stage inverter of the circuit.
FIG. 8 is a diagram showing the logic circuit of another embodiment, FIG. 9 is a waveform diagram showing the input/output characteristics of the output stage inverter of the circuit, and FIGS. 10 to 13 are the logic circuits of other embodiments. FIG. 14 is a diagram showing another type of logic circuit proposed previously, and FIG. 15 is a diagram showing a logic circuit of an embodiment to which the present invention is applied. Qs 1, Q32 --- Switching FET %
Qss *Qla... IT for load, et al. 3. -6...
- Current source FET%D41. 82... Diode for interstage level shift, D43... Diode for common source level shift, D44... Diode for level shift, Qst... FgT for current source. LJ3g... pg'r for source follower 0 Applicant's representative Patent attorney Takehiko Suzue Figure 1 (a) V. - 1 [2 Figure Vφ Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 1 tdlllIl gio Figure 11 Figure II 12 Figure 13 Figure 14 Figure 15

Claims (2)

[Claims] (1) Using a normally-on switching field effect transistor in which the drain is connected to a first constant potential through a load and the source is connected to a second constant potential through a level shift circuit, the drain is connected to a level. In a logic circuit configured to connect to an output terminal via a shift circuit and provide a current source field effect transistor between the output terminal and the second constant potential to configure an output stage inverter, the current A logic circuit characterized in that a source field effect transistor is configured such that its dirt is driven by a previous stage output. (2) The logic circuit according to claim 1, wherein the output of the previous stage is inputted to the current source field effect (DART) of the current source through the level shift circuit.