JPS5813049A - Packet storage system - Google Patents

Abstract

PURPOSE:To prevent different packets from being coupled together, by collating pieces of key information of split and stored packets given at the time of reception when those packets are coupled together. CONSTITUTION:When transferring packets to a CCE (communication controller) by packet transmission, a CPU informs the CCE of key information reported during reception together with addresses of a PM (packet storage memory) wherein the packets to be coupled are stored. A BKC (buffer key control part) collates the key information added to the packet stored in the PM address reported from the CPU with the key information reported from the CPU. When the collation result shows coincidence, the CCE after removing the key information from the packets stored in the PM couples those packets and sends them to a circuit. When they are not coincident, the CPU is instructed to discard the packets.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides three methods for transmitting and receiving packets in packet switching.
40 regarding a packet storage method in a memory (PM) for storing O packets in a multiplexed overconfidence control device (CCIC) and a main memory (MM) of a central processing unit (CPU).

No. 1 is a block diagram showing the configuration of CCN and CPU. The CPU is composed of a central controller (CC) and 1a (K), and the CCN is a block transfer control @ (ITc),
P.M.

O to carry out line control @ (LCT) and main transmission
Pattu key control 1g (IKc Ritoyo) is configured.

In addition, 1. ! , 8.4 are MM-CC and CC, respectively.
This is a line that connects IITC-I and 07 to -lTc and l'rc-P and is connected to each other to transmit and receive O information between each component. Below is OI! Transmission/reception of information regarding each component is performed by the wings via the armpits.

When the CCI receives a packet from the line, it stores part of it in the PMK and transfers the other part to the CPU. The CPU stores the received packet in IQ[K, performs routing processing, etc., and then reversely transfers the packet to the ccm. When the CCE receives the packet transferred from the CPU, it stores it in PM P3, combines it with other parts of the packet, and sends the packet to the nine lines specified by the CPU.

The overvoltage CCK is duplicated), and when a failure occurs, the device performs an emergency check to prevent interruption of the 00M processing.

However, if there are no PMPiK packets within 9 ccm of the active system after device switching is performed, it becomes impossible to send packets to the line. When a packet is received at this 9th ccm and the FMK is stored, the CCEOPMK of another system (standby system) is also stored to prevent loss of packets in the case of switching. However, in the past, if the CCI died and the packet was transferred to the CPU, a failure occurred, and the CCIC was switched to 111 while the packet was stored in the backup CC1e OPi [ffi].
MMK packets in CPt1T exist (should be combined with O packets @ OPM in CCX is initialized or may already contain other packets), ccm 111 of them! , ', l□ or a different packet F11, will be clamped and sent to the line.

The purpose of this study is to learn about the above-mentioned shortcomings and to eliminate packet coupling errors within 00M.

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, when the ccm receives a packet from the line, it stores a part of it in the ccg o area.
Kc is the bucket to be stored) O destination 1 [1c Key information is added and stored. Furthermore, K CCl1 a) Transfers the other part of the packet to the CPU, and reports to the CPUK that the packet has been received, but at this time, along with the PM packet storage address, the circle mark - information 7 that is added when the PM is stored. Report the same key information to the CPU. When KaCPυ transfers a CCII K packet when transmitting a packet, it notifies the address where the combined packet is stored and the key information to the CCIC upon reception. lKc compares the key information added to the packet stored in the PM address notified by the CPU with the key information notified by the cpv. If some of the query results are partially CCE, they are stored in the file 9:,1. ... Keratomo deletes the key information, combines both packets at Maruue, and sends them out to the line. If the trench 9 does not match and 9 r'', it instructs the CPU to 0.

As stated above, in order to carry out the present invention, OIIKC must:
It generates key information, adds key information to the packet stored in the PM, and queries the O key information when sending the packet to the line.

11 illustrates each instruction resistance between KcPU and 001.

As explained above, according to the present invention 11, when combining packets that have been divided and accumulated, different packets F
41111 points can be prevented from being combined, and MMK, which is part of bucket F, is stored in the original W expansion CPU.
This method is particularly effective in all cases where packets are divided and stored in different devices, such as when packets are stored on a magnetic drum, magnetic disk drive, etc.

[Brief explanation of drawings]

All is the CPU and cczo boot configuration (example), and the irises is an example of the instruction V-cce between the original CPt) and ccg. CPU - central sensing layer device, CC - central control unit, field...
Main storage device, CCX-Communication control device, 1IC-Block transfer control unit, h...Packet storage memory, BKC-
-Buffer key control unit, I, C? ---Line control section, 1
- A line that connects MM and CC, a line that connects s - cc and m'rc, a line that connects $ - BTC and PM, 4
-Connection between ITc and LC'r -ょPatent applicant Nippon Telegraph and Telephone Company

Claims (1)

[Claims] After receiving the packet from the first line, the fully loaded 9-channel high-reliability control device stores a part of the packet (40 packets) in the mail WK for storing O packets for both the channels and the backup system, and sends the other part to the central device. However, when transmitting a packet, the two packets are combined in the communication control device and sent to the "r+a" line.
When the communication control device receives the packet, it adds the same key information to the special packet stored in the message storage memory and the message packet stored in the central processing device, A packet storage device comprising a means for preventing different packets from being combined (by inquiring key information of both packets when combining packets when sending packets to a line), and comprising nine configurations. method.