JPS5812799B2 - switch network - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a switch network used in a telephone exchange etc.
In particular, it relates to its driving method.

In order to connect a large number of telephones, a telephone exchange usually has a plurality of input terminals (this number is expressed as m) and a plurality of output terminals (this number is expressed as n). A switch network consisting of a lattice (hereinafter simply referred to as a communication path switch).

) is used.

Especially in recent electronic exchanges, there are many switches with an 8x8 grid, where m=n=8.

Conventionally, this communication path switch has consisted of an assembly of functional elements as shown in the model of FIG.

That is, the communication path switch shown in Fig. 1 has a plurality of input terminals X1, X2, ... and output terminals Y1, Y2, ... arranged in a grid pattern, and a communication path is closed between the input and output terminals.・
In order to open the control terminals Cx1, Cx2,...CY
1, CY2, . . . are provided correspondingly.

At each grid intersection, there is an intersection switch S connected in series between the input and output terminals, a driver D for opening and closing the intersection switch S, a memory M for keeping the driver D operating during the call time, and a control terminal. Each gate G was provided to identify the content of the pulse-like control signal applied to CxCY and rewrite the state of the memory M.

Generally, in this type of known example, two control terminals Cx, C
In order to control the setting and resetting of the memory M from Y, the configuration of the gate G is complicated and has the drawback that its logical operation is limited.

These components, intersection switch S, driver D, memory M, and gate G, may be somewhat complex in practice, but conventional communication path switches all have these functions, especially the memory function for each intersection. It possessed an element of .

For example, in a communication path switch called a ferried switch developed at Bell Laboratories in the United States, two sets of cleverly set coils correspond to the gate G, and a semi-hard magnetic piece controls the action of the magnetic memory M. It also serves as a driver D for an intersection switch S consisting of a reed switch.

In order to further clarify the explanation of the circuit shown in FIG. 1, FIGS. 2 and 3 are block diagrams showing one intersection of the communication path switch.

FIG. 2 shows a known communication path switch constructed using MOS integrated circuit technology, and is provided with a flip-flop F/F engaged with control terminals Cx and CY, whose output corresponds to the intersection switch S in FIG. The configuration is such that the MOS transistor T is statically driven.

In FIG. 2, the gate G, memory M, and driver D shown in FIG. 1 are represented as a flip-flop F/F.

On the other hand, FIG. 3 is a block diagram of one intersection of a communication path switch according to the prior art of the present invention, which uses a semiconductor switch to open and close alternating current signals such as bell signals in the same way as mechanical communication path switches. It is.

In the circuit shown in FIG. 3, a gate G is connected between the control terminals Cx and CY, the control signal is identified by the gate G, and the memory M is rewritten, and the output of the memory M is used to write the constant current circuit C.
PNPN switch SCR connected in antiparallel by commanding C
It is what drives the.

Gate G and memory M can be made together as a set priority flip-flop.

In the configuration shown in Fig. 3, it is possible to pass alternating current such as a bell signal, intermittent current due to hooking dialing, etc. between the input and output terminals simply by applying pulse-like control signals to the control terminals Cx and CY. It will be understood that the constant current circuit CC corresponds to the driver D in FIG. 1, and the anti-parallel PNPN switch SCR corresponds to the intersection switch S in FIG.

As explained above, in the conventional communication route switch, the intersection switch is constantly driven via a memory provided for each intersection.

However, in practice, for example, in a communication path switch with 8x8 grid = 64 intersections, the number of intersections that are allowed to be closed is a maximum of 8 in order to avoid double connections.
At least 56 remaining intersections, Memory M, Driver D, etc. are idle and are not useful.

In addition, in the prior art shown in FIG. 3, connection points are used to connect both the PNPN switch SCR and constant current circuit CC, which are high voltage circuits, and the memory M and gate G, which are low voltage circuits, at each intersection. The large number of circuits makes it difficult to achieve high integration, and there are drawbacks to lower reliability.

In this way, conventional technology requires memory, which is a complicated circuit, for each intersection, and as a result, the functionality is not fully utilized, and the circuit becomes complicated, making it difficult to improve economic efficiency, reliability, etc. There was a point.

An object of the present invention is to simplify the circuit at each intersection by removing the memory circuit from the intersection, integrating the high voltage circuit section and the low voltage circuit section separately, and combining the two.
This aims to provide an economical and highly reliable communication path switch.

In the present invention, the intersection switch itself has a temporary memory function, the coordinates of the intersection to be closed are stored in a memory provided outside the grid, and the information in the memory is periodically read out to repeatedly drive the intersection switch. The dynamic drive method eliminates the need for memory at each intersection, which makes effective use of circuit functions, simplifies the circuit, facilitates division and connection of high-voltage and low-voltage sections, and improves control power. This is a technique that is particularly useful when attempting to integrate semiconductor circuits.

Hereinafter, the communication path switch according to the present invention will be explained in detail using the drawings.

FIG. 4 is a block diagram showing the basic components of a communication path switch according to the present invention.

In Fig. 4, X1, X2 are input terminals, Y1, Y2 are output terminals, Cx1, CX2, CY1, CY2 are control lines,
Mo is memory, S is intersection switch, G is gate, C is clock, DECx, DECy are decoders, D1, D2
indicates a driver, and R1 and R2 indicate a receiver.

Input terminals X1, X2, ... and output terminals Y1, Y2, ...
... are arranged in a grid, and each intersection has an intersection switch S and control lines Cx1, Cx2, CY1, CY2.
,... are provided, and each intersection switch S and gate G are connected.

Since the intersection does not have a memory, operations such as resetting the memory are not necessary, and the configuration of the gate G can be extremely simplified.

On the other hand, a control signal for closing the intersection switch S is applied to the terminal A, and the coordinate information of the designated intersection is stored in the memory Mo.

Then, in response to the signal from the clock C, the memory Mo transfers the coordinate information of the intersection to be opened to the decoder D, one piece of information at a time.
Send to ECx, DECY.

The decoders DECx and DECy translate the information in the memory Mo into X coordinates and Y coordinates,
, . . . issues an operation command to one set of receivers R1, R2 .

This activates the gate G at the selected intersection,
The intersection switch S is configured to close.

The clock C sends a continuous signal, and in response to this clock signal, the memory MO continues to sequentially read the coordinate information of another intersection to be closed, and once the reading has finished, it returns to the original state and continues reading the same content repeatedly.

As the intersection switch S, PNPN switch or MO
A switch, such as an S transistor or a slow-slow recovery relay, which temporarily stores the state when pulse-like short-time driving is obtained, is used.

If a PNPN switch is turned on by a pulsed gate signal, it will remain turned on by itself unless the current flowing through the switch is made zero externally. When a current flows or an intermittent current flows, the memory function is lost the moment the current becomes zero and it must be re-ignited, so a switch like this PNPN switch is also a switch that only has a temporary memory function. treated as such.

When the number of input terminals is m and the number of output terminals is n, the memory Mo has a storage capacity of m×n bits and stores the closed/open states of all intersections and reads them out bit by bit. There is a method of storing only the coordinate numbers of the intersections to be used.

For example, when m=n=8, the former uses a 64-bit memory and the clock signal completes one cycle of reading with 64 pulses, while the latter uses 3 bits of input coordinates and 3 bits of output coordinates.
A total of 6 bits is considered as 1 unit, and 8 units (in an 8×8 grid, only 8 intersection points are closed at most).

), it has a storage capacity of 48 bits, reads out one unit at a time, and completes one cycle with eight clock pulses.

The latter is desirable in order to shorten the memory read repetition cycle.

These are just examples, and any configuration may be used in practice.

Clock C may be built into the communication path switch, or may simply accept a continuous periodic signal commonly used within the exchange.

That is, the communication path switch of the present invention has this configuration as shown in FIG. 4, and with the aid of the temporary memory function and repetitive driving of the intersection switch S, the intersection switch S can be continuously operated as if it were driven statically in the past. You can continue to close it by doing so.

As a result, the memory that was conventionally required for each intersection can now be provided outside the grid, making the circuit around the intersection switch extremely simple and making it easy to separate high-voltage and low-voltage sections. Become.

In other words, when attempting to integrate a communication path switch into a semiconductor integrated circuit, since memory is a low-voltage circuit and the circuit is complex, it is technically difficult to integrate it on the same chip as a high-voltage circuit such as an intersection switch. It is not economically advisable to create the low-voltage section and high-voltage section separately and connect them with wiring, but the conventional method of providing memory at each intersection requires a large number of connection points. High integration was practically difficult due to the limit on the number of terminals.

However, in the present invention, since the memory is moved out of the grid together with the decoder etc., the number of connection points is greatly reduced.

For example, the conventional 64 connection points in an 8×8 grid can be reduced to 16 connection points, which is one-fourth.

As a result, the low voltage part can now be integrated into one chip.

Furthermore, depending on the method of configuring the memory, it is possible to reduce the actual storage capacity as described above.

FIG. 5 is a block diagram showing another embodiment of the communication path switch according to the present invention. In order to avoid complicating the diagram, only one intersection and its related circuits are shown and the others are omitted. be.

In FIG. 5, at the intersection of input terminal X1 and output terminal Y1, there is provided an intersection switch 1 in which PNPN switches that can be activated by light are connected in antiparallel.

On the other hand, a memory MxMy is provided to store a combination of input and output coordinates of an intersection to be closed.

When the grid size of the channel switch is 8×8, the memories Mx and My each have 3 bits as a unit and 8 units 2
It has a storage capacity of 4 bits each, and control signals are applied to terminals 2 and 3 at the same time.

Each time the memories Mx and My receive a clock signal from the clock C, the memories Mx and My synchronously repeatedly read out the stored information one unit at a time and send it to the decoders DECx and DECY, and the output is sent to the terminals translated by the decoders DECx and DECY. It is configured to come out.

A transistor 4 is connected to the decoder DECx, and the transistor 4 is normally conductive, and the logical signal of the decoder DECx is set so that the transistor 4 is turned off at the timing when the intersection should be closed by translation.

On the other hand, the transistor 5 is also connected to the decoder DECY, and is configured so that the transistor 5 is conductive at the timing when the intersection should be closed.

The collectors of the two transistors 4 and 55 are connected to the control terminal C.
x1 and CY1, and another transistor 6 and light emitting diode 7 are provided at each intersection.

For example, if the decoders DECx and DECy operate to simultaneously output signals to the control terminals CX1 and Cy1, the transistor 6 operates, the light emitting diode 7 emits light, and the intersection switch 1 is turned on.

If one intersection is driven for about 1 μs, for example, the original intersection is driven again after about 7 μs, and other intersections to be closed are driven for the rest of the time.

This operation continues to be repeated inside the channel switch.

During the approximately 7 μs period during which the drive is stopped, the intersection switch 1 continues to be closed due to its temporary memory function.

The light emitting diode 7 only occasionally passes current, which has the effect of reducing power consumption and extending its life.

FIG. 6 is a block diagram showing still another embodiment of the communication path switch according to the present invention, and like FIG. 5, one intersection and its related circuits are shown, and the others are omitted. .

In FIG. 6, memory Mo has a capacity to store the contents of all intersections, and the stored contents are read out for each intersection and sent to decoders DECx and DECY.

On the other hand, an oscillator OSO is provided that generates continuous pulses at a frequency faster than clock C, and its output signal is output from NAND gate 1.
It is always applied to one input terminal of 08.

Then, the transistor 104 is driven by the AND of the translation signal of the decoder DECx and the output signal of the oscillator OSC.

On the other hand, the transistor 105 is connected to the decoder DECy side as in FIG. 5, but contrary to the explanation in FIG. 5, this transistor 105 is normally conductive, and at the timing when the intersection should be closed, the transistor 105 is Set the logic signal of the decoder DECY to cut it off.

The collectors of the transistors 104 and 105 are connected to the control terminal C.
x1, CY1, to form a lattice, a simple gate consisting of a resistor 109 and diodes 110, 111 is provided at each intersection, and a capacitor 112 is provided at the midpoint.
According to the configuration of the circuit shown in FIG. 6, which is connected via a diode to each gate of the intersection switch 101, which is a PNPN switch connected in antiparallel, both transistors 104 and 105 are normally in a conductive state. Therefore, the potential at the midpoint of the diodes 110 and 111 is fixed to approximately the ground potential, but the
For example, at the timing when both Y and select terminal 1,
Transistor 104 is turned on and off by the signal from oscillator OSC, while transistor 105 is turned off, so the potential at the midpoint between diodes 110 and 111 increases and decreases, and capacitor 112 charges and discharges due to this potential change.

The charging current at this time becomes a drive signal for the intersection switch 101, and the intersection switch 101 is turned on.

Other functions are the same as those in the embodiment shown in FIG. 5, and their explanation will be omitted.

FIG. 7 shows still another embodiment of the communication path switch according to the present invention, and the structure is shown in a simplified manner similar to the above-mentioned example.

An example is shown in which a slow recovery type relay is used as an intersection switch.

That is, the contact 201 of the fast action slow recovery relay is connected between the input terminal X1 and the output terminal Y1, and the coil 213 is connected between the input terminal X1 and the output terminal Y1.
are connected to control terminals Cx1 and CY1.

A transistor 204 is connected to the control terminal CX1, and a transistor 205 is connected to the control terminal Cy1.
The decoder DECx is activated by the read signals of the memories Mx and My.
, DECy operate the transistors 204 and 205, current flows through the coil 213 and the contact 201 closes, and thereafter, the transistor 204 or 205 stops operating by periodically exciting the coil 213. Due to the slow and slow recovery characteristics of the relay, contact 201
It is an attempt to keep it closed.

Note that the Zener diode 214 is an example provided for level shifting between the potential of the decoder DECx and the transistor 204.

As explained above, the present invention simplifies the circuit configuration of the intersection by eliminating the need for a memory for each intersection.
By functionalizing the entire configuration, it is possible to reduce the number of connection points, make it more economical, and obtain a highly reliable communication path switch, especially when implementing semiconductor integrated circuits.

In the above embodiment, one intersection switch is provided at one intersection, but in practice, one communication path often consists of two balanced lines, and accordingly, one intersection switch is provided at one intersection. It is also possible to configure a balanced intersection switch with two switches as one set.

In addition, for example, in the case of an 8x8 grid communication path switch, the number of intersections that can be closed at the same time is at most 8 points. - It can be implemented as desired by simply changing the read cycle etc. slightly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the functional configuration of a conventionally known switch network, and FIGS. 2 and 3 are specific examples of switch networks according to the prior art of the present invention. FIG. 4 is a block diagram showing the main circuit configuration of the switch network according to the present invention, and FIGS. 5 to 7 are block diagrams of other embodiments of the switch network according to the present invention. S...Intersection switch, G...Gate, D1, D2...Driver, R1, R2...
...Receiver, DECx, DECy...Decoder, Mo, Mx, My...Memory, OSC
...Oscillator, C...Clock, 108.
...Nand Gate, 1,101,201...
・Intersection switch, 4, 5, 6, 104, 105, 2
04,205...Transistor, 7...
・Light emitting diode, 110, 111, 113, 114・
... Diode, 214 ... Zener diode.

Claims (1)

[Claims] 1 Multiple intersections with a temporary memory function that can temporarily maintain the state by short-term drive inserted between two intersections where multiple incoming lines and outgoing lines are arranged in a grid and communication paths are to be formed between them. A switch, a storage means for storing coordinate information of at least an intersection to be closed among the plurality of intersection switches, and a drive means for selectively driving the intersection switch based on a readout signal from the storage means; A switch network characterized in that information is periodically read out and intersection switches to be closed are repeatedly driven for a predetermined period of time.