JPS5812647A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic diagnostic apparatus, and more particularly to an ultrasonic diagnostic apparatus capable of displaying the state of organs such as the heart in M mode.

For ultrasound diagnosis of the heart, the mitral valve, tricuspid valve, atrium,
When displaying the operating status of each part such as the ventricle as CR'I',
The M mode display, which takes time on the horizontal axis and depth from the body surface on the vertical axis, and displays the desired cross section C = corresponding ultrasound reflection intensity of the relevant part as a change in brightness, has been This is where it is being done. In this type of diagnosis, it is often necessary to display one screen for more than 10 seconds, but conventionally only CRTs with long afterglow properties are used, making it difficult to maintain sufficient brightness. . In addition, when recording an image, there is a means for recording on photosensitive recording paper through a plurality of glass fibers, each end of which is arranged in the vertical axis direction of the CRT, a means for photographing a CRT image screen by screen, a means for recording on a CRT In the past, a method was used in which the time axis was displayed as one point and the image was photographed using a long film driven at a constant speed. It is extremely inconvenient or difficult to carry out the process, and there are also disadvantages such as the recording medium is expensive and the development process takes time.

The present invention has been made under the above circumstances (2), and its objectives are to enable stable high-brightness variable display even in bright places, to enable viewing of the display, and to use an inexpensive recording medium. It is an object of the present invention to provide an ultrasonic diagnostic apparatus that can display images again at any time.

Hereinafter, the present invention will be described with reference to an illustrated embodiment. 1st
In the figure, a first trigger signal Tr is sent out from a first timing signal generator 1 at every predetermined repetition period T.
I causes the oscillator 2 to generate a pulse signal of a predetermined width. Ultrasonic pulses sent out from an ultrasound probe (not shown) in response to this pulse signal are reflected from, for example, the mitral valve of the heart, enter the ultrasound probe, and are converted into electrical signals (converted into two and received). The receiving section 3 amplifies and detects the first electric black signal to make it a video signal, and converts it into a video signal via a low frequency f wave generator 4, a mixer 5, and an element 6 of the third switch 8N. In the following, for ease of understanding, a case will be explained assuming that the repetition period T is 40%8, the carrier frequency of the ultrasonic pulse is 2 MHz, and the pulse width τ is 6 μS. The mixer 4 has a line break frequency fc set to fc = 1/f''F 167 KHz so as to extract only the main lobe from the spectrum of the video signal. The third switch S1 is configured to be able to mix desired signals, such as an output signal such as an output signal and a marker signal.
The element 6 is used for mode switching in conjunction with other third switch elements to be described later, and is shown set to display mode and recording mode in FIG.

The A/D converter 7 converts the video signal to a conversion speed using a synchronization signal WPI (see FIG. 2) sent from the first timing signal generator 1 through the element 8 of the third switch 81. It is configured to quantize at 2fc. In the following, a case where the quantization unit is 2 (4 gradations) will be explained.

The output signal of the A/D converter 2 is sent to the first switch 8.
A pair of first buffer memory sections 10 .
I am guided by 11. These memory units 10 and 11 may be shift registers or the like, and are divided into two sets (hereinafter, they are classified by adding suffixes a and b, and only the wiring related to each one is shown) corresponding to the quantization unit. It has become. Each output terminal of the first buffer memory sections 10 and 11 is led to the main memory section 13 via an element 12 of a first switch 8.

The switching of elements 9 and 12 of the first switch S2 is controlled by the output signal of the flip-flop circuit 14. This flip-flop circuit 14 is driven by a first signal Trl applied from the first timing signal generating section 1 via an element 15 of the third switch SN, and an element 9 of the first switch S■. and 12 are alternately switched and connected to the first buffer memory sections 10 and 11 at each repetition period T. Further, the first buffer memory sections 10 and 12 are driven by first and second clock pulses Cl and cl. That is, the first write pulse WPI and the first read pulse RPI sent from the first timing signal generator 1 are applied to the element 1 of the third switch 8.
d and 17 and through elements 18 and 19 of the first switch 87, the first buffer memory sections 1o and 11
are guided by each. Therefore, the first buffer memories 10 and 11 are connected to the elements 18. of the first switch '81.
19, the first write pulse wPI, the first M, and the output pulse RP are alternately input.

Now, the propagation distance of ultrasonic waves in the human body is approximately 1540.
trc/s, the time required for round-trip propagation from the body surface to 20 (II-) is approximately 260 μs. Therefore, the video signal to be processed is (See Figure 2).The above first buffer memory section JO,1
The storage speed of 1 is A/l) 2f, which is the same as the conversion speed of converter 7.
c, in the case of the left register, the number of stages may be 260/(1/2 fc ) = 86.7.

Therefore, considering the margin, the number of stages is set to 128. In this case, the first clock pulse cH is equal to the first write pulse WP[, and the first trigger signal Tr l
There are 128 pulses after 260 μm, and the pulse interval is about 2.
It is 03μ wealth.

Then, writing is performed in one side 1o of the first buffer memory section by this write pulse WP■. Also,
On the other hand, in the main memory section 11, the memory contents written in the previous cycle T are read out, and the main memory section 1
The input to 3 is carried out. In this case, the clock pulse Cl is equal to the first read pulse RPJ, which corresponds to the minimum cycle dim of the main memory section 13 (assumed to be 0.25 μl).

The main memory section 13 inputs a first counter 21 and a second counter 2 via an address change section 2o such as a multiplexer.
2 and the synchronizing signal generating section 23. The first counter 2z' receives signals from the eleven timing signal generators 1 to 3.
The first write pulse R is applied via element 24 of switch 8N.
P2 is applied, and a vertical write address signal VWA is generated by counting this RPI with a 7-bit counter. The second counter 22 is supplied with the signal Trl via the element 25 of the third switch 81, and this Trl is
Horizontal write address signal HW counted by bit counter
Generate people. These first. The reset signal is inputted to the second kakunta 21 and 22 (d).
A first write gate signal W'oI (see FIG. 1) is led from the timing signal generating section 1 of , via the element 26 of the third switch f8M. The synchronizing signal generating section 23 may be similar to that for a television receiver, for example, and converts the vertical and horizontal signals from the sweep circuit into 7-bit and 8-bit signals, respectively (vertical readout address similar to 2/D conversion). The signal VR is configured to send out the signal VR and the horizontal read address signal HRA.

That is, in the main memory section J3C, the vertical write address signal vW and the horizontal write address signal HWA are
A write address is specified by , and writing and reading are performed using a first write gate signal WGI that covers the generation of the first read pulse RPI. Therefore, the main memory section 13 stores the first trigger signal Tr (@
128 video signals of 260 pm each, 2 Trl
56 data are stored, and when the storage of 256 data is completed, all stored contents are reset by the carry output signal from the second counter 22, and such a write operation is repeated.

By the way, the main memory section 1s is in the write state during the period in which the first write pulse RPI is generated, so the first write pulse RPI is in the write state.
Since it is only for 32μs during the generation period of the write gate signal WG■, the above repetition period T (400ooμ$)
The remaining 39968 μm is in the read state (5th
See figure R).

In this read state, the address changing section pg switches to the vertical successive address VRA and horizontal read address (IR) from the synchronizing signal generating section 2J.

The stored contents of the main memory section 13 read out in this manner are converted into an analog signal by the D/person converter 26 and then taken out to the output terminal 28 via the first modulation circuit 27. This first modulation circuit 27 includes the synchronization signal generation section 23.
A first monitor signal MI (see FIG. 5) is given from
Horizontal and vertical synchronization signals are added to the analog video signal. Therefore, if a normal monitor television is connected to the output terminal, images such as the heart can be displayed in M mode. In this case (see Figure 4), the CRT's afterglow can be displayed repeatedly at high speed for 256 sweeps of one repetition synchronization (40-s), that is, about 10 seconds. It can be easily observed in a bright place without relying on gender.

On the other hand, the output signal of the human/D converter 1 is transmitted to the third switch 8.
It is led to a pair of second buffer memory sections 31.31 via element 2# of (2) and element 30 of @2 switch 8H, and each output terminal of these memory sections 31.32 is connected to an element of second switch sn. 3
3, is led to the output end 31 via the D/A converter 34, the second modulation circuit 35, and the element S6 of the third switch 8N. Elements 30 and 33 of the second switch 81
is synchronized with elements 9 and 12 of the first switch 8I in the first buffer memory section 10.11, and is switched and controlled by the output of the flip-flop circuit 14. The second buffer memories 31 and 32 are driven by third and fourth clock pulses C1 and C2. That is, the first write pulse WP■ and the second read pulse RPI from the first timing signal generator 1 are transmitted to the elements 18 and 39 of the second switch sh.
The signal is led to the second buffer memories 3 and S2 through the buffer memories S1 and S2, and WPI is alternately applied to these buffer memories S1 and 32, respectively. In this case, the second read pulse RPI has a pulse interval of approximately 312μ.
It is configured to eject 128 pulses in about 402 mm. That is, 260
Since the video signal equivalent to μ$ is expanded to 40,000 μs, the signal band is reduced from 157 KHz to approximately 1.1K.
This results in HgJ two-band compression. The digital video signal band-compressed in this manner is converted into an analog signal by the D/person converter 34 and guided to the second modulation circuit Jul2. This second modulation circuit 35 is given a second monitor signal MI (see FIG. 4) sent from the first timing signal generator 1, and the first signal is a vertical synchronization signal synchronized with the signal Tri. , a frame synchronization signal is added for each screen (every 128 vertical synchronization signals), and subcarrier frequency modulation is applied. The second read pulse R
Since the PI pulse width of 312μ corresponds to approximately 8.2 KHz, the frequency of the subcarrier may be set to about 3 KHI if (
: If set, the bandwidth of the video signal taken out to the output terminal 31 will be approximately IKHI centered around 3 KHz, and it can be easily recorded on a general-purpose audio cassette tape or the like.

/) Now, the case of reproducing a signal recorded as described above will be explained. In this case, the third sweet above?
It is assumed that all the elements 81 are switched to the opposite side 62 from that in FIG. Therefore, the recorded contents of the tape are transmitted to the demodulation circuit 3 via the element 36 of the third switch 8N.
8, the video signal, frame synchronization signal and vertical synchronization signal C are divided into two, and the video signal is sent to the iJ3 switch 8.
The frame synchronization signal and the vertical synchronization signal are guided to the A/D converter 1 via the N elements e, and the frame synchronization signal and the vertical synchronization signal are also guided to the second timing signal generation section 39. In this second timing signal generating section S9, a second trigger signal 'I'rI
(See Figure 3), and 82 write pulses wpi that output 128 pulses during an interval of about 40 minutes from this Tri.
, a third read pulse RPI that outputs 128 pulses during an interval of 32 pm from Tri, and a second write gate signal WGI that covers the RPI of . And the second trigger signal Tri is the third switch? The signal is led to the flip-flop circuit 14 through the element 11 of 81.

Second glance pulse WPi and third read pulse R
The P mark is connected to elements 16 and 11 of the third switch 8 and the first switch ? The first clock pulse CI and the second clock pulse C alternately through elements 18 and 19 of 8I.
1 to the first buffer memories 10 and 11. Further, the second write gate signal WGl[ is the third
It is led to the main memory section 13 and the address change section 20 via the element 26 of the switch 8I.

Therefore, in this reproduction mode, the low-speed signal from the tape is band-expanded via the main memory section 13, and a high-brightness display similar to that in the display mode is performed on the monitor television connected to output #a28.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, instead of performing 2-bit quantization as described above, 1-bit or 3-bit or more quantization may be performed. Further, each of the other numerical values is assumed for convenience of explanation, and can be changed as appropriate. In addition, various modifications and applications are possible within the scope of the gist of the present invention.

The present invention includes an A/D converter that quantizes a video signal, a pair of first and second buffer memories that alternately store output signals of the A/D converter at predetermined repetition periods, and a display unit. It has a storage capacity equivalent to one screen of
A main memory section that reads and sequentially stores the contents of the buffer memory alternately every repetition period and within a predetermined reading time shorter than the repetition period, and this main memo 9.
part (: means for reading out the stored content of one screen at each repetition period and displaying it on the display part; and means for reading out the stored content of one screen at each repetition period and displaying it on the display part; and means for reading and recording within a predetermined time approximately equal to.
A video signal can be band-expanded and displayed repeatedly at a predetermined repetition period, and a high-brightness display that can be easily observed even in a bright place can be performed. Furthermore, since the bandwidth of the video signal can be compressed using the idle time of ultrasonic transmission and reception, it is possible to easily record on inexpensive recording media such as general-purpose audio tapes, and this recording and the above Display can be performed freely without causing any interference with each other.

Also, a display mode in which the contents stored in the soil memory section are displayed on the display section, a recording mode in which the contents stored in the second buffer memory are recorded, and a playback mode in which the recorded contents of the audio tape are displayed on the display section. Since a means for selectively setting the above modes is provided, each of the above modes can be selected at any time as required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 to 5 are timing charts for explaining the operation. 1.39... Timing signal generation section, 2... Transmission 6 section, 3...9 Receiving section, 7... A/D converter, 10゜1
1... First buffer memory, 13... Main memory section,
14...Flip-flop circuit, 20...Address change section, 21.22...Counter, 23...Synchronization signal generation section, 1#, 37...Output end, 31.32.
...Second buffer memory, 8I...First switch, 8
1...Second switch, 81...Third switch.

Claims (2)

[Claims] (1) A receiving unit capable of transmitting a video signal corresponding to a reflected wave of an ultrasonic pulse transmitted at a predetermined repetition period, and a display unit capable of displaying the video signal in M mode; A/D that quantizes the signal
A converter, a pair of W41 and a second buffer memory for alternately storing output signals of the A/D converter at each repetition period, and a storage capacity having a storage capacity equivalent to one screen of the display section. A main memory section that reads and sequentially stores the stored contents of the first buffer memory alternately at each repetition period and within a predetermined reading time shorter than this repetition period; and one screen stored in this main memory section. means for reading out the contents of the second buffer memory at each repetition period and displaying the same on the display section; An ultrasonic diagnostic apparatus comprising: means for reading and recording information. , (2) A display mode in which the contents stored in the main memory section are displayed on the display section, a recording mode in which the contents stored in the second buffer memory are recorded, and a playback mode in which the recorded contents in the audio tape are displayed on the display section. The ultrasonic diagnostic apparatus according to claim 1, further comprising means for selectively setting.