JPS5812422A - Delay circuit - Google Patents

Abstract

PURPOSE:To easily delay a signal only when it rises and falls, by terminating a depletion type MOSFET, which outputs a signal through the source and drain, through a capacitor. CONSTITUTION:A capacitor 5 is charged when the level of an input from an input terminal 1 is 0, or discharged when 1. The rise of the output is delayed from the application of 0-level input to 1-level output to an output terminal 2, and the fall of the output is delayed from 1-level input to 0-level output. For this purpose, the input terminal 1 is connected to the gate of a depletion type MOSFET6, so conduction resistance is greater when the level 0 is applied than when the level 1 is inputted. Therefore, the 0-to-1 delay of the output level is set greater than the 1-to-0 delay. Thus, the delay limited to the rise and fall of the signal is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay circuit, and more particularly to a delay circuit applied to a %KMO8 integrated circuit.

For signal delay of a minute amount of time (a time that does not correspond to the basic clock period in a synchronous logic circuit) in a cocoon layer circuit, etc., a method is generally adopted that utilizes the charging and discharging time of the capacitor. M
In 08 integrated circuits, the structure of charging or discharging a capacitor through a transistor depends on the structure of the element.
This is due to the fact that it is relatively easy to implement, and the conduction resistance and capacitance of the transistor can be precisely controlled. However, in the above configuration, the charging time and the discharging time are not necessarily uniform, resulting in a difference in the delay time between the rise and fall of the output. On the other hand, control is difficult for the purpose of limiting the delay to only the start-up and fall-off outputs. However, in order to increase the delay time, a transistor with a large capacitance or a large conduction resistance is required, and when the delay circuit is constructed in an integrated circuit, the area occupied becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and to provide a delay circuit that can easily configure a delay limited to the rising and falling edges of a signal and is suitable for obtaining a large delay time with a relatively small capacitance. There is a thing called K.

The delay circuit according to the present invention has no depression in the signal line of the delay circuit! ! ! MO8)? The source and drain of the transistor are connected in series, and the capacitor terminated on the drain side is charged through the channel of the transistor.

The present invention is characterized in that it is configured to perform discharge, and further has a configuration in which the gates of the depressing transistors described above are controlled by signals that are in phase or in phase with the input signals.

That is, the basic configuration of the present invention is a capacitor, a transistor for controlling charging or discharging of the capacitor, and a depletion circuit connected in series with the transistor and the capacitor.

It is composed of a signal that controls the gates of a V W n11) transistor and a depletion, diagonal, and diagonal transistor, and is characterized by the ability to arbitrarily control the conditions for charging and discharging the capacitor by selecting the gate control signal. It is said that

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows that the present invention is formed on a P-type silicon substrate.
This is an example of a delay inverter applied to a channel MO8 integrated circuit. Output terminal 2, depletion transistor 3 as a load transistor of the inverter. Enhancement transistor as driver4. Capacity5. Depres with a capacitor 5 connected to the terminal in series with the signal,
It includes a single transistor 6. In the configuration shown in FIG. 1, when positive logic aha is input, the enhancement point 57
)Meta 4tiL is interrupted and the capacitor 5 is charged by the power supply VDD through the load transistor 3゜transistor 6. On the other hand, when the logic value 11" is input, the transistor 4
becomes conductive, and the charge accumulated in the capacitor 5 passes through the transistor 6 and is discharged from the transistor 4 to the ground. With this configuration, the delay time of the inverter is such that when the output rises, the logic level @01 is applied to the input, and the output terminal 20 level changes to the logic level Jl? When the output falls, it is the time from input 111 until the output reaches ``O@''.In the figure, the gate of deblessing transistor 6 is connected to input terminal IK, so it is shorter than input Jl. The conduction resistance is larger when 101 is applied.Therefore, the delay from 101 to 811 at the output level is higher than from 118 to 10.
It can be set larger than the @ delay.

Further, in these configurations, the delay characteristics can be arbitrarily designed by appropriately setting the characteristics of each transistor.

Another embodiment of the present invention will be explained with reference to FIGS. 2 to 5.

In the circuit shown in FIG. 2, the transistor 60 has a configuration similar to that shown in FIG.
The gate is connected to the output terminal 2 of the delay circuit. Even in this configuration, when charging the capacitor 5, the gate of the transistor 6 is connected to a low potential Km), and there is a high conduction resistance.

Further, during discharge, since the potential is high, the conduction resistance is low and the same effect as the configuration shown in FIG. 1 is expected.

The configuration in Figure 3 is the same as in Figures 1 and 2, with transistor 6
In this example, the gate of transistor 6 is connected to the source of load transistor 3, the gate of transistor 6 is at a high potential when charging the capacitor 5, and is at a low potential when discharging. Contrary to the configuration shown in FIG. 1.2, this has the effect of lengthening the output logic level 111→1010 delay grinding time.

FIG. 4 shows the same configuration as above, with the gates of the transistors 6 and 6 being grounded. Here, transistor 6
Although the channel resistance is uniform, compared to a configuration without this transistor, even with the same capacitance value of 1°, the resistance of the charging/discharging path is high, so a long delay can be obtained.

FIG. 5 shows a switching signal 7, which switches between the configuration of FIG. 2 and the configuration of FIG.
8 to control enhancement transistor 9.
Added a switching circuit of lO, the switching signal 7 is @1”8
When is 101, transistor 9 is conductive, and when output 2 falls at 7, when 1018 is 111, transistor IO is conductive, and the delay in the rise of output 2 is emphasized.

As explained above, the present invention is a simple delay circuit that applies the storage and discharge time of one capacitance. It is characterized by variable time. The first application is to control the gates of the transistors with the same phase of the delayed signal, and the second is to control them with the opposite phase.Furthermore, it is also possible to clamp the gates to a third fixed potential. Finally, at least 2 of the above 1st to 30th conditions
We also proposed a function to switch between one or all of them. The present invention has a remarkable effect in configuring a delay circuit that can arbitrarily control minute time delays with a relatively simple configuration and also allows for more subtle modulation.

[Brief explanation of drawings]

FIG. 1 is a nine-circuit diagram showing one embodiment of the present invention, and FIGS. 2 to 5 are circuit diagrams showing other different embodiments of the present invention. 1-...Input terminal, 2...Output terminal, 3--
--P board N channel depressing, load MO8) transistor, 4...°-P board N channel enhancement 242 MO8 transistor, 5... Capacity,
6...-P-Based N Channel Depres, John M()8
) transistor, 7,8°°/-° switching signal, 9.10
-°...-P-based N-channel enhancement M for switching
O8) Ran resistor. Figure 1, beginning, figure 2, figure #3

Claims (1)

[Claims] 1. A delay circuit comprising: a depletion field effect transistor that supplies a signal to an output via a source-drain path; and a capacitor that terminates the output.