JPS58123672U - horizontal deflection circuit - Google Patents
horizontal deflection circuitInfo
- Publication number
- JPS58123672U JPS58123672U JP1847882U JP1847882U JPS58123672U JP S58123672 U JPS58123672 U JP S58123672U JP 1847882 U JP1847882 U JP 1847882U JP 1847882 U JP1847882 U JP 1847882U JP S58123672 U JPS58123672 U JP S58123672U
- Authority
- JP
- Japan
- Prior art keywords
- blocking capacitor
- terminal
- diode
- circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Television Scanning (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来方式を示すブロック図、第２図は本考案の
一実施例の回路図、第３図は第２図の波形図である。
２・・・・・・水平偏向回路、５・・・・・・パルス幅
変調回路、−６・・・・・・ドライブ固結。FIG. 1 is a block diagram showing a conventional system, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram of FIG. 2. 2... Horizontal deflection circuit, 5... Pulse width modulation circuit, -6... Drive consolidation.
Claims (1)
線の他端より、ダイオードを通してスイッチング用トラ
ンジ７スタのコレクタ端子杏子Ｗｌｔｅし、同端子にア
ノード側を接続したダイオードを通１て、ダンパダイオ
ード、直流阻止用コンデンサを□接続した偏向ヨーク及
び共振回路を並列接続し、さらにその端子ば前記フライ
バックトランスの１− 次巻線と同相になるようにし
た２次巻線左、グイ・オードを直列に接続した構成にお
いて、前記直流阻止用コンデンサに加わる電圧を平滑し
、この電圧を検出し、誤差増幅回路、パルス幅変調回路
により１．前記スイッチングトランジスタのオン期間を
制御することにより、直流阻止用コンデンサに加わる電
圧を常に一定に制御し、電源が変動しても−１一定の偏
向電流及び高圧を供給できることを特徴とする水平偏向
回路。From the other end of the transformer flyback primary winding, one end of which is connected to the power supply terminal, pass through a diode to the collector terminal of the switching transistor 7 stars, pass through the diode whose anode side is connected to the same terminal, and then connect the damper diode. A deflection yoke with a DC blocking capacitor connected in □ and a resonant circuit are connected in parallel, and the secondary winding is connected in series with the left secondary winding so that its terminal is in phase with the primary winding of the flyback transformer. In the configuration connected to the DC blocking capacitor, the voltage applied to the DC blocking capacitor is smoothed, this voltage is detected, and an error amplification circuit and a pulse width modulation circuit are used to perform 1. A horizontal deflection circuit characterized in that by controlling the on-period of the switching transistor, the voltage applied to the DC blocking capacitor is always controlled to be constant, and a -1 constant deflection current and high voltage can be supplied even if the power supply fluctuates. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1847882U JPS58123672U (en) | 1982-02-15 | 1982-02-15 | horizontal deflection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1847882U JPS58123672U (en) | 1982-02-15 | 1982-02-15 | horizontal deflection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123672U true JPS58123672U (en) | 1983-08-23 |
Family
ID=30030730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1847882U Pending JPS58123672U (en) | 1982-02-15 | 1982-02-15 | horizontal deflection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123672U (en) |
-
1982
- 1982-02-15 JP JP1847882U patent/JPS58123672U/en active Pending
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