JPS58123210A - Power source voltage-controlled amplifier - Google Patents

Abstract

PURPOSE:To prevent a breakdown of a transistor (TR) due to the magnetic saturation of a high frequency transformer by holding the maximum of the duty ratio of a control signal applied to a DC-DC converting circuit below 50% even if a transient input signal arrives. CONSTITUTION:An input signal ei from an input signal source 1 is inputted to the preamplifier 13 of an output amplifier 2 and a control amplifier 7. The output signal of the control amplifier 7 is applied to an ampliture limiting circuit 40 to clip the peak part of the input signal through the operation of a resistance 41 and Zener diodes 42 and 43 when the signal level exceeds a Zener voltage, i.e. when the input signal ei is excessive, thereby applying the resulting signal to level shifting circuits 8 and 9. Output signals of the level shifting circuits 8 and 9 are applied to voltage comparing circuits 11 and 12, whose output signals are applied to DC-DC converting circuits 5 and 6. Even if the input signal ei becomes excessive, its duty ratio is held below 50% through the ampliture limiter 40, so high frequency transformers 23 and 24 are prevented from getting saturated and switching TRs 25 and 26 never breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply voltage controlled amplifier suitable for use in power supply amplifiers, particularly audio output amplifiers, etc., depending on the input signal to be amplified. The output amplifier used for this purpose is required to have a relatively large output, since the dynamic range of the signals handled is wide and the efficiency of the speakers used is low.

For this type of amplifier, if an amplifier with a class A amplifier circuit configuration is used, there will be problems with power consumption and heat generation, and the size will become too large, resulting in an excessive cost burden. However, amplifiers with a class B amplification path configuration are often used. This is because class B amplifier circuits have higher power efficiency and generate less heat than class A amplifier circuits, making them suitable for increasing output.

However, as is well known, the power efficiency of an output amplifier having a class B amplifier circuit configuration has a fairly high value of about 78% KU at maximum output, but drops significantly at low output. The average power efficiency when amplifying an audio signal or the like with a large difference between the peak level and the average level becomes a value that is less than the aOS. Therefore, in an output amplifier with a conventional class B amplifier circuit configuration, the amount of heat generated increases as the output increases, making it difficult to design heat dissipation. The disadvantage is that the maximum output that can be extracted is limited and it is difficult to construct a high-output output amplifier.

To solve the above-mentioned nine drawbacks of the output amplifier with the B-class amplifier circuit configuration, the inventors of the present application disclosed in Japanese Unexamined Patent Application Publication No. 51-73
A power supply voltage controlled amplifier was proposed in Publication No. 862 and others. This power supply voltage controlled amplifier uses a switching type DC-DC converter in its power supply section and controls the switching duty ratio according to the magnitude of the input signal to be amplified. By changing the power supply voltage according to the magnitude of the input signal, the output transistor, which is the output element of the amplifier, is always operated in a state close to its maximum output, and the power efficiency of the amplifier can be improved. .

An example of a power supply voltage controlled amplifier according to this prior art will be described below with reference to the drawings.

Figure 1 is a circuit diagram showing an example of a conventional power supply voltage controlled amplifier, in which 1 is an input signal source, 2 is an output amplifier, 3 is a speaker, 4 is a DC power supply, and 5 and 6 are DC-DC. conversion circuit, 7 is a control amplifier, 8 and 8 are level shift circuits, 10 is a carrier oscillator, 11 and 12 are voltage comparators,
13 is a preamplifier, 14 and 15 are output transistors,
16 and 17 are AC voltage input terminals, 18, 19, 20 and 21 are full-wave rectifier diodes, 22 are smoothing capacitors 23 and 24 are high frequency transformers, 25 and 26 are switching transistors, 21 and 28 are pulse transformers, 2L30 , 31, 32, 33 and 34 are diodes, 35 and 36 are check coils, and 31 and 38 are capacitors.

In Fig. 111, the DC power supply section 4 includes full-wave rectifying diodes 18 to 21 and smoothing diodes 18 to 21 and smoothing diodes 18 to 21. 22, and rectifies and smoothes the commercial AC applied to the AC voltage input terminals 16 and 17. , 33, is composed of a circuit 35 and a capacitor 31,
DC voltage tube voltage comparator 11 to which DC voltage is applied from DC power supply unit 4
The positive voltage + is varied by the control signal es(+) from
ef occurs. DC-DCC conversion circuit 6, diode 3
It is configured exactly the same as the DC-DC conversion circuit 5, except that the connection direction of the circuits 2 and 34 is opposite to that of the DC-DC conversion path 5, and the DC voltage applied to the DC power supply section 41p is converted to a voltage comparator. The control signal @5(-) from 12 is varied by 19 to produce a negative voltage -C''. The input signal source 1 is configured with an output transistor 14.Is to which positive and negative voltages +e and -C are applied as power supply voltages.
It amplifies the input signal from the input signal eo and drives the speaker 3t as an output signal eo.

Hereinafter, the operation of the power supply voltage controlled wave amplifier according to the prior art having the above-mentioned configuration will be explained using waveform diagrams shown in FIGS.

The input signal to be amplified as shown in Figure 2 (heat) from the input signal source 1 is input to the preamplifier 13 of the output amplifier 2, and the zero output amplifier 2 is input to the control amplifier 1 at the same time. , this input signal is amplified by the preamplifier 13 and the output transistors 14 and 15, and outputted to the speaker 3 as an output signal e6. On the other hand, the nine-power signal ei[, which is input to the control amplifier T, is amplified to a suitable level by the control amplifier 1, and is applied to the level shift circuits 8 and 9. The level shift circuit and the control amplifier 1 apply [LR of -ΔEo and +ΔBo to the good signal, respectively.
Superimposing a voltage to level shift the signal, 111
Waveforms j'i('') and @1( shown by solid lines in 21m(b)
-) output signal tone is generated and applied to one input terminal of voltage comparators 11 and 12. The other input voltage &C of the voltage comparators 11 and 12 is IIz from the carrier oscillator 10.
A carrier signal shown in waveform e (closed) is applied in the figure (b).

As is clear from the second factor Φ), this carrier signal Cc has a repetitive triangular waveform, and its repetition frequency is a sufficiently large value compared to the maximum wave number of the input signal el.
For example, if the input signal ei is an audio signal, approximately 20
It is set to a value of about 0 kHz. The voltage comparator 11 is
Compare this carrier signal e (and the output signal @?('') from the level shift circuit 8, and when %ec<C1(+), an output pulse is generated.0 This output pulse is a DC
- It is used as a control signal es('') to control the DC conversion circuit 5, and becomes a pulse train as shown by the solid line K in FIG. (and the output signal e from the level shift circuit 9
'i(-), and when ec>ei(-), an output pulse is generated.

This output pulse H1 is used as a control signal es(-) for controlling the DC-DC conversion circuit 6, and becomes a pulse train as shown by the solid line in FIG. 2(d).

These control signals as(+) and es(-) are connected to the input signal ei as can be seen from FIGS. 2(C) and 2(d).
This is a so-called pulse width modulation signal in which the pulse width changes depending on the magnitude of the signal, and the voltage comparators 11 and 12 operate as pulse width modulators.

The DC-DC conversion (b) path 5 receives the input signal eiK↓repulse width modulation, and the control signal ag('') is a pulse transformer.
・Input to 1 27 and controls the magnitude of its output voltage +゛e. That is, the control signal es('') input to the pulse transformer 27 is applied to the switching transistor 25t-
On/off control, high frequency transformer 2 from DC power supply section 4
The DC power supply supplied to the primary winding of No. 3 is controlled intermittently. For this reason, the
The positive output voltage +e obtained through the rectifier circuit consisting of the diodes 31 and 33, the smoothing circuit consisting of the choke coil 35 and the capacitor 37 changes according to the input signal ei in the positive region of the input signal ei, and el has a constant value in the negative region. DC-DC conversion circuit 6
operates similarly, and its negative output voltage -e is equal to the input signal e
4 changes according to the input signal e4 in the negative region, and has a constant [1 in the positive region of the input signal ei.

Positive and negative output voltages +C of DC-DC conversion circuits 5 and 6
and -elf are supplied to the output transistors 14 and 15 as the power supply voltage of the output amplifier 2.

At this time, FIG. 2(e) shows the relationship between the output signal e6 of the output amplifiers 2 and the power supply voltages +, C, and -e supplied to the amplifier 2. That is, the power supply voltage + applied to the output amplifier 2 from the DC-D, C conversion circuits 5 and 6
C and -0 are controlled so that the difference voltage (hereinafter referred to as offset voltage) with the output signal e of the output amplifier 2 becomes EO as shown in FIG. 2(e). ;[, is the voltage required to actively operate output transistors 14 and 154, typically several volts 11! A small voltage on IIL is sufficient. Therefore, the output transistor on the side that supplies the output current to the speaker 3 has the above-mentioned small differential voltage KO that is always constant.
As a result, the power loss of the output amplifier 2 is significantly reduced compared to an amplifier with a class B amplifier circuit configuration, and the power efficiency is also high. (Control signals em(+) and es (
−) can be obtained by giving an offset to the control signals esD) and es(−), which are output from the voltage comparators 11 and 12 when there is no input signal el, that is, when there is no signal. Make DC-
I decided to set the value of the DC voltage to be superimposed on the input signal Ci in the level shift circuits 8 and 8 so that the output voltages 10 and -C of the iJc conversion circuits 5 and 6 become +E and -E, respectively. The resulting image, Figure 2(e)
, the output voltage of the DC-DC conversion circuits 5 and 6 +C
Although the waveforms of the carrier signal eC and -C are smoothly expressed, the frequency component of the carrier signal e(0) is actually included as a frequency component pipe ripple of the carrier signal eC from the carrier oscillator 10. It is sufficiently high compared to
In the conventional power supply voltage control amplifier described above, when the magnitude of the input signal e1 becomes excessive, the DC - There is a problem that the DC conversion circuits 5 and 6 cannot operate normally. 0 In other words, the level of the input signal e4 exceeds ΔEl, which is the magnitude of the DC voltage superimposed on the input signal by the level shift circuits 8 and . and the output signals of the level shift circuits 8 and 9 are IN2
The waveform becomes as shown by the KJIi line in the figure Φ). As a result,
Voltage comparators 11 and 12 operating as pulse width modulators
The waveforms of the control signals es('') and C@('') that are output as shown in FIG. big,
That is, the pulse train has a duty ratio of 50- or more. However, in a switching type DC-DCC conversion circuit that generally uses a high-frequency transformer, when the duty ratio of the control signal pulse train becomes 50 or more, the high-frequency transformer becomes saturated and an excessive voltage is applied to the switching transistor. There is a problem that the transistor is destroyed.

The reason for this will be explained below using diagrams tjlIa and FIG.

Diagram 1s3 is a nine circuit diagram by extracting only the 5 parts of the DC-DC conversion circuit from Figure 1, and Figure II4 (a) e (b), (
C), (d) and (e) are rounding waveform diagrams illustrating the operation tube of the third factor.

Now, the operation of FIG. 113 will be explained in the case where the duty ratio of the control signal Cs applied to the pulse track 29 in FIG. 3 is 5011G or less.
The operating waveforms of each part of the DC conversion circuit are shown by solid lines in FIG. Control signal C applied to pulse transformer 2T
$ has a ↓ waveform shown by the solid line in Figure 4 (a), and T
The switching transistor 25t is turned on during the ON period, and the transistor 25 is turned off during the TOIFF period. While the switching transistor 25 is on, the primary current jc from the DC power supply section 4 flows through the primary winding ftAN1 of the high frequency transformer 23, the diode 31 is turned on, and the fourth figure(
e) A secondary current jpl indicating K flows. The primary winding N of the high frequency transformer 23 and the switching transistor 25
The primary electric current R1c flowing in is shown in Figure 4 (C) ↓
The primary and secondary windings 11N1 and N2 of the high-frequency transformer 23 are
The turns ratio of , that is, N2/N1 times is added, and the magnetic flux density of the high frequency transformer 23 [B is 112WA
, 1(d), the voltage VOE applied between the collector, emitter, and ivy of the switching transistor 25 is $4.
As shown in Figure-), it is almost zero.

When the switching transistor 25 is turned off, the primary 11111NI of the high frequency transformer 23 is turned off! jct!
It becomes zero, and the diode 314 turns off. Instead, the diode 2I is turned on, and the tertiary winding current fi1m shown in FIG. 4(C) flows through the secondary winding MNs, and the diode 33 is turned on, and the secondary current tpl shown in FIG. 4(e) K flows. . The tertiary winding N number is the same as control 1 (No. 1 C3 increases during the period of Ton, e.g., 1. A, 23 wires and bundles, e. 1%. If a demagnetizing action is performed to return it to zero during the 110 period, it becomes the same. , control signal C8
is consumed during the Toll period, and is returned to the power supply section 4 for one offset during the TOPIF period [1[fi]. Furthermore, if the number of turns of the tertiary winding Ns of the high-frequency transformer 23 is made equal to the number of turns of the primary winding N10, the period τOFF during which the magnetic flux density B of the high-frequency transformer 23 returns to zero is approximately equal to the period of Tom of the control signal es. The voltage VCFi it applied to the switching transistor 25 during this period becomes twice the power supply voltage El from the DC power supply unit 4, as shown in FIG. 4(b).

The secondary currents jpl and iD2 described above flow through the first coil 35 as a current i1, and their average current IO is supplied to the load device 39.Next, the death-stay ratio of the control signal C is The case where the number exceeds 5011 will be explained. In this case, the control signal es applied to the pulse transformer 2T has a waveform tube as shown by the dotted line in FIG. Control off. This means that the duty ratio of the control signal Cs described above is s
The operation is the same as when it is on or below. When the duty ratio of the control signal es is 501 or more, it is natural that the relationship between the Ton period and the TOFF period described above is
＞Toll'OAlso, as described in the explanation of the operation when the data ratio of the control signal es is 50% or less, the magnetic flux density B of the high frequency transformer 23 becomes completely zero.
It takes a time t equal to the period of #1 TON. Therefore, as mentioned above, TON > TOFF
In the case of , the magnetic flux density of the high-frequency transformer 23 [B is the control signal es') before it becomes completely zero)TOF? As a result, the magnetic flux density B of the high-frequency transformer 23 gradually increases as shown by the dotted line in FIG. 4(d), and the high-frequency transformer 23 reaches magnetic saturation. Resulting in. As a result, an excessive current flows through the switching transistor 25, resulting in destruction of the transistor 25'.

If the number of turns of the tertiary winding Ns of the high-frequency transformer 23 is made smaller than the number of turns of the first-order winding Nl, the time for the magnetic flux density B of the high-frequency transformer 23 to return to zero, fOFF, will be shorter than the period of the tube TON. It is possible and there is 1
! Although the nine situations described above can be avoided, on the other hand, the voltage VclC applied to the switching transistor 25 is
This becomes more than twice the power supply voltage Ei from the DC power supply unit 4, and the withstand voltage of the switching transistor 25 becomes a problem. In any case, it is impossible to use the DC-DC conversion circuit with the duty ratio of the control signal t100%, so some kind of restriction is necessary.

As explained above, in the conventional power supply voltage controlled amplifier, when the input signal to be amplified becomes excessive, the high frequency transformer in the DC-DC conversion circuit that supplies the power supply voltage is magnetically saturated and the switching transistor The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide highly reliable power supply voltage control that operates stably even when an excessive input signal is applied. K provides a type of amplifier.

In order to achieve all of these objects, the present invention provides a DC-DC conversion circuit that supplies the entire power supply voltage by providing an amplitude limiting circuit tube for limiting the amplitude of an input signal in the preceding stage of a voltage comparator that operates as a pulse width modulator. The duty ratio of the control signal for controlling the DC-DCf conversion circuit is limited to 50% or less, so that the high-frequency circuit lance of the DC-DCf conversion circuit does not magnetically saturate even when an excessive input signal is input. 0 Below, an embodiment of the voltage controlled amplifier according to the present invention will be explained with reference to the window surface.〇 Figure 5 is a circuit diagram showing a first embodiment of the power supply voltage controlled amplifier according to the present invention. Reference numeral 40 denotes an amplitude limiting circuit, and the portions corresponding to those shown in FIG. 1 are equipped with the same code tube.

1161m is the 5th floor! ! ! FIG. 3 is a waveform diagram showing voltage waveforms at various parts of J.

Next, the operation of this embodiment will be explained.

In FIGS. 5 and 6, the sixth meat (
The input signal ei shown in a) is input to the preamplifier 1 of the output amplifier 2.
3 and the control amplifier 7 are I! This is the same as in Figure 1. The output signal of the control amplifier 7 has an amplitude of
@When the output signal level of the control amplifier T becomes higher than the Zener voltage of the Zener diodes 42 and 43 due to the action of the resistor 41 and the Zener diodes 42 and 43 applied to the circuit 40, that is, the input signal e1 becomes excessive. At this time, the peak portion is clipped and applied to the level shift circuits 8 and 9. The level shift circuit and 9 superimpose DC voltages of -ΔE and +ΔE on the applied signal, as in the case of the prior art shown in FIG. As mentioned above, the output signal of the amplitude limiting circuit 40 is equal to the input signal e.
i (1)9! When the i level becomes excessive, its peak portion is clipped, so the output signals ei (ri and cl(-)) of the level shift circuits 8 and 8 are expressed as shown in FIG.
), the waveform has the portion indicated by the dotted line removed. As a result, output signals e't(-) and e'5(-) of the level shift circuits 8 and 9 are output from voltage comparison circuits 11 and 12 which operate as pulse width modulators. The control signals es(+) and em(-) become pulse trains as shown in FIG. The amplitude limiting (b) circuit 40 input to the circuits 8 and 9 does not increase beyond the duty ratio corresponding to the input signal subjected to the limit.Amplitude limiting circuit 40K
Low amplitude limiting level, i.e. Zener diode 42
and 43 Zener voltages are applied to level shift circuits 8 and 9.
The DC voltage ΔEic4B, which is superimposed by Also, its duty O ratio is 50.
- The high frequency transformers 23 and 24 of the DC-DC conversion circuits 5 and 6 will not cause magnetic saturation, and therefore the switching transistors 25 and 26 will not be destroyed.

The control signal ag ( applied to the DC-DCC conversion circuits 5 and 6
”) and the duty ratio of es(-)
By la, DC-DC conversion (b) paths 5 and 6
When the input signal 61 becomes excessive, the output voltages +C and -C and the output signal eQ of the output amplifier 162 applied with this output voltage as the power supply voltage are controlled as shown in FIG. 6(e). However, so that the output at this limit level becomes the maximum output, 1) the turns specific gravity of the primary winding and secondary winding of the high frequency transformers 23 and 24 of the C-DCC conversion circuits 5 and 6 is set. If you do that, you'll get 1.

7 is a block diagram illustrating another embodiment of the voltage-controlled amplifier □ according to the present invention, in which the amplitude limiting path is composed of a resistor 46 and a diode 48;
and an amplitude limiting circuit 4 consisting of a resistor 47 and a diode 49.
These amplitude limiting circuits 44 and 45 are divided into two parts, ie, level shift circuits 8 and 9 and a voltage comparison circuit 161.
It differs from the first embodiment shown in FIG. That is, the level shift circuit 8
When the output of the level shift circuit 9 becomes positive, the diode 48 turns on, and the amplitude of the signal e's applied to the voltage comparator 11 is limited. Conversely, when the output of the level shift circuit 9 becomes negative, the diode 49 turns on. Thus, the signal e'1(-) applied to the voltage comparator 12 is amplitude limited. Therefore, the signal waveforms at each part in this embodiment are as shown in FIGS.
The waveform is almost the same as the one shown. However, the signals e's(ri and e'!(-) applied to the voltage comparators 11 and 12 become positive and negative, respectively, by the forward voltage of the diodes 48 and 49, so the voltage comparator 11 and f, 2 output signals from DC-DC conversion circuits 5 and 6 'y>?
The maximum value of 1 duty ratio of the rJ control signal CI(ri and as(-)) will slightly exceed 50-.

FIG. 8 is a preset diagram showing still another embodiment of the power supply voltage control section amplifier according to the present invention, in which the amplitude limiting circuit 4
A resistor 52 connected to a power supply terminal 54 to which a negative voltage is applied is connected to the cathode IIK diode 50 of the diode 48 in 4, and a diode 51 and a positive voltage are applied to the anode side of the diode 49 in the vibration limiting circuit 45. This embodiment is different from the embodiment @2 shown in the seventh factor in that the ninth resistor 53 is connected to the power supply terminal 55.

Diodes 50 and 51 are kept on at all times by a negative voltage applied to resistor 52 and terminal 54 and a positive voltage applied to resistor 53 and terminal 55, respectively, and diodes 48 and 49 are level shifted. When the circuits 8 and 9 are turned on by the signal pressure applied to them, their forward voltage t cancels out. This ninth, voltage comparators 11 and 1
The signals e'i(ri and @'1(-) applied to 2 do not exceed zero level and become positive and negative, respectively.
DC-1)C which is the output signal of voltage comparators 11 and 12
The duty ratio of the control signals em(+) and es(-) applied to the conversion circuits 5 and 6 does not exceed 5ost. Moreover, if the diodes 50 and 51 are connected in series, the control signals es(+) and es(
−).

FIG. 5 is a block diagram showing still another embodiment, in which a carrier signal eC from a carrier oscillator '10 is transmitted through a diode 5;
6. The level is adjusted by a bell shift circuit consisting of the wax resistor 58, a positive voltage source applied from the power terminal 55, and a level shift circuit consisting of the diode 51, resistor 59, and a negative voltage source applied from the power terminal 54. Shifted and '! 'c
('') e e'c (-) as voltage comparator circuit 1
1 and 12, and when the carrier signal ECT level shifts, the control signal C3 is applied to the forward electric-DC conversion paths 5 and 6 when the diodes 48 and 49 are turned on. The duty ratio of (+) and es(-) never exceeds 5oft.

FIG. 1 is a block diagram showing still another embodiment of the power supply voltage controlled amplifier according to the present invention, in which a transistor 6
0 and 61, the carrier signal e (t level shift), the forward voltage t when the diodes 48 and 48 are turned on is set to 15, and the transistors 60 and 61 level shift the carrier signal Cc. ) as well as the function of impedance conversion.As explained above, according to the present invention, no matter how excessive the input signal is, the DC-DC conversion can be performed. Since the maximum value of the duty ratio of the control notes applied to the circuit can be kept below 50 -, the disadvantage of the conventional technology that the high frequency transformer becomes magnetically saturated and completely destroys the switching transistor is eliminated, and power efficiency is improved. I! We can provide highly reliable, large output power supply voltage controlled amplifiers with zero

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of a conventional power supply voltage controlled amplifier, Fig. 2 (a) to e) is a waveform diagram illustrating the operating sound of Fig. 1, and Fig. 3 is a DC- The circuit diagram for explaining the operation of the DC conversion circuit, FIG. 4(a) to e) is #! 1 is a waveform diagram for explaining the operation of the DC-DC conversion circuit; FIG. 5 is a circuit diagram showing the first embodiment of the power supply voltage controlled amplifier according to the present invention;
) is a waveform diagram to explain the operation of diagram W45, @ diagram 7,
! FIGS. 8, 9, and 10 are circuit diagrams showing embodiments of III2 to IF5 of power supply voltage controlled amplifiers according to the present invention, respectively. 1...Input signal source, 2...Output amplifier, 3...2 speakers, 4...DC power supply section, 5.6...・DC-DC conversion-path, 1...
...Control amplifier, 8,9... Level shift circuit, 10...Carrier oscillator, 11#12.
...Voltage ratio softener, 4G, 44.45...
Amplitude limiting circuit. Agent: Patent Attorney 1 Kenjibe Take (and 1 other person) Figure 1 W42 Figure 5 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1) Driven by a pulse whose width is modulated by the input signal 1) A voltage that changes according to the input signal obtained from a C-DC conversion circuit is used as a power supply voltage, and the input signal is amplified. In the power supply voltage controlled source amplifier, an amplitude limiting circuit is provided to limit the amplitude of the input signal to be modulated by the pulse width within a predetermined range, and the duty ratio of the width modulated pulse is set to a predetermined value. An amplifier made of power supply voltage control and having a characteristic of 9%, which can be constructed as follows.