JPS58123141A - High-speed count branch executing system - Google Patents

Abstract

PURPOSE:To actuate the executing function of an instruction while a loop is repeated with virtually zero time, by substituting a count branch by-pass register provided to control the loop frequency for the function of a numerical branch instruction. CONSTITUTION:A numerical branch instruction is first set to an instruction register 4, and then an effective numerical value display F/F(E)11a is set at a time point when the numerical branch instruction is decoded at an instruction decoder 5. Thereafter, a loop is reset by an AND circuit 13 when it ends. However, the loop functions to show a numerical branch bias register (BBR)11 is effective until it is reset by a comparator 14 when the GRN (general-purpose register number) of a GRN holding part 11-1 held at the BBR11 is identical with the number of a general-purpose register 8 which is used for other instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed counting branch execution method that allows an information processing device to execute a program at high speed by repeating the same counting branch instruction many times.

Conventionally, this type of information processing device uses counting branch instructions (hereinafter referred to as B
(referred to as a CT instruction), the corresponding B
After reading the CT instruction from the main memory (which may exist in a cache or instruction cache memory) or from an instruction buffer, a designated general register (GR) is read and a counting operation is performed. In other words, in a program that configures a loop that repeats the same BCT instruction many times, the role of the BCT instruction executed midway through the loop is simply to manage the number of loops. Each time the command is repeated, the command is retrieved and executed again.

Therefore, the purpose of the present invention is that the BCT instruction does not require the execution time equal to the number of loop repetitions, and the program execution performance deteriorates. When repeating the loop, the above drawback is eliminated by substituting the function of the 5BCT instruction with a counting branch register provided to manage the number of loops. The purpose of this invention is to provide a high-speed counting branch execution method that can operate in apparently zero time.

According to the present invention, in an information processing device that counts the value held by a specified general-purpose register, determines whether or not to branch based on the counting result, and executes a counted branch instruction,
An address supply circuit that supplies a prefetch instruction address, a counting circuit that counts a count value, a monitoring instruction address that monitors whether a counted branch instruction is scheduled to be executed, and a prefetch instruction that is supplied from the address supply circuit. It includes an address comparison circuit that compares the address with the address, and one or more sets of counting branch pi/gus registers, and the counting branch pi/gus register includes the general-purpose register number of the general-purpose register and the count value held by the general-purpose register. , a branch destination address, and the monitoring instruction address, respectively, and when a counting branch instruction is executed, information corresponding to the counting branch instruction is set in the counting branch path/zoos register, and the address comparison circuit sets the information corresponding to the counting branch instruction. If it is found that the counted branch instruction is scheduled as the next instruction to be preempted, the counting circuit is activated and the instruction is preempted at the previous branch branch destination address according to the content of the counted value. A high-speed counting branch execution method in an information processing device can be obtained.

Next, the high-speed counting branch execution method according to the present invention will be explained in detail with reference to the drawings.

Figure 1 shows the format of an example of the instruction type applied to this invention: 1. As seen in this figure, there are RR type and RX type of instructions. ,life·
In addition to specifying the type of operation with the instruction code (op),
and the second operand is designated by R1 and R2 (or X2r82+D2), respectively. R1 and R2 give the numbers of general registers (GR) or pace registers (BR). Alternatively, the content of BR becomes the first or second Euland. X2 gives the GR number (GRN), and the contents of the designated GR serve as an index value for the address of the second operand.

B2 gives the number (BRN) of the BH, and the contents of the specified BR serve as the basis for the address of the second operand.

The value of D2 serves as a displacement of the address of the second OK land.

That is, the second wave land designated by +X2+B2 and D2 is designated as the data in the main memory indicated by the address created by adding the contents of the designated BR and GR and D2. In this example, the instruction format is limited to the above two types, but it goes without saying that various types known in the prior art, such as RI, XX, etc. may also exist.

In the present invention, the BCT instruction targeted for speedup uses a count value (CN) that controls the number of loops in the first operand.
, and the second operand indicates the branch destination instruction to be branched to when the total number of CN results is not ``0''. In other words, the address of the second osland is the branch destination address (BA
). Therefore, the logical operation of the BCT instruction is to read CN from the specified 〇R every time the instruction is executed, count it, write the result to the specified GR and return it to ``0'', and if the result is a fist, the next in the sequence is ``0''. 0”/
If the instruction 1 is not ▼, the instruction sequence is changed so that the instruction indicated by BA is executed in the next line. With this, the branch destination instruction and BC are executed as many times as given by the first CN.
A loop surrounded by T instructions is specified to be repeatedly executed.

FIG. 2 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, an address supply circuit (IAC) 1 serves to supply the address of a prefetch command to an instruction cache circuit (IC) 2 in order to read the instruction held by the IC 2 before execution. The IC2 is a cache dedicated to instructions, but it may be configured so that it can be shared with an Otakuland cache circuit (OC) 9, which will be described later, and holds a copy of part of the data in the main memory (not shown). Then, the instruction is read out according to the given preemption instruction address. The data width read from IC2 is 4 bytes and may include two instruction parts, so the instruction boundary alignment circuit (AL) 3 aligns the contents of part of the instruction register (IR) 4 The next instruction to be executed is arranged with the left end aligned with the output of IC2, and then is given to IR4. The IR4 holds the instruction to be executed, the issued instruction code is decoded by the instruction decoder 5, and the address addition circuit (AA) 5 outputs instruction information while the second address is being calculated. be done.

When the pace reno star (BR) 7 receives BRN from the IR4 to the read address (RA) input terminal, the contents of the specified BR are output from the read data (RD) output terminal, and the write address (WA) input terminal, Writing is performed by applying BRN and write data to the write data (WD) input terminals. The general-purpose register (GR) 8 is designed so that reading can be performed on two registers in parallel.
The configuration is otherwise similar to BR7 except that there are two input terminals, RIA) and (R2A), and two output terminals, read data (RID) and (R2D). OC9 is a cache circuit that holds memory operands and transfers the operand data to the operation execution unit (EU).
10 to execute the arithmetic operation.

The counting branch bypass register (BBR) 11 forms a feature of the present invention, and in this embodiment, only one set is present, accompanied by a valid indicator F7/F(E)11a. A plurality of BBRs 11 may be provided, in which case high-speed processing becomes possible for a program in which multiple loops are composed of a plurality of BCT instructions. Ella is another form,
For example, store the value of an address that the program will never use as a monitoring address (SA) in the BBR11. This allows them to have the same functionality. BBR
11 includes a GRN holding unit 11-1. CN holding section 112.
There is a BA holding section 11-3 and an SA holding section 11-4, and when a BCT instruction is decoded for the first time, the corresponding values are set to 7. That is. The content of GR8 indicated by R1 is set as R++CN of the BCT instruction as GRN, and the second Euland address is set as BA.

Also, as SA, in order to pre-empt the corresponding BCT command,
The preemption instruction address previously given from AC1 is set after the timing adjustment is performed by the adjustment register 12.

In such a configuration, first the BCT command force - IR4
Then, when the instruction is decoded by the instruction decoder 5, E11aAf is set. Thereafter, when the loop ends, it is reset by the AND circuit 13, but the GRN holding unit 1 held in the BBR 11
When the GRN-Af of 1-1 is the same as the GR number used in another instruction, it works to indicate that the BBR11 is valid until it is reset by the comparator circuit 14. Also, in this example, the address of the BCT instruction is used as d and SA, but depending on the structure of the line, the address of the instruction preceding the BCT instruction or an appropriate address according to the unit of access to the IC may be used. It may be an address, and essentially any address that can detect whether or not it is an instruction-7EBCT instruction that should be preempted may be used. Corresponding information in BBR11: When set, a value is written to register "0" designated by R1 of GR8 using selection circuits 15 and 16. This means that 11 is written in advance of "0" because the contents of "0" 7GR8 specified at the end of the loop should be ψ. At the same time, C
The value of the content of the N holding unit 11-2 is decreased by "1#" by the counting circuit (CTR) 17.
Corresponds to counting operations by executing instructions.

The contents of the SA holding unit 11-4 are always compared with the preemption command address given from IAC1 in the address comparator (ACP) 18 when Ellai: is set, and when the result shows a match, the content is read from IAC1. The prefetch instruction at 9 is selected by the selection circuit 19 and the selection circuit 20
It works to convert to the value given through. This p
During the number of loops indicated by , CN, the branch destination instruction is preempted at the timing of prefetching the BCT instruction on behalf of executing the BCT instruction. On the other hand, the contents of the CN holding unit 11-2 are changed to CTR1 every time the ACP 18 indicates a match.
7 and reset, and compared with "1" in the comparison circuit 20. If the comparison circuit 2o detects a match, the next BCT instruction indicates the end of the loop. , the address selected by the selection circuit 21 and given to the selection circuit 19 is such that the output of the address adjustment adder circuit (ATA) 22 is selected instead of the previous contents of the BA holding section 11-3. Naru.AT
A22 is an adder circuit for giving the address of the instruction next to the BCT instruction from the address of the BCT instruction held in the SA holding unit 11-4, and it calculates the position of the BCT instruction within the 4-byte boundary and the length of the BCT instruction. The additional value differs depending on the size.

When the end of the loop is detected by the comparison circuit 20, A
CP]8 detects a match, the AND circuit 13 operates and resets Ella. In addition to disabling BBR11, the output of ATA22 is selected as the prefetch instruction address given by selection circuit 19.21, and the sequence is changed so that the instruction next to the BCT instruction is read out, thereby ending the loop. Terminate it.

On the other hand, the comparator circuit 14 operates while the BBR 11 is working effectively. If a register with the same number as GR8 of the GRN holding unit 11-1 is used by another instruction, the function of the BBR 11 is canceled because the GRS does not contain the correct contents at that time. That is, when the comparator circuit 14 detects that the instruction in the IR4 specifies the same GRN as the GRN held by the GRN holding unit 11-1, the IR4
During this period, the contents of the GRN holding section 11-1 are given as a write address (WA) to the GR8 through the selection circuit 15, and the contents of the CN holding section 11-1 are given as a write address (WA) to the GR8 through the selection circuit 15.
By giving the contents of 2 (the contents that the designated GR should hold at this point) to GR8 as write data (WD) through the selection circuit 16, the contents of the designated GR can be corrected. Fix it and reset Ella.

Finally, the effects obtained by the above embodiment will be explained with reference to the BCT instruction execution time chart of FIG. In this example of a time chart, the instructions are arranged in the order of AllA21A31B and C on the main memory, and the instructions are B.
is shown as indicating the BCT instruction and BA as indicating the instruction AI. Now, when executing instruction B for the first time, BBR11
Since the contents have not yet been prepared, the BCT instruction takes three clocks to execute as in the conventional device, and then branches to the instruction Al. Note that each instruction requires three clocks to execute each individual instruction, but as is known in the prior art, since the pipeline control method is adopted, if the Nog Iso Line works well enough, , it appears that one instruction is executed in one clock. However, the branch operation performed by the BCT instruction disturbs the instruction sequence, and normally the effect of the z4' Eve line disappears. The first instruction sequence AI-A2-A3-B-A. seen in the time chart.
shows this fact. The BCT instruction (instruction B) in the loop is rarely executed as an instruction because the BBR 11 is working. Then, the instructions are executed in the sequence Al-A2-A3-Al, . . . , and all the instructions are apparently executed in one clock, so that the no-quip line works ideally. Instruction A being repeated from the second time onwards in the time chart. The following illustrates this fact. At the end of the loop, the BBR 11 detects the end of the instruction, and the sequence moves to instruction C without executing the BCT instruction (instruction B). This can be seen in the last step in the time chart.

As is clear from the above description, according to the present invention, by correctly controlling the instruction sequence without apparently executing the BCT instruction except when the counting branch path register is first given, , BCT instructions can be executed at high speed, and a great effect can be obtained in improving processing efficiency.

[Brief explanation of the drawing]

Fig. 1 is a format showing an example of an instruction type applied to the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment according to the present invention, and Fig. 3 is an execution of the BCT instruction in the embodiment of Fig. 2. It is a time chart for explaining an example. In the figure, 1 is an address supply circuit (IAC), 2 is an instruction cache circuit (IC), and 3 is an instruction boundary alignment circuit (AL).
), 4 is an instruction register (IR), 5 is an instruction decoder, 6
is the address adder circuit (AA), 7 [base reno star (B)
R), 8 is a general-purpose register (GR), 9 is an overland cache circuit (QC), 10 is an arithmetic execution unit (EU), 11
is the counting branch bias register (BBR). 11a is the valid display F/F (E), 11-1 is the general register number (G
RN) holding unit, 11-2 is a count conversion (CN) holding unit, 113 is a branch address (BA) holding unit, 11-4 is a monitoring address (SA) holding unit, 12 is an adjustment register, and 13 is an AND circuit. , 14.20 is a comparison circuit, 15, 16, 19.21 is a selection circuit, 17 is a counting circuit (CTR), 18 is an address comparator (ACP), 22=
is the address adjustment adder circuit (ATA) 0 232-

Claims (1)

[Claims] 1 Count the ◆ peak value held in the specified general-purpose register,
In an information processing device that executes a counting branch instruction by determining whether or not to branch based on the counting result, an address supply circuit that supplies a prefetch instruction address, a counting circuit that counts a count value, and a counting branch instruction an address comparison circuit that compares a monitor instruction address for monitoring scheduled execution with a prefetch instruction address supplied from the address supply circuit; and one or more sets of counting branch bypass registers; The branch bypass register includes a part that holds the general-purpose register number of the general-purpose register, the count value held by the general-purpose register, the branch destination address, and the monitoring instruction address, and when the counting branch instruction is executed, the counting branch Information corresponding to the instruction is set in the counting branch bypass register, and when it is determined by the address comparison circuit that the counting branch instruction is scheduled as the next instruction to be preempted, the counting circuit is activated and the counting branch bypass register is set. A high-speed counting branch execution method in an information processing device, characterized in that a branch instruction is prefetched at the branch destination address according to the contents of a count value.