JPS5812295A - Dimming system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dimming method that can dim a plurality of lighting loads all at once or individually. The requested optical system Fi is shown in Figures 1 and 2 as shown in Figures 1 and 2, and the commercial power supply (1) is t! ￥1 (!-j.

Trigger pulse of triac (4) for lighting load control (
PT) to illuminate the lighting loads (5a) and (5b) respectively, and nine side dimmer circuits (3m) and (3b),
- light operation unit body υ. Synchronous circuit - is the second
Figure (a) As shown in K, the double-wave rectified voltage (EAc) that has been step-down rectified by the step-down transis- sion (TI) and the diode bridge (DB) is connected to the base of the transistor (Qυ) via the zener diode (W, ). When applied, the next power synchronization pulse (P2) is output in synchronization with the zero 901 point of the commercial power supply voltage (vAc).(R1) to (R,)F in the figure
i resistance, resistance, (Dt is resistance, iode, (C+) a resistance, (ZD2) #-19 energy resistance.

Individual, dimming circuit (3m) (3b) consisting of a relaxation oscillator circuit
It is as shown in Fig. 2(b)K, and the transistors (ra) (q), diodes (Dt), (Ds), and
Tarama Puruyu Unijakushi 3: J Trasisista (PUT
), M anti(Ro) ~ (R+m), Konij Desisa (C,
) (C,) Phase 317 Strasis (T,)K is configured and is delayed by a preset phase from the falling edge of the power synchronization pulse (Pz) input to the pace of the trough register (Qs). A trigger pulse (PT) is generated to fire the try hook 1411. The delayed phase of the tri-force pulse (Pl,) with respect to the power synchronization pulse (Pz) is the voltage applied to the base of the transistor (Q,), that is, the dimming operation shown in Fig. 2(c). The dimming level control voltage (El, XEb7t') set by the individual dimming level setting filter (VRa) of the part key υ (and the collective dimming level setting faucet ((VRI)K) is determined. In the figure, - is a DC power supply, ((Q,)Fi+5 resistor, (R14) is a resistor.Therefore, each lighting load (5m) (5b)K is provided with a corresponding meter for individual dimming and bell setting ( VRa
) (VRb), each lighting load (5m
) (5b) By operating the collective dimming fader (VRu), the dimming level of (5b) can be individually controlled.
The dimming level of the lighting loads (51) (5b) can be controlled all at once. However, such a conventional example has the problem of being difficult and expensive. The present invention has been made in view of the above points.

Embodiments will be explained below with reference to the drawings. 1, 3, and 4 show an embodiment of the present invention, and FIG. 3 shows a synchronous circuit (2a), which is a conventional synchronous circuit. -, the auxiliary winding M (L, , > and parallel to the auxiliary winding M (t, s)) is connected to the step-down transis- sion (T,) of the auxiliary winding M (t, s). , ] Shijishisa (C
1) Step-down system (T,) by changing the capacity of
By changing the phase shift between the electromotive force ratio (VtJ) and the primary winding 1ia (Ll) induced in the secondary winding m(1,,) of the The synchronizing pulse (Pc) generated in synchronization with the t!o zero point of , The constant phase (θ) lags when the synchronous pulse (Pc) is delayed by a certain phase (θ). Phase shift (lI)
are shown respectively. In the figure, (ED) is the divided voltage, (E
z) is the Zener voltage. Figure 4 shows an example of an individual dimming circuit (3m) (3b) consisting of a relaxation-strain circuit.
The circuit is equipped with a time constant circuit (CR) consisting of a resistor (Ro) and a value resistor (C4), and a variable dimming volume (VR,). Synchronous pulse (PC) by changing the time constant
K is designed to control the time from the falling point of the trigger pulse (1)T) to the generation point of the trigger pulse (1)T).

Now, in the example, the individual dimming circuit (3m) (3b)
By adjusting the volume (VR,) of the lighting load (
5m) (5b) dimming bell can be individually dimmed;
For adjusting the decimeter (C3), each individual dimmer circuit (
3m) (3b) of the commercial power supply voltage (VAc) of the synchronization pulse (Pc) input as a reference pulse! Lighting load (5m) by changing the phase shift (θ) with respect to the zero point
(5b) The light can be dimmed.

FIG. 6 shows another embodiment, in which blood pressure reduction (T,
) o° Secondary winding (tt) o I! Electromotive voltage (Vt), tube resistance (R+s) and variable capacitance sensor (CS)
Good partial pressure circuit M(VDI)K? Partial pressure L, cosiday/
” '(Cs) O Both ends III Pressure (Va) t!0
The synchronizing circuit (2b) is configured to generate a synchronizing pulse (PC) in synchronization with the zero point, and the dimming operation is the same as in the previous embodiment.

FIG. 7 to FIG. 1O each show other embodiments,
Commercial power supply voltage (VAc) t! By changing the pulse width of the power synchronization pulse (P2) that is generated in synchronization with the zero point, it is possible to equivalently shift the phase of the power synchronization pulse (Pz) to generate nine synchronization pulses (Pc). It's sixty years old. That is, individual dimming circuit (3m) (3b)
Since the generation point of the trigger pulse (PT) is set based on the falling point of the sync pulse (Pc), changing the pulse width of one sync pulse (Pc) means changing the falling point of the sync pulse (Pc). There is no need to change the power synchronization pulse (P
The embodiment of FIG.
16) and a voltage divider circuit ('VR4)
This is a synchronous circuit (2c) in which the pulse width of the synchronous pulse (Pc) is changed by providing a synchronous pulse (VD, ). In the embodiment shown in FIG. 8, the voltage dividing resistor (R6) in the conventional example is
) K replacement 9 synchronous circuit (2d), Fig. 9 Embodiment Fi
Two large windings of the step-down system (T,) @ (L,) K taps (T,) to (T4) are provided, and the taps (T,) to (T4) are switched using the switch (SW,) K. However, the operations of both of the above embodiments are almost the same as the embodiment of FIG. In the embodiment shown in FIG. 1O, a plurality of Zener diodes (ZDa) to (ZDc) with different Zener voltages are
%)K to change the pulse width of the synchronous pulse (Pc).

FIG. 11 shows still another embodiment, in which a variable resistor (
VL) and Koni J Dashisa (C6) are used to set up a voltage divider circuit (9 synchronous circuit (2f)), and adjust the volume (VR4) to change the pulse width of the synchronous pulse (Pc) from hK2. At the same time, the voltage (vAc) t! The phase shift (θ) of the synchronizing pulse (PC) with respect to the zero point is also changed. FIG. 12 and FIG. 13 show still another embodiment, in which the power supply synchronous circuit (2R) (28) (2T) and each phase (IR) (Is
) (IT) K-connected individual dimming circuits (3R
) (3 days) (3T) (however, only one pulse is shown in the figure) Synchronous pulse (PR) (Pa) (PT
-) to the power supply synchronization bus (PZR) (PZR) (PZ
Selection switch to select from T) (8Wl()(
S%VB) (SWT) ,! -! Rinal fii 1st season Do
It is equipped with a circuit (2g) and a power synchronization circuit (2R).
) (2S) (2T) Power synchronization pulse (P
ZR) (PZS) (PZT) are 600 degrees out of phase with each other as shown in Figure 14. This power synchronization pulse 2 (PzR) (PzB) (PzT) is selected by selecting the switch (
yR) (SWB) (SS'l'z) Select the individual dimmer circuit (3R) (38) (3T) by inputting the lighting load (SR) of each phase (IRXIS) (tT). ) (58) (5T) can be dimmed in three steps.

Figure 15 shows terminals (GA) ~ (G c), (HA) ~ (
Hc), (G,) ~ (G, ), (H6) ~ (R3). In the connection example of Figure (a), the lighting load (SR) (58) (5T ) are all one-stage dimming (the brightest full 5 lights), and in the connection example in the same figure (b), the lighting load (SR
) (BS) (5T) each has 3 steps of dimming (darkest),
2-stage dimming (medium brightness), 1-stage dimming, same figure (c
), the lighting loads (SR) (58) (5T) are 2-stage dimming, 1-stage dimming, and 1-stage dimming, respectively. J(!-
By the way, each phase (JR) (ISXIT) K each has multiple individual dimming circuits (3R) (3R)..., (38) (38
)..., (3T) (3T)... are connected, for example, R phase individual dimming circuit (2R) (2R)...
・If the same synchronization pulse (PR) is input to all K, the lighting load (aK) (SR) of the same phase (IR)...
will be dimmed by (-). In addition, the individual dimming circuit (2R) (2R) connected to the in-phase (IR)
...K different power synchronization pulses (PZR) (Pza)
If (PzT) is inputted individually, it is also possible to perform individual dimming. Furthermore, it goes without saying that the above-described embodiments may also be used in parallel.

The present invention is constructed as described above.
Since the dimming is performed by changing the phase of the synchronous path, there is an advantage that a dimming circuit capable of individually or collectively dimming a plurality of lighting loads can be implemented with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing a conventional dimming system, Fig. 2-) to (c) #i is a main circuit diagram of the same as above, and Figs. 3 and 4 are Abe circuits of a dimming system according to the present invention. FIG. 5(a) is an explanatory diagram of the same operation as above, and FIGS. 6 to 11 are explanatory diagrams of 'gIs circuit diagrams of other embodiments, respectively. +1) (IR) (Is) (IT) is commercial power supply, (2m
) ~ (2g) ii synchronous circuit, (3m) (3b) (3RX
3S) (3T) is an individual dimming circuit, (4) is a try 7”J
9. (5m) (5b) (SRX5S) (ST) is the lighting load. Agent Patent Attorney Ishi 1) Chief 7 Figure 1 Figure 2 (0) (b) Yan Figure 4 Figure 6 1-
j
@511 Fig. 10 2e No. 9 ■ 2f / 1----------1-J No. 1111 f

Claims (1)

[Claims] +1J II A synchronizing pulse is input to each individual dimming circuit provided corresponding to several lighting loads, and a trigger pulse with a preset phase delay is output to each dimming circuit. Finally, by using a dimming method in which the load control try hook is controlled by the trigger pulse, the commercial power supply voltage t! Multiple lighting loads can be dimmed at once by inputting a synchronizing pulse outputted from a synchronizing circuit whose phase can be freely shifted from a power supply synchronizing pulse synchronized to the zero point to each individual dimming circuit. A dimming method consisting of