JPS58114677A - Video recorder - Google Patents

Abstract

PURPOSE:To record the titles including the time and data of recording on a video screen of the TV broadcast, etc. and then reproducing the information on these titles along with the video signals in a reproduction mode, by recording the information stored in a memory together with the video signals. CONSTITUTION:The video signal with which the TV broadcast, etc. is recorded is fed to a line 1 and amplified through an amplifying circuit 2 to be applied to a mixer 4 and a synchronizing signal output circuit 13 via a line 3. The signals corresponding to the vertical and horizontal signals respectively are delivered from the circuit 13 and applied to a writing position generating circuit 16. The output of the circuit 16 is applied to a display timing generating circuit 38. These circuits are controlled by a control circuit 37 and in response to the operation of a control circuit 9, and the character information stored previously to an ROM5 is read out to the mixer 4 synchronously with the supplied video signal and mixed with the video signal to be processed through a video recording processing circuit 8. Thus the titles including the time and data of recording, etc. are recorded on the display screen of the video signal.

Description

[Detailed Description of the Invention] The present invention relates to a scissor image recording device, and more specifically, it is capable of displaying information such as characters in a video signal obtained from a television broadcast or the like. Regarding scissor image recording equipment.

Conventional video-image devices can record video signals such as TV broadcasts, but they also require input of information such as the date and time of recording and characters such as titles for recording. No consideration was given. If images such as the date and time of recording and the title could be obtained, it would be convenient when playing back video.

An object of the present invention is to provide a video recording device that can further add information such as characters to a video signal to add a comment.

FIG. 1 is a block diagram of an embodiment of the present invention. A video signal to be recorded, such as a television broadcast, is also input to line 1, amplified by amplifier circuit 2, and output to line 3. The video signal from line 3 is applied to mixer 4. A signal representing information such as characters from the read-only memory 5 is applied to the mixer 4 via the twin 6, as described in 6.1 below. Mixer 4 mixes the video signal from line 3 and the signal representing information such as characters from line 6 and outputs the mixed signal from line 7 to recording processing circuit 8 .

Recording processing circuit 8 receives the mixed signal from line 7 and records it on a recording medium. If no signal is derived from the read-only memory 5 to line 6, only the video signal via line 3 is recorded by the recording processing circuitry. The derivation of the signal from the read-only memory 5 is performed by operation -l
This is done according to the IG operation. The mixer 4 is the tin 3
11 minutes of the video signal from Twin 6 is removed, and a signal representing information such as characters from Twin 6 is inserted into the removed portion.

FIG. 182 is a front view showing the operation panel of the operation circuit 9. FIG. On the operation panel, there are a plurality of character keys 10 for inputting characters, etc., a star key 11 that is operated to start recording characters, etc. input by the character keys 1G, and a changeover switch 12. is placed.

When the selector switch 12 is in the switching mode corresponding to the position where "1 sequentially" is displayed, among the plurality of characters entered manually using the character key 10, the first character is displayed, and then, The first character and the second character are displayed, and then the first character, the second character, and the third character are displayed, and so on, and the characters are sequentially displayed. Further, when the changeover switch 12 is set to the "simultaneous" position, all of the plurality of characters input using the character keys 10 can be simultaneously recorded and displayed and reproduced.

The video signal derived from the amplifier circuit 2 to the line 3 is given to the synchronization signal output circuit 13. Synchronous signal output circuit 13
derives a horizontal synchronization signal on line 14 and a vertical synchronization signal on line 15.

These horizontal synchronization signals and vertical synchronization signals are applied to the write position signal generation circuit 16.

FIG. 3 is a boot diagram showing a specific configuration of the synchronization signal output circuit 13. The video signal from the amplifier circuit 2 via the line 3 includes a video signal component 17 and a horizontal synchronizing signal 18, as shown in FIG. 4(1). Synchronous separation circuit 19
receives such a video signal from the fin 3, performs level discrimination, and derives the signal shown in FIG. 4(2) on the line 20. The signal led out to the line 20 is amplified by the horizontal synchronizing signal amplification circuit 21, and the signal led out to the line 14 is
The signal shown in Figure (3) is derived.

The signal derived on line 20 is also shown again in FIG. 5 fl) with a reduced time axis compared to FIG. 4 10.

Reference mark W1 indicates the position horizontal scanning period.

Integrating circuit 22 receives the signal from line 20 and derives the signal shown in FIG. 5 on line=4.

The waveform shaping circuit 25 levels-discriminates the signal derived from the tin 24, shapes the waveform into a rectangular wave as shown in FIG.

FIG. 6 is a splitter diagram showing a specific configuration of the writing position signal generation circuit 16. Figure 4 from line 14 (3
(The horizontal synchronization signal shown in FIG. When the rising waveform of the horizontal synchronization signal from 14 is obtained, a predetermined time W2 from 1111tl
Figure 2 (2) remains at low level until
) is introduced on line 29 with a waveform shown in FIG. This time W2 is determined by a capacitor 30 and a resistor 31 connected to the horizontal position register 28.

Vertical position register 32 is the number $WJf from line 15.
A vertical synchronizing signal indicated by ll is received, and a signal having a waveform at a low level is derived to the twin 33 until a predetermined time W3 has elapsed from the rising edge of the vertical synchronizing signal 11t2. This time W3 is the vertical position register 3.
Signals from the pins 29 and 33 defined by the pin t34 and the resistors 3 and 5 connected to the timing control circuit 36 are applied to the timing control circuit 36.

The operation of timing control circuit 36 will be explained with reference to FIG. The waveform of the signal applied from line 29 to timing control circuit 36 is shown in FIG.
The waveform of the signal applied from line 33 to timing control circuit 36 is shown in FIG. 9(2). Timing control circuit 36 also receives a signal from control circuit 37 via line 28 indicating the period during which characters or the like are to be displayed. The waveform of the signal from line 27 is shown in FIG. 9(3), and is at a high level only during the period when characters are to be displayed. When the timing control circuit 36 is receiving the signal representing the display period from the line 27, the timing control circuit 36 determines that l1kI! J receives the signal obtained from the horizontal position register 28 via the twin 29, and derives from the line 26 an entry position signal which becomes high level at 1111t3 when the signal from the line 29 rises. This writing position signal simultaneously becomes low level at time [4] when the signal representing the display period falls and becomes low level.

The write position signal derived from the timing control circuit on line 26 is applied to a display timing signal generation circuit 38.

A clock signal is applied to the display timing signal generation circuit 38 from the control circuit 37 via a line 39. The horizontal position of characters to be displayed is determined at a position where time W2 has elapsed since the rise of the horizontal synchronization signal. The vertical position of characters to be displayed is determined at a position where a time W3 has elapsed from the rise of the vertical synchronization signal. The display timing signal generation circuit 38 uses a clock signal to time the period during which the entry position signal is at a high level.

Display timing signal generation - The display timing identification signal derived from path 38 on line 40 is applied to read-only memory 5, thereby determining the time at which character data from only memory 5 is derived on line 6. is determined. The read-only memory 5 stores data representing characters such as letters to be displayed as described above. The control circuit 37 responsive to signals from the operating circuit 9 sequentially addresses the storage areas of the read-only memory 5 in which character data representing characters to be displayed are stored by character selection signals via a line 41. . In this way, from read-only memory 5,
When the display timing signal is being generated, the control circuit 3
The character data stored in the storage area designated by the signal from 7 is derived.

The 10th WJ is a diagram for explaining the operation when plural characters, etc. are sequentially displayed on the l1iiWI.

The number 1xm shown in FIG. 10 represents the display time of characters, etc. to be displayed on the screen. Control-path 137
derives a character selection signal from line 41 at the time shown in FIG. do. Next, in order to display a second character at a position horizontally adjacent to the first character, the control circuit 3
7 derives a character selection signal at the time shown in FIG. 10 (2). In order to display the third character next to the second character, the control circuit 37 derives a character selection signal at the time shown in FIG. 10(3). Similarly, to represent the 14th character and the 5th character, Figure 10 (anatomy) and Figure 10 (6)
), the sentence and character appropriate translation signals are respectively derived. Thereafter, in order to similarly display the In character next to the (n-1)th character, a character selection signal is derived at the time shown in FIG. 1θ (6).

When changeover switch 12 is switched to the "simultaneous" position in FIG. 2, control circuit 37 derives a character selection signal from line 41 to read-only memory 5 at the time shown in FIG. 911. This causes a number of characters to be displayed simultaneously on the screen.

As described above, according to the present invention, since the information stored in the memory is mixed with the image signal and recorded,
During playback, the information can be viewed together with the signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a front view showing the operation panel of the operation circuit 9, FIG. 3 is a block diagram showing the specific configuration of the synchronization signal output circuit 13, and FIG. The figure is a waveform diagram for explaining the operation of the horizontal synchronous amplifier circuit 21.
FIG. 5 is a waveform diagram for explaining the operations of the integrating circuit 22 and the waveform shaping circuit 25, FIG. 6 is a block diagram showing the specific configuration of the writing position signal generation circuit 16, and FIG. 7 is a horizontal position register 28. 8 is a waveform diagram to explain the operation of the vertical position register 32, FIG. 9 is a waveform diagram to explain the operation of the timing control 11g1 path 36, and FIG. 11 is a diagram for explaining the operation for sequentially recording characters, and FIG. 11 is a diagram for explaining the operation for displaying a plurality of characters simultaneously. 2... Amplification path, 4... Mixer, 5... Read-only memory, 8... Recording processing circuit, A... Operation circuit, 13... Synchronous signal output circuit, 1G...・Input position signal generation circuit, 37...Control circuit, 38...Display timing signal generation - Patent attorney Kei Nishi Part 2, Figure 4, Figure 6, Figure 7, Figure 8, Figure 9 Figure 11

Claims (1)

[Claims] A video recording device for recording a video signal, wherein information stored in a memory is mixed with the video signal and recorded.