JPS58114241A - Interface converting device - Google Patents

Abstract

PURPOSE:To use a processing mechanism as one device of independent type, by mutually converting a panel interface with a system console interface by an interface converting circuit placed on the outside of the processing mechanism. CONSTITUTION:An interface converting device 11 is constituted of a panel interface adaptor part 12 connected to an operating panel 10, a system console interface adaptor part 14 connected to a processing mechanism 3, and a control part 13 for controlling both these parts. Control by the operating panel 10 is absorbed by the panel interface adaptor part 12, its interface is converted by the control part 13, and it is transmitted to the system console interface adaptor part 14. On the other hand, a state of a device is sucked up by the system console interface part 14 by scanning of the control part 13, its interface is converted, and it is transmitted to the panel interface adaptor part 14.

Description

DETAILED DESCRIPTION OF THE INVENTION U) Technical Field of the Invention The present invention relates to a system in which a processing mechanism within a device that is controlled by a system console can also be controlled by an operation panel in place of the system console. The present invention relates to an interface conversion device that converts a console interface to an operation panel interface.

Main) Prior art and problems No. 11i3 shows a processing II device 2 equipped with a system console l, and each %llllll in the processing device 2
113 are all controlled by the system console 1.

A system console interface control unit 4 is provided for each processing mechanism, and physically, as shown in FIG. 2, there are processing layer mechanism addresses a, a' and a control address b.

b', control data c, c' exist for each input and output, and a timing straw for control 19g4jd
It is also equipped with When the keyboard installed on the system console A/1 is pressed, the system console 1 will control each area 111111Kti 11 Mechanism address 1
．． Control address b, control data C9 and timing stop tz-d are sent. The processing mechanism 3 compares the process 1jlII & structure address sent by the V stem console interface control unit 4 and sent from the nine-way mechanism address section 6 with the nine-way 1llllII structure address to which IIIJ is added, and If it cannot be removed, it is transmitted as is to the next processing mechanism. The address matches 9 places j1i! The mechanism takes in the control address and control data b, and controls the processing mechanism 3 in synchronization with the timing strobe signal. To display the status on the console 1 of the coffee shop I18, turn off the timing stroke from the system console 1 and enter the address Hatake 1 of the Kaijo Organization.

When the control address b without timing strobe d and the control data C are received, the tore-9 tin layer mechanism displays the processing mail structure required by the control address b' in the control data 1a' on the output side. It carries the data and sends it to the V-stem console l along with the processing mechanism address al l and the control address bl. System console 1 receives the data and displays the status to console A/1. The status is displayed by the system console 1 at regular intervals.
Ill structure 3 and! @Coffee This is done by scanning the state of the structure in the mechanism 3, and specifically, the processing mechanism address a and the control address b are changed nine times from time to time to receive the data CI sent out from the processing mechanism. 9 It will be done.

On the other hand, FIG. 3 shows a panel interface section of a single-stage processing device which is controlled by an operating spring y. When the operation spring ~ is pressed down, 9
At the same time that the PUaHm signal is turned on, coordinate addresses X and Y indicating which position on the panel was pressed are transmitted to the device side. The panel interface control section of the device is PU
The rising edge 9 of 8H is detected and the device is controlled based on the X and Y values. In addition, the display on the operation panel is performed in synchronization with αX sent from the device side, and x, y - (o, o) to (a, m)
t is transmitted bit serially by the DTIN signal.

Synchronization of the x and y addresses is performed by returning j) In other words, BYNC Hakugo is turned on, and after his death, PDC Kakunta, which controls the address of KK Robi, uses CLK.
At the same time, the left register on the panel side operates in synchronization with CLK, and the display data selected by ps by the MPX on the device side is sequentially stored in the left register. When the 8-bit transmission is completed, the S bit data is turned on and the S bit data is held. At the same time, the DC counter is increased by 1 and the U of the column indicated by DC is
Point ffi on the hump. When the next 8 bits () are received, the display data is held in a similar manner and the -DC counter is counted up, so that the tmm lamp indicated by DC is emitted. When all data display is completed in this manner, the PDC returns to zero, the pDC counter returns to zero by the IIYNc signal, and the operation as in 1 continues after that.

The reason for the above explanation is that there is a difference between the control using the V;L stem control and the control using the spring A/II structure. Since the interface on the I1 mechanism or device side is the physical KA, in order to place the processing mechanism with the system console interface under control of the panel as an independent device, replace the system console 7 rain interface section with the panel interface section. The need arises, forcing major hardware changes.

(c) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional technology, the present invention provides a new interface conversion circuit that is installed outside the physical mechanism equipped with the system console interface section, and a parent circuit that converts the panel interface and the system console interface. Convert each other into one spring processing mechanism! This allows it to operate under control and can be used as a stand-alone device.

B.) Structure of the Invention; and this object, in accordance with the present invention, in any processing mechanism within a system that is controlled by a system console, to the physical V-stem console interface portion of the upper rudder processing mechanism.

Logically connectable and system console interface
Equipped with an interface conversion device that converts 7ACE into an operation panel interface, the above iu* structure,
To provide an interface conversion device characterized in that, by connecting the above-mentioned interface conversion device and an operation spring, one processing mechanism in the device is controlled as one independent processing device that can be controlled by an operation panel. achieved by.

- Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 shows an outline of the interface conversion circuit of the present invention. The interface conversion device 11 includes a panel interface adapter portion 12° connected to the operation spring A/10, and a system console interface 7 air adapter portion 174 connected to the side 1 of the processing machine. and a control unit 13 that controls both. That is, the control by the operation panel 10 is absorbed by the panel interface adapter section 12, and the interface conversion field is transmitted to the system console interface adapter section 14 by the control section 13. - The state of the blade device is taken up by the system console interface section 14 through scanning by the control section 13, converted into an interface, and transmitted to the panel interface adapter section 14.

FIG. 1 is a block diagram showing an embodiment of an interface conversion device according to the present invention. FIG. S shows a case in which a microprocessor (hereinafter referred to as μP) 31 is used as the control section, and FIG. 6 shows a state diagram of level value changes of the microprocessor μP31.

The operations in Figures 5 and 6 will be explained in detail below.
P31 shall run at 4 levels of LO-Ll,
LO is an interrupt request that is raised only when an abnormal state of the interface conversion device is detected, and Ll is an interrupt for scissors placement control that often occurs due to external operation of the operation panel. It is assumed that L2 is generated due to a status display request to the operation panel, and Ll is at a normal driving level. μP31 is L
In order to monitor the status of the running device, the system console interface, the processing mechanism address (hereinafter referred to as 0DVAD) in the ageta unit 14, and the control address (O
DPAD)! 4. Sequentially change the control data (ODT2M) and ADOUT in the strobe off state.

Send to D'rOUT. The response from the device is 6 ADIN, DTINt' IDVAD, IDPAD!
? ,EDT! When the SK data is received, it is prepared in the random access memory (MIM) 22 under the JIP 31, converted to data for displaying the status on the panel via the data exchange table 23, and then sequentially stored in the table for status display. (However, in this case, 0DVAD should always be a constant value, that is, it should always match the DVAD of the processing section.) In other words, it is in charge of constantly scanning the device status and refreshing the soft line display table.On the other hand, the panel Power on the display data in the Inter 7 Ace adapter section 12!
DDC) 28 is a 3-bit counter, which counts from θ to 7.
As soon as data is stored in the bit display data register (DDK) 27, counting up is started, and each time the count is up, a CLK signal is transmitted to the spring side. The count of DDC2J1 is determined by its 11 selection circuit (
The display data transmitted to the MPX) 2g and stored in the DDR 27 will be sent to the panel in bit serial form as DTIN. DDC! When 8 is counted up to 71 and returns to zero, the data address counter (I) AC) 29
is counted up by +1.

In the initial state aK, the DD (J.
C (see IM in Figure 3) was also returned to zero, but DDC118
When detecting that becomes O, the 8-doware displays an interrupt request (FFIO).
Generates 2 interrupt requests. #P31 is DPC2 in Ll
When it reads 1 and confirms that it is 0, the display data for DAC-0 (that is, for DC-0 indicating the spring ρ display address) is set in DR27. When data is set in the DDR 27, as explained above, the DDC 211 starts counting up and transmits it as serial data to the spring/I/III. At the same time as DDC211 becomes O again, DAC1
9 is changed to 11, and an L2 request occurs again. μP31 is L
DAC211 is read again in l, but in this case it is 1, so the display data for DAC-1- is read in DDII.
! 7 is stored, and the same operation follows when DAC21!1 is stored at 7~
Until it becomes i! It continues. That is, aP31 is Ll
When DDiL! occurs, the data at the display address indicated by DAC2. The state of the springs is displayed without changing to 7F. D
When AC29 becomes full, spring A/
DDC at the same time as telling @! II, the DAC 29' is returned to zero and the same operation is repeated.

The status display on the panel has been explained above, but next, the operation when the operation panel is pressed will be explained. When the operation panel is pressed, the PUSH number and the X and Y addresses indicating the pressed location are sent from the spring μ side. The panel interface adapter unit 12 detects the rising edge of the PU8 H signal, and if PACTV indicating the panel function enable state is on, turns on the control input tap (FF4) and generates an L1 request. #nti1 company LI KiteX,
Read the Y address, refer to the data conversion table, and
Convert the Y address to a control address and control data for the system console interface, and turn on the strobe signal to 0DPAD.

The data is sent to the system console interface unit 14 using the ODT and DTOU signals.

Finally, an overview of the firmware control that operates within the voice P will be explained.

As shown in the first 1iIK, during normal driving level L3 driving, the device is in state II! I monitor and update the display data tape ~, but when Ll occurs, the data indicated by the DAC 211 in the display data table created in L3 becomes DR2? Heard and went back to L3 for 4 doro. Ll is DD
This occurs every time C2g returns to zero (for a certain period of time and K). On the other hand, when Ll is generated by pressing the operation panel, x,
Read Y and data conversion team 7 # fc Yotte f
- Ill exchange L DVDAD, DPAD, ODT hes draw 1 on state - is output, and the data tape for display is updated again to L3.

(F) Effects of the Invention As explained in detail, by installing the interface conversion device of the present invention, the specifications of any operation panel can be changed to the specifications of any system console interface control unit by simply changing the data conversion tape 14/. It has wide versatility in that it can be modified.

ti All of the above explanations were for converting an operation panel interface to a system console interface, that is, for using the processing mechanism within the device as an independent processing device, but conversely, converting a system console interface to a panel interface to convert,
That is, it is also possible to use a stand-alone device as an integrated processing mechanism within a system.

[Brief explanation of the drawing]

1wA is a block diagram of a processing device equipped with a V-stem console to which the present application is applied, FIG. 2 is a specific configuration diagram of the processing device shown in FIG. 1, and FIG. FIG. 4 is a block diagram of the interface conversion device according to the present invention. FIG. 5 is a configuration diagram showing an embodiment of the interface conversion device according to the present invention. 6wJ
1 is a diagram showing a level value change of the micropressor used in FIG. In the drawings, 1 is a system console, 2 is a device, 3-1 to 1 are a processing mechanism, 4 is a system console interface control section, S is a processing section, and 7 is a mechanism address section. is an address comparator, 8 is a decoder, 1 is a multiplexer, 10 is an operation panel, 1
1 is an interface conversion device. 12d spring to Inter-7 ace adapter part, 13ufl
J Go 116. 1au system console interface adapter part, 22 is a rising 9 detection circuit, xsFi AND element, 24 is a flip-flop, 2h uX, Y address reception register, 26 is a multi-direction, 27Fi
Display Data Resis I, 2 Hatake is Display Data Calan! , 2 is a data address counter, 130 is a 7-lip flop, 31 is a microprocessor, 32 is a memory, 3s is a data conversion table, 34 is a processing mechanism address for output and a control address register for output, 35
36 is an output control data register, 36 is a strobe generation register, 37 is an input processing mechanism address and output control address register, 38 is an input control data register, and 39 is a processing section.

Claims (1)

Claims: In any processing mechanism within a device that is controlled by a system console, the system console interface is physically connected to the processing mechanism. Logical km can be continued 69. It is equipped with an interface conversion device that converts a system console interface into an operation panel interface, and by connecting the interface conversion device and the operation panel to the processing mechanism, it is possible to control the inside of the device! An interface conversion device characterized in that the processing mechanism is controlled as an independent layer l tin layer device controllable by a IIIk actuating spring.