JPS58113976A - Character pattern generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character pattern generation device used in dot printers, character display devices, etc., and in particular to the use of a character pattern memory in a character pattern generation device that outputs characters corresponding to an input code in a dot pattern. The present invention relates to a character pattern generating device that improves efficiency and can easily handle different code systems such as ASCII and tel@t@x.

Dot printers, inkjet printers, or display devices using CRTs or liquid crystals process each character or symbol as a code, and use a character pattern generator to process the character code when printing or displaying it on layout paper or a display screen. I am trying to convert it to a dot pattern.

FIG. 1 is a functional block diagram showing an example of the configuration of a dot printer equipped with a conventional character pattern generating device. In the drawings, l is a host machine, ko is a character pattern generator, ko/ is its data latch circuit, 2λ is a control section, ko 3 is a character pattern memory, 3 is a printer,
Also, Data is the input code, Dot Data is the dot pattern data, 8TROBE-/ and 5TROBK-
ko indicates a strobe signal.

In character code systems such as ASCII and tel@tex, t
The code of each character is defined by the combination of bits.

From the host machine, this S-bit character code is applied as an input code Data to the data latch circuit of the character pattern generator and latched therein, and a strobe signal 8TROBE-/ is applied to the control unit.

A character pattern memory 3 made up of a ROM or the like stores dot pattern data corresponding to a character code at each address.

Figure 2 shows the English letter rA that can be written in character pattern memory 3.
This is an example of the dot pattern data of J. In the drawings, [)/-D, t indicate each bit string, R/~R7 indicate each bit line, the hatched area indicates logic ``''/', and the white area indicates logic 1.
0' data is shown.

FIG. 2 shows a case where one character is composed of horizontal x vertical = 3 x bits.

Data latch circuit! The character code latched in / is output to the character pattern memory = 3 as an upper address signal, and when the character code is the English letter "A", the address where the dot pattern data in Figure 1 is stored is addressed. Ru.

Furthermore, the control unit 22 outputs a strobe signal 8T.
With ROBF knee/ as a trigger, in this case ζ corresponds to the bit string D/~D-j! During the cycle, a chip select signal CS is generated to select the character pattern memory code 3.
Activate.

Then, according to the lower address signal, 7 bits of each line R/-R7 of the bit string in the V direction are set as 7 bits in the V direction every cycle, and 7 parallel dots of dot data are generated.
is output to the printer 3.

This kind of behavior! The cycle is repeated and the bit string D
When each of the seven dot data of /-DJ is sequentially output in the H direction, printing of the dot pattern "A" corresponding to FIG. 2 is completed.

By the way, in each of these code systems, combinations of 2S and B are possible due to the t-bit structure, but the types of characters used in printers are around 96 in the case of European characters. and,
The character code is its type, such as uppercase, lowercase,
They are assigned in order for each type of number, etc.

FIG. 3 is a conceptual diagram of a storage image showing the storage state of pattern data in the one-character pattern memory card 3. FIG. In the drawing, the shaded area indicates the storage area for pattern data, and the white area indicates the unused area. When accessing the character pattern memory with a 0g bit character code, if the character code is used as an address signal, the address of can be identified, but the pattern data is around 96, so
Addresses of 60% or more become white unused areas.

Therefore, the usage efficiency of the character pattern memory code 3 is not very good.

Moreover, if the code system changes, different character patterns will be defined even for the same character code, so it is necessary to prepare one character pattern memory 23 for seven code systems.

Therefore, in the character pattern generation device of the present invention, these disadvantages in the conventional character pattern memory are solved.
By configuring a character pattern memory with the minimum storage capacity that can store pattern data corresponding to the culms of characters, the usage efficiency of the pattern memory is improved.

The purpose is to be able to deal with subsystems even for different code systems.

To this end, the character pattern generator of the present invention includes a character pattern memory capable of storing necessary types of character pattern data, and addresses of each pattern data on the character pattern memory corresponding to the type of code system. The present invention includes a plurality of address memories made up of ROMs and the like, and selection means for selecting one of these address memories according to the code system to be used.

FIG. q is a functional block diagram showing an embodiment of a dot printer equipped with the character pattern generating device of the present invention.

The symbols in the drawings are the same as in FIG. 1, and 9. Further, 2' is a character pattern generator, 2 is a first address memory that stores the upper address of the character pattern memory 23 for the first code, and 5 is a character pattern memory 3 for the first hood. The first address memory stores the upper address of C.
ode is a code designation signal, CLK is a clock signal, S
A is the output signal of the data latch circuit λl, SB is the selection signal of the first address memory 2da and the first address memory 23 output from the control section 22, and SC is the selection signal of the first address memory 2da or the first address memory 23. Address memo IJ 2
SD indicates a lower address signal output from the control section 22, and Sg indicates a chip select signal output from the control section 22.

FIG. 7 shows a printer equipped with a character pattern generating device which can use two code systems, and has a first address memory 24! corresponding to each code system. and a first address memory 23 are provided.

The two first address memories are address conversion ROMs that convert the input character code of the first code system into the code of each address of the character pattern memory 3 in which the pattern data is stored. First address memory 2S
is an address conversion ROM that converts character codes of the first code system.

Then, in order to select the first address memory Jf and the first address memory S, the host machine/
A code designation signal Cod is given to the control section 2=. In the case of one code system, the code designation signal Co
d. may be a / bit, and is predetermined so that when the logic is 171, it indicates the first code system, and when the logic is 1010, it indicates the first code system.

The other configurations are basically the same as those shown in FIG. 1 above.

FIG. S is a timing chart for explaining the operation of the printer of FIG. 7. The symbols attached to each signal waveform correspond to the symbol positions in FIG.

From the host machine /, / bit code designation signal Cod・
and strobe signal 5TROBE-/ are applied to the control section 2- of the character pattern generator λ', and the t-bit character code Data is applied to the data latch circuit 21.
Here, the first code system is ASCII, the second code system is Telstex, and when the code designation signal Cod is logic q''11, the first code system of ASCII When the code system is specified diagonal logic 10#, the first telet
It is assumed that the code system of ex is specified. In addition, the character pattern memory 3 contains 1 characters as shown in Figure 2 above.
It is assumed that pattern data in which characters are composed of 3×7 (bits) is stored.

When using the first code system, the code designation signal C
ode is given at 171, and the control unit 2 selects the first address memory reader by using the address memory selection signal SB as Me.

In this case, the character code D given from the host machine
ATA is an ASCII code system, and the control section here causes the data latch circuit to latch the 5-character code Data at the output corresponding to the input strobe signal 8TROBE-/.

Therefore, the first address memory 29 is
The character code according to the code system of I is the data latch circuit /
is outputted as an output signal SA from
It is given to the character pattern memory 3 as C.

The control section 22 also receives a strobe signal 8TRO.
Using BE-/ as a trigger, the lower address signal SD is outputted to the character pattern memory 23 for three cycles, and at the same time, the chip select signal Sg is outputted during that period to activate the character pattern memory 3.

As a result of this operation, the 7 bits for / column of the character pattern are sequentially output from the character pattern memory 23 three times to the printer 3 as dot data, and one
A dot pattern of characters is printed.

When the second code system is teletsx, the code designation signal Cod@ becomes 1θ', and the selection signal SB output from the control section here also becomes "01".In this case, the output inverted by the imper tacho B but"/'
Therefore, the second address memory S is selected.

Other operations are the same as when the first code system is used.

In the above embodiments, the dot printer was mainly explained.

However, the character pattern generating device of the present invention is not limited to such dot printers, but can be similarly applied to inkjet printers and other printers that print in dot patterns. Also, depending on the type of printer, some use a buffer for processing input character codes one by one, or a buffer for outputting dot patterns, but it is important to apply this to all of these printers. is possible.

Furthermore, there is a display device using a dot pattern.

Can be applied.

The following FIG. 6 is a conceptual system diagram showing the process from character code to output of pattern data in the character pattern generating device of the present invention. The symbol in the drawing is
This is similar to FIGS. 1 and 7.

As shown in FIG. 6, the character pattern generator of the present invention is equipped with a plurality of address memorizers and 3s for performing address conversion, depending on the type of code system used, and These address memorizers and 3 are selected in accordance with the input code system. Each address memory data or code S is provided with a character pattern memory 3 corresponding to each character code in advance so that each address of the character pattern memory 23 storing pattern data according to the code system to be used can be addressed.
The upper address of is stored.

Therefore, according to the character pattern generation device of the present invention, it is possible to sequentially store the required character pattern data to each address of the character pattern memory code 3, regardless of the code system used. Since the storage capacity can be reduced by the amount of used area, the usage efficiency is significantly improved. Moreover, many excellent effects can be obtained, such as being able to cope with various code systems by simply adding an address memory consisting of an address conversion ROM or the like.

[Brief explanation of drawings]

Fig. 1 is a functional block diagram showing an example of the configuration of a dot printer equipped with a conventional character pattern generation device, Fig. 2 is an example of dot pattern data for the English letter rAJ in the character pattern memory, and Fig. 3 is a functional block diagram showing an example of the configuration of a dot printer equipped with a conventional character pattern generating device. FIG. 7 is a functional block diagram showing an embodiment of a dot printer equipped with the character pattern generating device of the present invention. FIG. 5 is a conceptual diagram of a storage image showing the storage state of pattern data. FIG. FIG. 1 is a conceptual system diagram showing a timing chart for explaining the process from a character code to outputting pattern data in the character pattern generating device of the present invention. In the drawings, ko' is a character pattern generator, -/ is a data latch circuit, 22 is a control section, 23 is a character pattern memory, λda is a first address memory, and 2S is a first address memory. Patent applicant Rico Co., Ltd. −

Claims (1)

[Claims] A character pattern memory that stores pattern data of the types of characters necessary for each address, and a character pattern memory that is provided corresponding to each code system and stores pattern data of each character code. A character pattern generating device comprising: an address memory for converting into a memory address; and a selection means for selecting the address memory according to an input code system.