JPS5811352U - Wireless communication device receiving circuit - Google Patents

Wireless communication device receiving circuit

Info

Publication number
JPS5811352U
JPS5811352U JP1981105912U JP10591281U JPS5811352U JP S5811352 U JPS5811352 U JP S5811352U JP 1981105912 U JP1981105912 U JP 1981105912U JP 10591281 U JP10591281 U JP 10591281U JP S5811352 U JPS5811352 U JP S5811352U
Authority
JP
Japan
Prior art keywords
variable capacitance
circuit
capacitance diode
wireless communication
communication device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981105912U
Other languages
Japanese (ja)
Inventor
昌行 松尾
安彦 利夫
邦治 竪月
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP1981105912U priority Critical patent/JPS5811352U/en
Publication of JPS5811352U publication Critical patent/JPS5811352U/en
Pending legal-status Critical Current

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  • Transceivers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はPLLシンセサイザ回路の基本例の回路ブロッ
ク図、第2図、第3図a、  bは同上の回路動作特性
図、第4図は本考案の一実施例の回路ブロック図、第5
図は同上のPLLシンセサイザ回路のブロック図、第6
図は同上の要部の回路図であり、4は電圧制御発振器、
5a、5bは可変容量ダイオード、15はPLLシンセ
サイザ回路、1Bは受信検出回路、19はプルインレン
ジ切換回路である。 第5図      、6 〉し′/2 N@刺1 −− 第6図 1    18−
FIG. 1 is a circuit block diagram of a basic example of a PLL synthesizer circuit, FIGS. 2 and 3 a and b are circuit operation characteristic diagrams of the same as above, FIG.
The figure is a block diagram of the same PLL synthesizer circuit, No. 6.
The figure is a circuit diagram of the main parts of the same as above, 4 is a voltage controlled oscillator,
5a and 5b are variable capacitance diodes, 15 is a PLL synthesizer circuit, 1B is a reception detection circuit, and 19 is a pull-in range switching circuit. Figure 5, 6 〉shi'/2 N@Sashi 1 -- Figure 6 1 18-

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] PLLシンセサイザ回路を局部発振回路として用い、か
つ受信待機中にはPLLシンセサイザ回路を間欠的に動
作させて用い、通話時には連続的に用いる無線通信機の
スーパヘテロゲイン方式の受信回路にお゛いて、PLL
シンセサイザ回路の電圧制御発振器に設けた発振可能領
域設定用の可変容量ダイオードとしてプルインレンジを
広げる電圧特性を有する第1の可変容量ダイオードと、
プルインレンジを狭くする電圧特性を有する第2の可変
容量ダイオードとの2種を用いるとともに上記受信待機
中には第1の可変容量ダイオードを、通話時には第2の
可変容量ダイオードを切換えて電圧制御発振器に接続す
る受信検出切換手段を具備して成る無線通信機の受信回
路。
In a super-hetero gain receiving circuit of a wireless communication device that uses a PLL synthesizer circuit as a local oscillation circuit, operates the PLL synthesizer circuit intermittently during reception standby, and continuously uses it during a call, PLL
a first variable capacitance diode having voltage characteristics that widens the pull-in range as a variable capacitance diode for setting an oscillation possible region provided in a voltage controlled oscillator of a synthesizer circuit;
A voltage controlled oscillator is constructed by using two types of variable capacitance diodes, a second variable capacitance diode having voltage characteristics that narrow the pull-in range, and switching the first variable capacitance diode during reception standby and the second variable capacitance diode during a call. A receiving circuit for a wireless communication device comprising a receiving detection switching means connected to a receiving circuit.
JP1981105912U 1981-07-15 1981-07-15 Wireless communication device receiving circuit Pending JPS5811352U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981105912U JPS5811352U (en) 1981-07-15 1981-07-15 Wireless communication device receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981105912U JPS5811352U (en) 1981-07-15 1981-07-15 Wireless communication device receiving circuit

Publications (1)

Publication Number Publication Date
JPS5811352U true JPS5811352U (en) 1983-01-25

Family

ID=29900428

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981105912U Pending JPS5811352U (en) 1981-07-15 1981-07-15 Wireless communication device receiving circuit

Country Status (1)

Country Link
JP (1) JPS5811352U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106492A (en) * 1983-11-16 1985-06-11 松下電器産業株式会社 Electric washer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106492A (en) * 1983-11-16 1985-06-11 松下電器産業株式会社 Electric washer

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