JPS58111452A - Code conversion circuit - Google Patents

Abstract

PURPOSE:To reduce interference between codes and to extract surely timing, by inserting a complementary code just before or seveal bits before a pulse to an m-th bit of a binary signal series and suppressing the consecution of the same codes. CONSTITUTION:Data from a terminal 1 and a clock signal CLK from a terminal 2 are inputted to a shift register 4 having FFs of (K+1) sets of cascade connection. The CLK of the pulse interval T0 is frequency-divided at a 1/m frequency division circuit 5, and a pulse C2 of the pulse width T0 is generated at each mT0. The Q' output of the FFs at the final stage and the prestage of the register 4 is inputted to an exclusive logical sum section 8 via a complementary code pulse position indicating section 6 and a complementary code control pulse generating section 7, and an exclusive logical sum signal A is outputted to a complementary code inserting section 9 at each mT0 according to the signal C2. The Q, Q' outputs of the register 4 are delayed for a prescribed time at a delay circut 10, inputted to the inserting section 9, where a complementary code to be inserted to K bits before the pulse is outputted to the m-th bit of an input data together with signals A, C2 according to the logic of (Q-A-C2)+(QAC2)+ (-Q-AC2).

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a code conversion circuit used in a high-speed binary digital transmission system.

(Background technology) Conventionally, in high-speed binary digital transmission systems, the method shown in Fig. 1 (
As shown in A), a code conversion device consisting only of a scrambler is often used. When using this device,
By converging the mark rate of the digital signal sequence to a uniform value and randomizing it, securing constant transmission characteristics, suppressing jitter, etc. are performed stochastically. However, depending on the signal pattern, long sequences of the same code may occur, which has disadvantages such as increased code amount interference and inability to extract timing, resulting in deterioration in transmission quality.

In addition, as shown in Fig. 1 (B), 2
A device may be used to transcode m bits of a value into n (generally n2m+1) pits. In this case, it is possible to determine the number of consecutive identical codes in the worst case, but the rate of increase in the transmission path (rate of increase in transmission speed) is generally too large, and the configuration of the code conversion circuit becomes extremely complex, making it unsuitable for high-speed digital transmission systems. Not suitable. FIG. 1(C) shows a block diagram of the code conversion circuit when m=3. This circuit requires approximately 120 gates and m flip-flops.

(Problem to be solved by the invention) The present invention aims to improve the reliability of a digital transmission system by improving the above-mentioned drawbacks of the conventional technology and by eliminating code amount interference and reliably extracting timing. The complementary code immediately before or several bits before the pulse is inserted into the m-th bit (m is a natural number) of the pulse to suppress the same code consecutively.Its features include an input terminal that accepts input data, and a complementary code that is several bits before the pulse. A shift register having +1 (k is a natural number) cascaded flip-flops connected to the pulse interval T. The clock pulse of is divided into planes to obtain the pulse width T for each mTo. A frequency divider that generates 4tj pulses (m is a natural number of 2 or more), and the exclusive OR A of the final stage output of the shift register and its k (6m - 1 stage previous output for 1≦) is divided into Exclusive OR means for each mTo according to the output C2 of the frequency converter, a delay circuit that delays the final stage output of the shift register by the calculation time necessary for the exclusive OR process and provides the output Q, and QAC2+QA.
The code conversion circuit includes a complementary code inserting section which inserts a complementary code before the pit into the mth bit of input data according to the logic of C2+QAC2, and an output terminal connected to the output of the complementary code inserting section.

(Structure and operation of the invention) FIG. 2 shows an embodiment of the circuit of the present invention, in which 1 is a signal input terminal, 2 is a clock input terminal, and 3 is an output terminal for a code-converted signal. Further, 4 is a 2-pit shift register, 5 is an l/m frequency dividing circuit, 6 is a complementary code pulse position indicating section, 7 is a complementary code control pulse generating section, 8 is an exclusive OR section, and 9 is a complementary code inserting section. , 10 indicates a delay circuit. The operation of this circuit will be explained using the time chart shown in FIG. The flip-flop used is D-TYPE MASTE.
)(, -8LAVE type.

Now, suppose that the binary signal shown in FIG. 3 (al) is input to terminal 1.
It is shifted to the Qz terminal and output ((c), (e
) ).

The complementary codes Ql (d) and Qt(f) of this output are expressed as 5
i 7m (m=11) is synchronized at 6 by clock pulse C1(g). The AND of these outputs and C1 is taken by 7, and Q((h),Q;(i
), the output is limited to one pulse.The exclusive OR of these two outputs is calculated by 8.

When the signals at the m-l-th bit and the m-th bit have the same sign, that is, 1,1'' or 60,0'', the output Qgxl(j) of 8 becomes O''.If they have different signs, i.e. 1, O" or '0.1", Qi:xt(j
) is “1”. With this Qgxl, the output Q2 of 4
and C2 to control the code that enters the m-th bit. That is, when C1 is l'' and Qgxt is 0'', 'Q2 is set to [QD8], and when C1 is 1', Q-(QD
Take 2).

Further, when C1 is O'', that is, outside the time for inserting a complementary code, the output of Qzxl is 0'' and always takes Q [QDl]. These three outputs are logically summed, shaped using flip-flops, and output.

Because of this operation, the worst case continuous length of the same code can be suppressed to m pits.

Although a circuit that takes the complementary sign of the immediately preceding pit has been shown as an example, the shift register shown in 4 is divided into stages (k-2, 3...
.

Next, an example of the configuration of the l/m frequency divider circuit is shown in FIG. 4(A) for the case of m-11. This circuit uses conventional circuit technology.
It can be configured for any m. Further, the operation of FIG. 4(A) is shown in FIG. 4(B).

FIG. 5 shows the configuration of a transmission system using the circuit of the present invention. 1
Reference numeral 1 designates a speed conversion section, 12 a frame configuration section, 13 a scrambler, 14 a complementary code insertion section, 15 a transmission path, 16 a frame synchronization detection section, 17 a descrambler, and 18 a speed conversion section.

The input binary signal sequence is first speed-converted in step 11, and service pulses for inserting complementary codes, frame synchronization pulses, game monitoring control information, etc. are secured. This signal sequence is constructed into a frame at step 12 and then decoded/dumbed at step 13 by a scrambler. At this time, the service pulse should not be scrambled. Next, the circuit 14 of the present invention periodically inserts a complementary code and sends the suppressed code to the transmission line 15. On the receiving side, frame synchronization is first established at step 16, and then descrambling is performed at step 17. Finally, speed conversion is performed at 18 to remove all service pulses and output only two electric signal sequences. Since the complementary code insertion pulse is not scrambled, descrambling on the receiving side can be performed independently of the complementary code insertion pulse as long as synchronization is achieved, and the complementary code insertion pulse is removed by the speed conversion in 18. .

The power spectrum of the transmission line code constructed by this code conversion circuit is as shown in FIG. 6, and the effect of using this code is shown in FIG. By suppressing the worst-case sequence of the same code ( ), it is possible to suppress an increase in the amount of code amount interference and improve timing characteristics. FIG. 7 shows the results of measuring the code amount and interference tolerance characteristics of an optical repeater operating at 400 MHz. In a scrambler-only transmission code, 24 pits in a row can occur frequently. If this transmission line code is limited to 10 bits, the allowable amount of code interference increases to about 4%. In the design of optical repeaters, the allowable amount of interference is set at 2.5% for deterioration factors such as jitter and discrimination level fluctuations that affect the same code continuity tolerance characteristic. Therefore, it can be seen that stable repeater operation can be obtained by restricting the same code sequence.

(Effects of the Invention) As described above, according to the present invention, since the bit inserted every certain number of bits is the complementary code of the specific bit appearing before it, it is possible to suppress the same code from occurring in the worst case. Therefore, it is possible to suppress an increase in the amount of code amount interference, improve timing characteristics, etc., stabilize the operation of the repeater, and realize a high-speed digital transmission system with good communication quality.

[Brief explanation of the drawing]

Figures 1(A) and 1(B) are block diagrams of a conventional digital transmission system, Figure 1(C) is a block diagram of a code conversion circuit in Figure 1(B), and Figure 2 is a block diagram of the present invention. 3 is an operation time chart of the circuit in FIG. 2, and FIG. 4(A) is an example of an 11 frequency divider circuit.
B) is a diagram showing the operation of the circuit in FIG. 4(A), FIG. 5 is a block diagram of a digital transmission system using the present invention, FIG. FIG. 7 is a diagram showing the code amount interference tolerance characteristics of the optical repeater. 1...Signal input terminal 2...Clock input terminal 3...
...Signal output terminal 4...Shift register 5...L/m frequency divider circuit 6...Complementary code pulse position instruction section 7...
...Complementary code control pulse generator 8...
...Exclusive OR section 9...Complementary code insertion section 10...Delay circuit 11...Speed conversion section 12... ...Frame configuration part 13...
. . . Scrambler 14 . . . Complementary code insertion section 15 . . . Transmission line 16 .
・・・・・・Descrambler 18・・・・・・・Speed conversion unit Patent applicant Nippon Telegraph and Telephone Corporation Patent application representative Patent attorney Megumi Yamamoto −

Claims (1)

[Claims] A shift register having an input terminal for receiving input data, +1 (k is a natural number) cascaded flip-flops connected to the input terminal, and a pulse interval T. Divide the clock pulse by 1 to obtain the pulse width T for each mTo. a frequency divider that generates a pulse C2 of (m is a natural number of 2 or more)
, the final stage output of the shift register and its k(l≦to≦
mT) Exclusive OR A with the output of the previous stage according to the output C2 of the frequency divider. QAC2+QAC! + A code conversion circuit characterized by having a complementary code insertion unit that inserts a complementary code before a pit into the m-th bit of input data according to QAC2 logic, and an output terminal connected to the output thereof.